always @(posedge clk) begin
if (have_out1) begin
`onwrite(out1_r, out1_a) have_out1 <= 0; end
- end
- if (have_out2) begin
+
+ end else if (have_out2) begin
`onwrite(out2_r, out2_a) have_out2 <= 0; end
- end
- if (!have_out1 && !have_out2) begin
+ end else if (!have_out1 && !have_out2) begin
if (!have_a) begin
`onread(in1_r, in1_a) have_a <= 1; a <= in1_d; end
end
end
if (have_a && have_b && have_c) begin
- out1_d <= ((a & b) | (b & c) | (a & c)) << 1;
+ out1_d <= { { ((a & b) | (b & c) | (a & c)) } , 1'b0 };
out2_d <= a ^ b ^ c;
+ have_a <= 0;
+ have_b <= 0;
+ have_c <= 0;
have_out1 <= 1;
have_out2 <= 1;
end
alu2.in1: [*] take, deliver;
alu2.in2: [*] take, deliver;
-alu2.inOp: [*] take, deliver;
+alu2.inOp: take; [*] deliver;
-alu3.out1: take, sendto alu2.in1;
-alu3.out2: take, sendto alu2.in2;
+alu3.out1: [*] take, sendto alu2.in1;
+alu3.out2: [*] take, sendto alu2.in2;
Alu2.ADD: sendto alu2.inOp;
-alu2.out: take, sendto debug.in;
+alu2.out: [*] take, sendto debug.in;
debug.in: [*] take, deliver;