this.module = new Module(getType().toLowerCase());
this.instance = new Module.InstantiatedModule(fleet.getVerilogModule(), module);
for(DockDescription sdbb : sd) {
- if (sdbb.isInputDock()) module.createInputPort(sdbb.getName(), WIDTH_WORD+1);
- else module.createOutputPort(sdbb.getName(), WIDTH_WORD+1, "");
+ if (sdbb.isInputDock()) module.createInputPort(sdbb.getName(), getFleet().getWordWidth()+1);
+ else module.createOutputPort(sdbb.getName(), getFleet().getWordWidth()+1, "");
ports.put(sdbb.getName(), new FpgaDock(this, sdbb));
}
if (getType().toLowerCase().equals("debug"))
- module.createOutputPort("debug_out", WIDTH_WORD, "");
+ module.createOutputPort("debug_out", getFleet().getWordWidth(), "");
}
public Iterator<Dock> iterator() { return (Iterator<Dock>)(Object)ports.values().iterator(); }