cleanups in main.v

diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
index 069e898..51eed13 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ b/src/edu/berkeley/fleet/fpga/main.v
@@ -19,22 +19,7 @@ module main
   ddr1_DM_pin,
   ddr1_DQS,
   ddr1_DQ,
-/*
-  ddr2_ODT_pin,
-  ddr2_Clk_pin,
-  ddr2_Clk_n_pin,
-  ddr2_Addr_pin,
-  ddr2_BankAddr_pin,
-  ddr2_CAS_n_pin,
-  ddr2_CE_pin,
-  ddr2_CS_n_pin,
-  ddr2_RAS_n_pin,
-  ddr2_WE_n_pin,
-  ddr2_DM_pin,
-  ddr2_DQS,
-  ddr2_DQS_n,
-  ddr2_DQ,
-*/
+
   vga_psave,
   vga_hsync,
   vga_vsync,
@@ -67,22 +52,7 @@ module main
   output [3:0]  ddr1_DM_pin;
   inout  [3:0]  ddr1_DQS;
   inout  [31:0] ddr1_DQ;
-/*
-  output        ddr2_ODT_pin;
-  output        ddr2_Clk_pin;
-  output        ddr2_Clk_n_pin;
-  output [12:0] ddr2_Addr_pin;
-  output [1:0]  ddr2_BankAddr_pin;
-  output        ddr2_CAS_n_pin;
-  output        ddr2_CE_pin;
-  output        ddr2_CS_n_pin;
-  output        ddr2_RAS_n_pin;
-  output        ddr2_WE_n_pin;
-  output [7:0]  ddr2_DM_pin;
-  inout  [7:0]  ddr2_DQS;
-  inout  [7:0]  ddr2_DQS_n;
-  inout  [63:0] ddr2_DQ;
-*/
+
   wire  [31:0]  dram_addr;
   wire          dram_addr_r;
   wire          dram_addr_a;
@@ -95,20 +65,6 @@ module main
   wire          dram_read_data_empty;
   wire   [1:0]  dram_read_data_latency;
 
-/*
-  wire  [31:0]  ddr2_addr;
-  wire          ddr2_addr_r;
-  wire          ddr2_addr_a;
-  wire          ddr2_isread;
-  wire  [63:0]  ddr2_write_data;
-  wire          ddr2_write_data_push;
-  wire          ddr2_write_data_full;
-  wire   [63:0] ddr2_read_data;
-  wire          ddr2_read_data_pop;
-  wire          ddr2_read_data_empty;
-  wire   [1:0]  ddr2_read_data_latency;
-*/
-
   output vga_psave;
   output vga_hsync;
   output vga_vsync;
@@ -257,11 +213,7 @@ module main
                 vga_b,
                 vga_clkout
                );
-/*
-   fifo4 my_root(clk, rst,
-                root_in_r,  root_in_a,  root_in_d,
-                root_out_r, root_out_a, data_to_host);
-*/
+
    assign root_out_a                = root_out_a_reg;                
    assign root_in_r                 = root_in_r_reg;
    assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;