better initialization code in main.v

diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
index ead2c40..371f27c 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ b/src/edu/berkeley/fleet/fpga/main.v
@@ -97,8 +97,6 @@ module main
    // fpga -> host
    always @(posedge clk)
    begin
-     data_to_host_write_enable_reg = 0;
-/*
      if (break) begin
        root_out_a_reg = 0;
        data_to_host_write_enable_reg <= 0;
@@ -112,12 +110,16 @@ module main
        data_to_host_r <= 107;
        send_k <= 0;
 */
-     if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
-       data_to_host_write_enable_reg = 1;
+
+     end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
+       data_to_host_write_enable_reg <= 1;
        data_to_host_r <= root_out_d;
        root_out_a_reg = 1;
      end else if (root_out_a_reg && !root_out_r) begin
+       data_to_host_write_enable_reg <= 0;
        root_out_a_reg = 0;
+     end else begin
+       data_to_host_write_enable_reg <= 0;
      end
    end
 
@@ -125,14 +127,20 @@ module main
    always @(posedge clk)
    begin
      ser_rst_r <= 1;
-     data_to_fleet_read_enable_reg = 0;
+     if (break) begin
+       root_in_r_reg <= 0;
+       root_in_d_reg <= 0;
+       data_to_fleet_read_enable_reg <= 0;
+     end else
+  
      if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
-        root_in_r_reg = 1;
-        root_in_d_reg = data_to_fleet;
-        data_to_fleet_read_enable_reg = 1;
+        root_in_r_reg <= 1;
+        root_in_d_reg <= data_to_fleet;
+        data_to_fleet_read_enable_reg <= 1;
      end else begin
+       data_to_fleet_read_enable_reg <= 0;
         if (root_in_a) begin
-          root_in_r_reg = 0;
+          root_in_r_reg <= 0;
         end
      end
    end