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more predictable instance naming in Verilog.java
author
megacz
<adam@megacz.com>
Sun, 1 Mar 2009 16:18:43 +0000
(08:18 -0800)
committer
megacz
<adam@megacz.com>
Sun, 1 Mar 2009 16:18:43 +0000
(08:18 -0800)
src/edu/berkeley/fleet/fpga/verilog/Verilog.java
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diff --git
a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index
3ac807f
..
04985ff
100644
(file)
--- a/
src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/
src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@
-628,7
+628,17
@@
public class Verilog {
public InstantiatedModule(Module thisModule, Module module) {
this.thisModule = thisModule;
this.module = module;
- this.id = thisModule.id++;
+ // CRUDE
+ int id = 0;
+ OUTER: while(true) {
+ for (InstantiatedModule im : thisModule.instantiatedModules)
+ if (im.getName().equals(module.getName()+"_"+id)) {
+ id++;
+ continue OUTER;
+ }
+ break;
+ }
+ this.id = id;
thisModule.instantiatedModules.add(this);
for(String s : module.portorder)
getPort(s);