readjust inMux{sch} select line buffer sizes

diff --git a/electric/dockPartOD.jelib b/electric/dockPartOD.jelib
index fcf3efd..252c94e 100755 (executable)
--- a/electric/dockPartOD.jelib
+++ b/electric/dockPartOD.jelib
@@ -1404,7 +1404,7 @@ Evdd_101||D5G2;|moveLit@0|vdd_63|P
 X
 
 # Cell ringSkipMoveLit;2{sch}
-CringSkipMoveLit;2{sch}||schematic|1224771351449|1227053001292|
+CringSkipMoveLit;2{sch}||schematic|1224771351449|1227140159868|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 IwiresL:bitAssignments;1{sch}|bitAssig@0||-50|2|||D5G4;
 NOff-Page|conn@0||-11|3|||Y|
@@ -1539,7 +1539,7 @@ Awire|net@456|||0|moveLit@1|count|91|-8|pin@336||66|-8
 Awire|net@459|||2700|ringFIFO@0|sout_1@508518759|6|0|conn@26|a|6|17
 Abus|od[1:36]|D5G2;|-0.5|IJ900|pin@321||-16|-8|pin@322||-16|-14
 Abus|od[15:20]|D5G2;|-0.5|IJ900|moveLit@1|od[15:20]|94|-10|pin@264||94|-12
-Awire|olcNZ|D5G2;||2700|pin@304||-6|-31|ringFIFO@0|inz|-6|-12
+Awire|olcZ|D5G2;||2700|pin@304||-6|-31|ringFIFO@0|inz|-6|-12
 Abus|pout[1:18]|D5G2;|-0.5|IJ900|pin@323||19.5|-4|pin@36||19.5|-12
 Ecl[T,F],clS[T,F],rd[T,F],mc||D4G2;|conn@4|a|I
 Edo[epi]||D4G2;|conn@0|a|I
@@ -1557,7 +1557,7 @@ Etorp||D4G2;|conn@24|a|I
 X
 
 # Cell skipCount;1{ic}
-CskipCount;1{ic}||artwork|1222693380973|1226697868849|E
+CskipCount;1{ic}||artwork|1222693380973|1227140145088|E
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NThick-Circle|art@2||9.5|5|1|1||
 Nschematic:Bus_Pin|pin@4||8|-7|-1|-1|R|
@@ -1644,7 +1644,7 @@ EinLO[1:7]|inA[1:6]|D5G2;|pin@4||I
 EinA[7:12]|inB[1:6,8]|D5G2;|pin@68||I
 Ein[1:18]||D5G2;|pin@6||I
 Etorp|kill|D5G2;|pin@18||I
-EolcNZ||D5G2;|pin@12||O
+EolcNZ|olcZ|D5G2;|pin@12||O
 EselLO[Lf,Lo,Co,Dm,Dl,Li]||D5G2;|pin@14||I
 Esel[A]||D5G2;|pin@70||I
 Esin||D5G2;|pin@84||I
@@ -2503,7 +2503,7 @@ Evdd_69||D5G2;|ilc@0|vdd_1|P
 X
 
 # Cell skipCount;3{sch}
-CskipCount;3{sch}||schematic|1226796407146|1226867324341|
+CskipCount;3{sch}||schematic|1226796407146|1227140145088|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||-29.5|-15||||
 NOff-Page|conn@1||-30.5|-9||||
@@ -2606,7 +2606,7 @@ EinA[1:6]||D4G2;|conn@1|a|I
 EinB[1:6,8]||D4G2;|conn@0|a|I
 Ein[1:18]||D4G2;|conn@7|a|I
 Ekill||D4G2;|conn@6|a|I
-EolcNZ||D6G2;|conn@14|y|O
+EolcNZ|olcZ|D6G2;|conn@14|y|O
 EselLO[Lf,Lo,Co,Dm,Dl,Li]||D4G2;|conn@10|a|I
 Esel[A]||D4G2;|conn@2|a|I
 Esin||D4G2;|conn@4|a|I

diff --git a/electric/loopCountL.jelib b/electric/loopCountL.jelib
index c63dc81..4a77ded 100755 (executable)
--- a/electric/loopCountL.jelib
+++ b/electric/loopCountL.jelib
@@ -1,5 +1,5 @@
 # header information:
-HloopCountL|8.08j
+HloopCountL|8.08k
 
 # Views:
 Vicon|ic
@@ -4492,7 +4492,7 @@ Evdd_29||D5G2;|pinsVddG@10|vdd_1|P
 X
 
 # Cell inMux;3{sch}
-CinMux;3{sch}||schematic|1216238895693|1226764585650|
+CinMux;3{sch}||schematic|1216238895693|1227223871897|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||-5.5|-7.5||||
 NOff-Page|conn@1||-6.5|8||||
@@ -4502,8 +4502,8 @@ NWire_Con|conn@4||-12.5|2||||
 IextZero;1{ic}|extZero@0||-35|-1|R||D5G4;
 NGround|gnd@0||-12.5|-3||||
 IinMux;1{ic}|inMux@0||32.5|14.5|||D5G4;
-IredFour:inv;1{ic}|inv@0||-8|15.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
-IredFour:inv;1{ic}|inv@1||7|15.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S20|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFour:inv;1{ic}|inv@0||-8|15.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S80|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFour:inv;1{ic}|inv@1||7|15.5|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S40|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IgatesK:mux10;1{ic}|mux[1:6,8]|D5G3;X6;Y4;|6|0|||D5G4;
 Ngeneric:Invisible-Pin|pin@0||-0.5|37|||||ART_message(D5G4;)Sprovides the inverted inputs to the loop counters
 Ngeneric:Invisible-Pin|pin@1||-0.5|42|||||ART_message(D5G6;)SinMux

diff --git a/testCode/hardwareBugs.txt b/testCode/hardwareBugs.txt
index cc007e3..0cdba11 100644 (file)
--- a/testCode/hardwareBugs.txt
+++ b/testCode/hardwareBugs.txt
@@ -8,7 +8,7 @@ Fixed:
 slow. When the set instruction loads a nonzero value into the OLC or
 the ILC Marina behaves as if the value is zero.
 Noted: 11 Nov 2008
-Fixed: 19 Nov 2008
+Fixed: 
 
 3) After the ILC decrements to zero, subsequent move instructions fail
 to execute at all. According to adm33 subsequent move instructions are

diff --git a/testCode/marina.spi b/testCode/marina.spi
index f132236..c680d7a 100644 (file)
--- a/testCode/marina.spi
+++ b/testCode/marina.spi
@@ -1,7 +1,7 @@
 *** SPICE deck for cell marina{sch} from library marinaL
 *** Created on Mon Nov 17, 2008 08:47:24
 *** Last revised on Tue Nov 18, 2008 12:17:39
-*** Written on Wed Nov 19, 2008 16:09:17 by Electric VLSI Design System, 
+*** Written on Thu Nov 20, 2008 15:31:29 by Electric VLSI Design System, 
 *version 8.08k
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
@@ -8173,6 +8173,12 @@ Xwire90@0 net@5 net@1 wire90-406_3-layer_1-width_3
 Xwire90@1 net@3 net@6 wire90-406_3-layer_1-width_3
 .ENDS extZero
 
+*** CELL: redFour:inv{sch}
+.SUBCKT inv-X_40 in out
+XNMOS@0 out in gnd NMOSx-X_40
+XPMOS@0 out in vdd PMOSx-X_40
+.ENDS inv-X_40
+
 *** CELL: orangeTSMC090nm:wire{sch}
 .SUBCKT wire-C_0_011f-2740_3-R_34_667m a b
 Ccap@0 gnd net@14 10.048f
@@ -8210,8 +8216,8 @@ Xwire@0 a b wire-C_0_011f-2463-R_34_667m
 +inB[4] inB[5] inB[6] inB[8] out[1] out[2] out[3] out[4] out[5] out[6] out[7] 
 +out[8] sel[A]
 XextZero@0 out[1] out[2] out[3] out[4] out[5] out[6] out[7] extZero
-Xinv@0 sel[A] net@10 inv-X_20
-Xinv@1 s[F] net@12 inv-X_20
+Xinv@0 sel[A] net@10 inv-X_80
+Xinv@1 s[F] net@12 inv-X_40
 Xmux[1] inA[1] inB[1] out[1] s[F] s[T] mux10
 Xmux[2] inA[2] inB[2] out[2] s[F] s[T] mux10
 Xmux[3] inA[3] inB[3] out[3] s[F] s[T] mux10
@@ -8972,12 +8978,6 @@ Xwire90@83 net@954 net@964 wire90-353_6-layer_1-width_3
 Xwire90@84 net@955 net@959 wire90-309_5-layer_1-width_3
 .ENDS array
 
-*** CELL: redFour:inv{sch}
-.SUBCKT inv-X_40 in out
-XNMOS@0 out in gnd NMOSx-X_40
-XPMOS@0 out in vdd PMOSx-X_40
-.ENDS inv-X_40
-
 *** CELL: orangeTSMC090nm:wire{sch}
 .SUBCKT wire-C_0_011f-262_8-R_34_667m a b
 Ccap@0 gnd net@14 0.964f
@@ -9427,7 +9427,7 @@ Xwire90@19 loadFlags[F] net@335 wire90-439_9-layer_1-width_3
 +fire[m2] flag[C] ilc[cnt] ilc[dLO] ilc[i] ilc[zLO] ilc[zoo] inA[1] inA[2] 
 +inA[3] inA[4] inA[5] inA[6] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[8] 
 +in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[1] in[2] 
-+in[3] in[4] in[5] in[6] in[7] in[8] in[9] kill mc olcNZ rd[F] rd[T] selLO[Co] 
++in[3] in[4] in[5] in[6] in[7] in[8] in[9] kill mc olcZ rd[F] rd[T] selLO[Co] 
 +selLO[Dl] selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo] sel[A] sin sout
 XilcZoo@0 net@18[8] net@18[7] net@18[6] net@18[5] net@18[4] net@18[3] 
 +ilc[cnt] ilc[dLO] ilc[i] net@26 ilc[zLO] ilc[zoo] inLO[1] inLO[2] inLO[3] 
@@ -9448,7 +9448,7 @@ XscanKx9@0 clS[F] clS[T] cl[F] cl[T] net@18[8] net@18[7] net@18[6] net@18[5]
 XskipAll@0 do[L] do[M] fire[ODE] fire[m1] fire[m2] net@51[1] net@51[0] 
 +flag[C] net@26 inLO[7] in[10] in[11] in[12] in[13] in[14] in[15] in[16] 
 +in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] kill mc 
-+olcNZ net@24[1] net@24[0] net@24[3] net@24[2] selLO[Co] selLO[Dl] selLO[Dm] 
++olcZ net@24[1] net@24[0] net@24[3] net@24[2] selLO[Co] selLO[Dl] selLO[Dm] 
 +selLO[Lf] selLO[Li] selLO[Lo] net@30 skipAll
 .ENDS skipCount