On x86[-64], MachCodeGen uses the old XOR trick to zero a register.
This patch makes regUsage not list the register as an input in this
case.
Listing the register as an input for the instruction could make it
appear like an unitialised value, which is bad because unitialised
values can cause the register allocator to panic (at least in the
presence of a loop).
IDIV sz op -> mkRU (eax:edx:use_R op) [eax,edx]
AND sz src dst -> usageRM src dst
OR sz src dst -> usageRM src dst
+ XOR sz (OpReg src) (OpReg dst)
+ | src == dst -> mkRU [] [dst]
XOR sz src dst -> usageRM src dst
NOT sz op -> usageM op
NEGI sz op -> usageM op