change olc_in to flag_z (single bit)

diff --git a/src/edu/berkeley/fleet/fpga/FpgaDock.java b/src/edu/berkeley/fleet/fpga/FpgaDock.java
index 57ef338..b4f44cc 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/FpgaDock.java
+++ b/src/edu/berkeley/fleet/fpga/FpgaDock.java
@@ -89,7 +89,7 @@ public class FpgaDock extends FleetTwoDock implements FabricElement {
             super("requeue");
             Module.SourcePort fabric_in = createInputPort ("fabric_in",  fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
             Module.SourcePort ondeck_in = createInputPort ("ondeck_in",  fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
-            Module.SourcePort olc_in    = createInputPort ("olc_in",     fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth);
+            Module.SourcePort flag_z    = createInputPort ("flag_z",     1);
             Module.SinkPort   out       = createOutputPort("out",        fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth, "");
             out.forceNoLatch = true;
 
@@ -101,8 +101,8 @@ public class FpgaDock extends FleetTwoDock implements FabricElement {
             addPreCrap("assign out = "+circulating.isEmpty()+" ? "+fabric_in.getName()+" : "+ondeck_in.getName()+";");
 
             // always: discard one-shot instructions
-            new Event(new Object[] { ondeck_in, /*olc_in,*/ fpga.OS.verilog(ondeck_in.getName()) },
-                      new Action[] { ondeck_in, /*olc_in */});
+            new Event(new Object[] { ondeck_in, fpga.OS.verilog(ondeck_in.getName()) },
+                      new Action[] { ondeck_in, });
 
             new Event(new Object[] { doResetFabric.isFull(),  out },
                       new Action[] { doResetFabric.doDrain(), fabric_in });
@@ -113,14 +113,14 @@ public class FpgaDock extends FleetTwoDock implements FabricElement {
                       new Action[] { circulating.doFill(),                   fabric_in });
             new Event(new Object[] { circulating.isEmpty(),                  fabric_in, "!("+fpga.TAIL.verilog(fabric_in.getName())+")", doResetFabric.isEmpty() },
                       new Action[] {                                         out, doResetFabric.doFill() });
-            new Event(new Object[] { using.isEmpty(),                        ondeck_in, /*olc_in,*/   "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in==0" },
-                      new Action[] {                                         ondeck_in, /*olc_in */ });
-            new Event(new Object[] { using.isEmpty(),                        ondeck_in, /*olc_in,*/   "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in!=0" },
+            new Event(new Object[] { using.isEmpty(),                        ondeck_in, "!("+fpga.OS.verilog(ondeck_in.getName())+")", "flag_z" },
+                      new Action[] {                                         ondeck_in, });
+            new Event(new Object[] { using.isEmpty(),                        ondeck_in, "!("+fpga.OS.verilog(ondeck_in.getName())+")", "!flag_z" },
                       new Action[] { using.doFill() });
-            new Event(new Object[] { circulating.isFull(),  using.isFull(),  ondeck_in, /*olc_in,*/   "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in==0" },
-                      new Action[] { circulating.doDrain(), using.doDrain(), ondeck_in, /*olc_in */});
-            new Event(new Object[] { circulating.isFull(),  using.isFull(),  ondeck_in, /*olc_in,*/   "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in!=0", doResetOndeck.isEmpty() },
-                      new Action[] {                                         out, /*olc_in,*/ doResetOndeck.doFill() });
+            new Event(new Object[] { circulating.isFull(),  using.isFull(),  ondeck_in, "!("+fpga.OS.verilog(ondeck_in.getName())+")", "flag_z" },
+                      new Action[] { circulating.doDrain(), using.doDrain(), ondeck_in, });
+            new Event(new Object[] { circulating.isFull(),  using.isFull(),  ondeck_in, "!("+fpga.OS.verilog(ondeck_in.getName())+")", "!flag_z", doResetOndeck.isEmpty() },
+                      new Action[] {                                         out, doResetOndeck.doFill() });
 
         }
     }
@@ -200,7 +200,7 @@ public class FpgaDock extends FleetTwoDock implements FabricElement {
             Module.InstantiatedModule requeue_module = new Module.InstantiatedModule(this, new RequeueModule());
             Module.SinkPort   requeue_fabric_in = requeue_module.getInputPort("fabric_in");
             Module.SinkPort   requeue_ondeck    = requeue_module.getInputPort("ondeck_in");
-            Module.SinkPort   requeue_olc_in    = requeue_module.getInputPort("olc_in");
+            Module.SinkPort   requeue_flag_z    = requeue_module.getInputPort("flag_z");
             Module.SourcePort requeue_out       = requeue_module.getOutputPort("out");
 
             efifo_out.connect(requeue_fabric_in);
@@ -212,7 +212,7 @@ public class FpgaDock extends FleetTwoDock implements FabricElement {
             addPreCrap("assign data_latch_output = " + (inbox ? data_out.getName() : fpga.PACKET_DATA.verilogVal(data_out.getName()))+";");
             addPreCrap("wire ["+(Math.max(ilc.width,olc.width)-1)+":0] decremented;");
             addPreCrap("assign decremented = ("+fpga.SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName())+" ? {1'b0, olc} : ilc)-1;");
-            addPreCrap("assign "+requeue_olc_in.getName()+" = olc;");
+            addPreCrap("assign "+requeue_flag_z.getName()+" = (olc==0);");
 
             Assignable data_latch    = new SimpleAssignable(inbox ? data_out.getName() : fpga.PACKET_DATA.verilogVal(data_out.getName()));
             String data_latch_input  = inbox ? data_in.getName() : data_in.getName();