factor out verilog headers on Alu2 ship

diff --git a/Makefile b/Makefile
index 76dc897..a13ec23 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -53,7 +53,7 @@ runfpga: fleet.jar
 mrunfpga: fleet.jar build/main.bit
        mkdir -p build
        rsync -zare ssh --progress --verbose build/main.bit root@bee441.cs.berkeley.edu:/var/slipway/megacz.bit
-       $(java) -jar fleet.jar bitfile=megacz.bit target=fpga run
+       $(java) -jar fleet.jar bitfile=megacz.bit target=fpga test tests
 
 build/fabric.v: $(verilog_files) src/edu/berkeley/fleet/slipway/Slipway.java
        make fleet.jar

diff --git a/ships/Alu2.ship b/ships/Alu2.ship
index 5e944b9..ab4044e 100644 (file)
--- a/ships/Alu2.ship
+++ b/ships/Alu2.ship
@@ -60,19 +60,13 @@ public void service() {
 == FleetSim ==============================================================
 
 == FPGA ==============================================================
-`include "macros.v"
-
-module alu2 (clk, 
-             a_r,    a_a_,  a_d,
-             b_r,    b_a_,  b_d,
-             op_r,   op_a_, op_d,
-             out_r_, out_a, out_d_);
 
   input  clk;
-  `input(a_r,    a_a,    a_a_,  [(`DATAWIDTH-1):0], a_d)
-  `input(b_r,    b_a,    b_a_,  [(`DATAWIDTH-1):0], b_d)
-  `input(op_r,   op_a,   op_a_, [(`DATAWIDTH-1):0], op_d)
+  `input(in1_r,    in1_a,    in1_a_,  [(`DATAWIDTH-1):0], in1_d)
+  `input(in2_r,    in2_a,    in2_a_,  [(`DATAWIDTH-1):0], in2_d)
+  `input(inOp_r,   inOp_a,   inOp_a_, [(`DATAWIDTH-1):0], inOp_d)
   `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
+
   `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
 
   reg                    have_a;
@@ -84,13 +78,13 @@ module alu2 (clk,
 
   always @(posedge clk) begin
     if (!have_a) begin
-      `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
+      `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
       end
     if (!have_b) begin
-      `onread(b_r, b_a) have_b = 1; reg_b = b_d; end
+      `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
       end
     if (!have_op) begin
-      `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
+      `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
       end
   
     if (have_a && have_b && have_op) begin

diff --git a/ships/Execute.ship b/ships/Execute.ship
index 4fe66a4..5fd49d0 100644 (file)
--- a/ships/Execute.ship
+++ b/ships/Execute.ship
@@ -14,17 +14,17 @@ data  in:   in
 == FPGA ==============================================================
 `include "macros.v"
 
-module execute (clk, command_r,   command_a_, command_d,
+module execute (clk, in_r,     in_a_,   in_d,
                      ihorn_r_, ihorn_a, ihorn_d_,
                      dhorn_r_, dhorn_a, dhorn_d_
                );
   input clk;
 
-  `input(command_r,   command_a,   command_a_, [(`DATAWIDTH-1):0], command_d)
+  `input(in_r,     in_a,     in_a_,   [(`DATAWIDTH-1):0],         in_d)
   `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
   `defreg(ihorn_d_,                   [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
-  `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
-  `defreg(dhorn_d_,                   [(`PACKET_WIDTH-1):0], dhorn_d)
+  `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0],      dhorn_d_)
+  `defreg(dhorn_d_,                   [(`PACKET_WIDTH-1):0],      dhorn_d)
 
   reg ihorn_full;
   reg dhorn_full;
@@ -39,17 +39,17 @@ module execute (clk, command_r,   command_a_, command_d,
         dhorn_full = 0;
       end
     end else begin
-      `onread(command_r, command_a)
-        case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
+      `onread(in_r, in_a)
+        case (in_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
           0: begin
               ihorn_full  = 1;
-              ihorn_d = command_d;
+              ihorn_d = in_d;
               end
           //01:
           2: begin
               dhorn_full  = 1;
-              `packet_data(dhorn_d) = command_d[23:0];
-              `packet_dest(dhorn_d) = command_d[34:24];
+              `packet_data(dhorn_d) = in_d[23:0];
+              `packet_dest(dhorn_d) = in_d[34:24];
               end
           //11:
         endcase

diff --git a/ships/Lut.ship b/ships/Lut.ship
index 4ae7953..8e1b90a 100644 (file)
--- a/ships/Lut.ship
+++ b/ships/Lut.ship
@@ -3,6 +3,7 @@ ship: Lut
 == Ports ===========================================================
 data  in:   in1
 data  in:   in2
+data  in:   in3
 data  in:   inLut
 
 data  out:  out

diff --git a/ships/Shift.ship b/ships/Shift.ship
index bbe50be..c3c8142 100644 (file)
--- a/ships/Shift.ship
+++ b/ships/Shift.ship
@@ -13,6 +13,7 @@ To Do:
 - rotate (in addition to shift)?
 - rotate, shift, and sign-extend subfields of a word?
 - scan for lowest/highest bit which is set/clear?
+- bitfields crossing two words
 
 == Fleeterpreter ====================================================
     public void service() {

diff --git a/src/edu/berkeley/fleet/slipway/Slipway.java b/src/edu/berkeley/fleet/slipway/Slipway.java
index 26a7dd2..a97d404 100644 (file)
--- a/src/edu/berkeley/fleet/slipway/Slipway.java
+++ b/src/edu/berkeley/fleet/slipway/Slipway.java
@@ -313,6 +313,28 @@ public class Slipway extends Interpreter {
             FileOutputStream out = new FileOutputStream(outf);
             PrintWriter pw = new PrintWriter(out);
 
+            if (filename.equals("alu2")) {
+                pw.println("`include \"macros.v\"");
+                pw.println();
+                pw.println("module " + filename + "( clk");
+                for(ShipDescription.BenkoBox bb : sd.benkoBoxes) {
+                    if (bb.ports.length > 1) throw new RuntimeException("gah");
+                    String bb_name = bb.ports[0];
+                    pw.print("        ");
+                    if (bb.inbox) {
+                        pw.print(", " + bb_name+"_r");
+                        pw.print(", " + bb_name+"_a_");
+                        pw.print(", " + bb_name+"_d");
+                    } else {
+                        pw.print(", " + bb_name+"_r_");
+                        pw.print(", " + bb_name+"_a");
+                        pw.print(", " + bb_name+"_d_");
+                    }
+                    pw.println();
+                }
+                pw.println("        );");
+            }
+
             pw.println(sd.sections.get("fpga"));
             pw.flush();
             pw.close();