if (read_buf_tail < read_buf_head) return (read_buf_head-read_buf_tail) < (BUFSIZE/2);\r
return (read_buf_tail-read_buf_head) > (BUFSIZE/2);\r
}\r
-/*\r
+\r
inline int write_full() { return inc(write_buf_tail)==write_buf_head; }\r
inline int write_empty() { return write_buf_head==write_buf_tail; }\r
inline int write_nearlyFull() {\r
if (write_buf_tail < write_buf_head) return (write_buf_head-write_buf_tail) < (BUFSIZE/2);\r
return (write_buf_tail-write_buf_head) > (BUFSIZE/2);\r
}\r
-*/\r
+\r
inline char recv() {\r
int q;\r
char ret;\r
return ret;\r
}\r
\r
+ISR(SIG_UART1_DATA) {\r
+ //if (write_empty()) return;\r
+ portd(1, 0);\r
+ _delay_ms(10);\r
+ portd(1, 1);\r
+ _delay_ms(10);\r
+ UCSR1B &= ~(1 << UDRIE1);\r
+ sei();\r
+}\r
+\r
void send(char c) {\r
\r
write_buf[write_buf_tail] = c;\r
write_buf_tail = inc(write_buf_tail);\r
\r
- char ret = write_buf[write_buf_head];\r
- write_buf_head = inc(write_buf_head);\r
+ UCSR1B |= (1 << UDRIE1);\r
\r
while(!(UCSR1A & (1 << UDRE1))); /* Wait for data Regiester to be empty */\r
+ char ret = write_buf[write_buf_head];\r
+ write_buf_head = inc(write_buf_head);\r
UDR1 = (int)ret;\r
}\r
\r