only generate break signal if rx_bit_cnt==9 to avoid mid-transmit resets

diff --git a/src/edu/berkeley/fleet/fpga/sasc_top.v b/src/edu/berkeley/fleet/fpga/sasc_top.v
index 2f5a1ae..a5dfa77 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/sasc_top.v
+++ b/src/edu/berkeley/fleet/fpga/sasc_top.v
@@ -245,7 +245,7 @@ assign break_o = break_r;
 always @(posedge clk)
        rx_valid <= #1 (rx_bit_cnt == 4'h9) && (rxd_s == STOP_BIT);
 always @(posedge clk)
-       break_r  <= #1 /*(rx_bit_cnt == 4'h9) &&*/ (rxr[9:0]==10'b0) && (rxd_dly == 5'b0) && (rxd_s == 0) && (rxd_r == 0);
+       break_r  <= #1 (rx_bit_cnt == 4'h9) && (rxr[9:0]==10'b0) && (rxd_dly == 5'b0) && (rxd_s == 0) && (rxd_r == 0);
 
 always @(posedge clk)
        rx_valid_r <= #1 rx_valid;