eliminate use of bram14 in Memory.ship

diff --git a/ships/Memory.ship b/ships/Memory.ship
index 6291093..416d070 100644 (file)
--- a/ships/Memory.ship
+++ b/ships/Memory.ship
@@ -161,23 +161,42 @@ sequence guarantee problem mentioned in the previous paragraph.
 
 == FPGA ==============================================================
 
+  reg                              write_flag;
+  reg [(`BRAM_ADDR_WIDTH-1):0]     cursor;
+  wire [(`BRAM_ADDR_WIDTH-1):0]   addr1;
+
+  // bram //////////////////////////////////////////////////////////////////////////////
+`define BRAM_ADDR_WIDTH 14
+`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))
+
+    reg    [(`WORDWIDTH-1):0]       ram [((`BRAM_SIZE)-1):0];
+    reg    [(`BRAM_ADDR_WIDTH-1):0] read_a; 
+    reg    [(`BRAM_ADDR_WIDTH-1):0] read_dpra; 
+    always @(posedge clk) begin 
+        if (write_flag) 
+            ram[addr1] <= inDataWrite_d; 
+        read_a <= addr1; 
+        read_dpra <= cursor; 
+    end
+
+  ////////////////////////////////////////////////////////////////////////////////
+
   wire [(`WORDWIDTH-1):0] out1;
   wire [(`WORDWIDTH-1):0] out2;
 
+  assign out1 = ram[read_a]; 
+  assign out2 = ram[read_dpra]; 
+
   reg [(`CODEBAG_SIZE_BITS-1):0]   counter;
-  reg [(`BRAM_ADDR_WIDTH-1):0]     cursor;
   initial cursor = 0;
   initial counter = 0;
 
-  reg                              write_flag;
   reg                              out_w;
   reg                              dispatching_cbd;
   initial write_flag = 0;
   initial dispatching_cbd = 0;
 
-  wire [(`BRAM_ADDR_WIDTH-1):0]   addr1;
   assign addr1 = write_flag ? inAddrWrite_d[(`WORDWIDTH-1):0] : inAddrRead_d[(`WORDWIDTH-1):0];
-  bram14 mybram(clk, rst, write_flag, addr1, cursor, inDataWrite_d, out1, out2);
 
   assign out_d_ = { out_w , (dispatching_cbd ? out2 : out1) };