new ConditionalAction(ondeck.testMask(fpga.DO), data_out),
new ConditionalAction(ondeck.testMask(fpga.FLUSH), data_out),
inbox
- ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+fpga.getWordWidth()+"]"), new SimpleValue(fpga.FLUSH.verilog(ondeck.getName())+"?1:0"))
- : new ConditionalAction(ondeck.testMask(fpga.DI), new AssignAction(flag_c, new SimpleValue(data_latch_input.getVerilog()+"["+fpga.getWordWidth()+"]"))),
+ ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+fpga.getWordWidth()+"]"),
+ new SimpleValue(fpga.FLUSH.verilog(ondeck.getName())+"?1:0"))
+ : null,
new ConditionalAction(ondeck.testMask(fpga.TI), token_in),
new ConditionalAction(ondeck.testMask(fpga.TO), token_out),
new ConditionalAction(ondeck.testMask(fpga.DC), new AssignAction(data_latch, data_latch_input)),