reg [(`PACKET_WIDTH-1):0] extrabits;
always @(posedge clk) begin
+ if (!rst) begin
+ have_a = 0;
+ have_op = 0;
+ `reset
+ end else begin
if (!have_a) begin
`onread(in_r, in_a) have_a = 1; reg_a = in_d; end
end
have_op = 0;
end
end
+ end
end
== Test ==============================================================================
reg [(`DATAWIDTH-1):0] reg_op;
always @(posedge clk) begin
+ if (!rst) begin
+ have_a = 0;
+ have_b = 0;
+ have_op = 0;
+ end else begin
if (!have_a) begin
`onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
end
end
end
end
+ end
== Test ==============================================================================
// expected output
reg wrote; initial wrote = 0;
always @(posedge clk) begin
+ if (!rst) begin
+ `reset
+ mode = 0;
+ have_in1 <= 0;
+ have_in2 <= 0;
+ have_in3 <= 0;
+ keep_in1 <= 0;
+ keep_in2 <= 0;
+ keep_in3 <= 0;
+ have_out1 <= 0;
+ have_out2 <= 0;
+ bitstorage = 0;
+ bitstorage_count <= 0;
+ wrote = 0;
+ end else begin
wrote = 0;
if (bitstorage_count >= `DATAWIDTH) begin
outBits_d = bitstorage[(`DATAWIDTH-1):0];
have_in2 <= 0;
have_in3 <= 0;
end
+ end
end
== Test ========================================================================
-
#ship alu3 : Alu3
#ship lut3 : Lut3
#ship bitfifo : BitFifo
initial bitstorage_count = 0;
always @(posedge clk) begin
+ if (!rst) begin
+ bitstorage_count <= 0;
+ enqueue_remaining <= 0;
+ dequeue_remaining <= 0;
+ `reset
+ end else begin
if (!in_r && in_a) in_a <= 0;
if (!inOp_r && inOp_a) inOp_a <= 0;
if (!outOp_r && outOp_a) outOp_a <= 0;
out_d <= (outOp_d[`OP_SIGNEXT] && bitstorage[outOp_d[`OP_DROP]]) ? 37'b1111111111111111111111111111111111111 : 0;
end
+ end
end
reg neg;
always @(posedge clk) begin
+ if (!rst) begin
+ `reset
+ have_in1 = 0;
+ have_in2 = 0;
+ have_in = 0;
+ have_out1 = 0;
+ have_out2 = 0;
+ zero = 0;
+ pos = 0;
+ neg = 0;
+ end else begin
if (!have_in1) begin
`onread(in1_r, in1_a) have_in1 <= 1; reg_in1 <= in1_d; end
end
end
+ end
end
endgenerate
always @(posedge clk) begin
+ if (!rst) begin
+ have_in1 = 0;
+ have_in2 = 0;
+ have_in3 = 0;
+ have_inLut = 0;
+ `reset
+ end else begin
if (!have_in1) begin
`onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
end else
have_inLut = 0;
end
end
+ end
end
always @(posedge clk /*or negedge rst*/) begin
if (!rst) begin
+
+/*
+ in_addr_a = 1;
+ write_addr_a = 1;
+ write_data_a = 1;
+ stride_a <= 1;
+ count_a <= 1;
+ preload_a <= 1;
+ cbd_a <= 1;
+*/
+ out_r <= 0;
+ ihorn_r <= 0;
+ dhorn_r <= 0;
+
ihorn_full <= 0;
dhorn_full <= 0;
command_valid <= 0;
== Test ====================================================
+#skip
#ship stack : Stack
-#ship debug : Debug
+#ship stack : Debug
#expect 4
#expect 3
createShip("Alu2", "alu2a");
createShip("BitFifo", "bitfifo");
// above is the minimal ship set needed to run the regression suite, excluding "ships" tests
- /*
- createShip("Fifo", "fifo3");
createShip("Alu1", "alu1");
createShip("Lut3", "lut3");
- createShip("Choice", "Choice");
- createShip("Stack", "Stack");
createShip("Alu3", "alu3");
+
+ /*
+ createShip("Stack", "Stack");
+ createShip("Fifo", "fifo3");
+ createShip("Choice", "Choice");
*/
// above is the minimal ship set needed to run the regression suite, including "ships" tests
!"execute".equals(filename) &&
!"memory".equals(filename) &&
!"fifo".equals(filename);
+
if (auto) {
pw.println("`include \"macros.v\"");
pw.println();
+
+ pw.print("`define reset ");
+ for(PumpDescription bb : sd) {
+ String bb_name = bb.getName();
+ if (bb.isInbox()) {
+ pw.print(bb_name+"_a <= 1; ");
+ } else {
+ pw.print(bb_name+"_r <= 0; ");
+ }
+ }
+ pw.println();
+
pw.println("module " + filename + "( clk, rst ");
for(PumpDescription bb : sd) {
String bb_name = bb.getName();
public String getVerilogName() { return name; }
public Value getBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
public Assignable getAssignableBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
+ public String doReset() { return name+"<=0;"; }
public void dump(PrintWriter pw) {
pw.println(" reg ["+(width-1)+":0] "+name+";");
pw.println(" initial "+name+"=0;");
pw.println(precrap);
pw.println("always @(posedge clk) begin");
pw.println(" if (!rst) begin");
+ for(Latch l : latches.values())
+ pw.println(l.doReset());
for(StateWire sw : statewires.values())
pw.println(sw.doReset());
for(Port p : ports.values()) {
wire clk;
assign clk = sys_clk_pin;
wire break_o;
+ wire break;
reg break_last;
wire rst;
assign rst = sys_rst_pin;
wire ser_rst;
reg ser_rst_r;
initial ser_rst_r = 0;
- assign ser_rst = rst & ser_rst_r;
+ assign ser_rst = (rst & ser_rst_r);
wire sio_ce;
wire sio_ce_x4;