replace addPreCrap() with noDriveLatches in FpgaDock.java

diff --git a/src/edu/berkeley/fleet/fpga/FpgaDock.java b/src/edu/berkeley/fleet/fpga/FpgaDock.java
index 7de5618..285f2d0 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/FpgaDock.java
+++ b/src/edu/berkeley/fleet/fpga/FpgaDock.java
@@ -71,14 +71,19 @@ public class FpgaDock extends FleetTwoDock implements FabricElement {
             // FIXME: assumes DISPATCH_PATH is at top of word!!!
             Module.SinkPort   out     = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth, "");
             Module.SinkPort   torpedo = createOutputPort("torpedo", 0, "");
-            in.hasLatch = false;
-            out.hasLatch = false;
-            torpedo.hasLatch = false;
+            Module.StateWire  busy    = new StateWire("busy", false);
+            out.forceNoLatch = true;
+
+            // FIXME: okay to eliminate torpedoWaiting
+
+            new Event(new Object[] { in, busy.isFull(), out },
+                      new Action[] { in, busy.doDrain() });
+            new Event(new Object[] { in, busy.isEmpty(), out, torpedo, fpga.PACKET_TOKEN.verilogVal("in") },
+                      new Action[] { in,                      torpedo });
+            new Event(new Object[] { in, busy.isEmpty(), out,      "!"+fpga.PACKET_TOKEN.verilogVal("in") },
+                      new Action[] {     busy.doFill(),  out });
 
             addPreCrap("assign out        = "+fpga.PACKET_DATA.verilogVal("in")+";");
-            addPreCrap("assign out_r      = in_r && !("+fpga.PACKET_TOKEN.verilogVal("in")+");");
-            addPreCrap("assign torpedo_r  = in_r &&   "+fpga.PACKET_TOKEN.verilogVal("in")+";");
-            addPreCrap("assign in_a       = out_a || torpedo_a;");
         }
     }