autogenerate parts of Alu1, Alu2, Lut3 verilog

diff --git a/ships/Alu1.ship b/ships/Alu1.ship
index 7ee1de9..abaee8a 100644 (file)
--- a/ships/Alu1.ship
+++ b/ships/Alu1.ship
@@ -16,41 +16,26 @@ DEC:
 == TeX ==============================================================
 == Fleeterpreter ====================================================
     public void service() {
-/*
-        if (in.dataReadyForShip() && op.dataReadyForShip()) {
-            int data   = in.removeDataForShip();
-            int opcode = in.removeDataForShip();
+        if (box_in.dataReadyForShip() && box_inOp.dataReadyForShip()) {
+            int data   = box_in.removeDataForShip();
+            int opcode = box_inOp.removeDataForShip();
             switch(opcode) {
-                case 0: out.addDataFromShip(-1 * data);      // NEG
+                case 0: box_out.addDataFromShip(-1 * data);      // NEG
                     break;
-                case 1: out.addDataFromShip(data+1);         // INC
+                case 1: box_out.addDataFromShip(data+1);         // INC
                     break;
-                case 2: out.addDataFromShip(data-1);         // DEC
+                case 2: box_out.addDataFromShip(data-1);         // DEC
                     break;
-                case 3: out.addDataFromShip(Math.abs(data)); // ABS
+                case 3: box_out.addDataFromShip(Math.abs(data)); // ABS
                     break;
-                default: out.addDataFromShip(0);
+                default: box_out.addDataFromShip(0);
                     break;
             }
         }
-*/
     }
 
 == FleetSim ==============================================================
 == FPGA ==============================================================
-`include "macros.v"
-
-module alu1 (clk, 
-             a_r,    a_a_,  a_d,
-             op_r,   op_a_, op_d,
-             out_r_, out_a, out_d_);
-
-  input  clk;
-  `input(a_r,    a_a,    a_a_,  [(`DATAWIDTH-1):0], a_d)
-  `input(op_r,   op_a,   op_a_, [(`DATAWIDTH-1):0], op_d)
-  `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
-  `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
-
   reg                    have_a;
   reg [(`DATAWIDTH-1):0] reg_a;
   reg                    have_op;
@@ -58,10 +43,10 @@ module alu1 (clk,
 
   always @(posedge clk) begin
     if (!have_a) begin
-      `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
+      `onread(in_r, in_a) have_a = 1; reg_a = in_d; end
       end
     if (!have_op) begin
-      `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
+      `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
       end
   
     if (have_a && have_op) begin
@@ -70,6 +55,7 @@ module alu1 (clk,
         1: out_d = reg_a+1;
         2: out_d = reg_a-1;
         3: out_d = (reg_a<0) ? (-reg_a) : reg_a;
+        4: out_d = 37'b1111111111111111111111111111111111111;
         default: out_d = 0;
       endcase        
       `onwrite(out_r, out_a)
@@ -79,8 +65,6 @@ module alu1 (clk,
     end
   end
 
-endmodule
-
 
 == Contributors =========================================================
 Adam Megacz <megacz@cs.berkeley.edu>

diff --git a/ships/Alu2.ship b/ships/Alu2.ship
index 392be46..ea5ffcb 100644 (file)
--- a/ships/Alu2.ship
+++ b/ships/Alu2.ship
@@ -57,14 +57,6 @@ public void service() {
 
 == FPGA ==============================================================
 
-  input  clk;
-  `input(in1_r,    in1_a,    in1_a_,  [(`DATAWIDTH-1):0], in1_d)
-  `input(in2_r,    in2_a,    in2_a_,  [(`DATAWIDTH-1):0], in2_d)
-  `input(inOp_r,   inOp_a,   inOp_a_, [(`DATAWIDTH-1):0], inOp_d)
-  `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
-
-  `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
-
   reg                    have_a;
   reg [(`DATAWIDTH-1):0] reg_a;
   reg                    have_b;
@@ -87,9 +79,6 @@ public void service() {
       case (reg_op)
         0: out_d = reg_a + reg_b;
         1: out_d = reg_a - reg_b;
-        //2: out_d = reg_a * reg_b; // will not synthesize --AM
-        //3: out_d = reg_a / reg_b; // will not synthesize --AM
-        //4: out_d = reg_a % reg_b; // will not synthesize --AM
         default: out_d = 0;
       endcase        
       `onwrite(out_r, out_a)
@@ -100,7 +89,6 @@ public void service() {
     end
   end
 
-endmodule
 
 
 

diff --git a/src/edu/berkeley/fleet/slipway/Slipway.java b/src/edu/berkeley/fleet/slipway/Slipway.java
index b694add..ee47652 100644 (file)
--- a/src/edu/berkeley/fleet/slipway/Slipway.java
+++ b/src/edu/berkeley/fleet/slipway/Slipway.java
@@ -318,7 +318,8 @@ public class Slipway extends Interpreter {
             FileOutputStream out = new FileOutputStream(outf);
             PrintWriter pw = new PrintWriter(out);
 
-            if (filename.equals("alu2")) {
+            boolean auto = filename.equals("alu2") || filename.equals("alu1") || filename.equals("lut3");
+            if (auto) {
                 pw.println("`include \"macros.v\"");
                 pw.println();
                 pw.println("module " + filename + "( clk");
@@ -338,9 +339,43 @@ public class Slipway extends Interpreter {
                     pw.println();
                 }
                 pw.println("        );");
+                pw.println();
+                pw.println("    input clk;");
+                for(ShipDescription.BenkoBox bb : sd.benkoBoxes) {
+                    if (bb.ports.length > 1) throw new RuntimeException("gah");
+                    String bb_name = bb.ports[0];
+                    pw.print("        ");
+                    if (bb.inbox) {
+                        pw.println("`input(" +
+                                   bb_name+"_r,  "+
+                                   bb_name+"_a,  "+
+                                   bb_name+"_a_, "+
+                                   "[(`DATAWIDTH-1):0],"+
+                                   bb_name+"_d)"
+                                   );
+                    } else {
+                        pw.println("`output(" +
+                                   bb_name+"_r,  "+
+                                   bb_name+"_r_, "+
+                                   bb_name+"_a,  "+
+                                   "[(`DATAWIDTH-1):0],"+
+                                   bb_name+"_d_)"
+                                   );
+                        pw.println("`defreg(" +
+                                   bb_name+"_d_,  "+
+                                   "[(`DATAWIDTH-1):0],"+
+                                   bb_name+"_d)"
+                                   );
+                    }
+                    pw.println();
+                }
             }
 
             pw.println(sd.sections.get("fpga"));
+
+            if (auto)
+                pw.println("endmodule");
+
             pw.flush();
             pw.close();
         } catch (Exception e) { throw new RuntimeException(e); }

diff --git a/src/edu/berkeley/fleet/slipway/root.v b/src/edu/berkeley/fleet/slipway/root.v
index f3d9d11..caa3041 100644 (file)
--- a/src/edu/berkeley/fleet/slipway/root.v
+++ b/src/edu/berkeley/fleet/slipway/root.v
@@ -5,7 +5,7 @@ module root(clk, in_r,   in_a_, in_d,
 
   input        clk;
 
-  `input(in_r,   in_a, in_a_,  [7:0], in_d)
+  `input(in_r,   in_a, in_a_,    [7:0], in_d)
   `output(out_r, out_r_, out_a,  [7:0], out_d_)
 
   `defreg(horn_in_r_, [0:0],          horn_in_r)