--- /dev/null
+ship: Video
+
+== Ports ===========================================================
+data in: inX
+data in: inY
+data in: inData
+
+percolate up: dvi_d0 1
+percolate up: dvi_d1 1
+percolate up: dvi_d2 1
+percolate up: dvi_d3 1
+percolate up: dvi_d4 1
+percolate up: dvi_d5 1
+percolate up: dvi_d6 1
+percolate up: dvi_d7 1
+percolate up: dvi_d8 1
+percolate up: dvi_d9 1
+percolate up: dvi_d10 1
+percolate up: dvi_d11 1
+
+percolate up: dvi_h 1
+percolate up: dvi_v 1
+percolate up: dvi_xclk_n 1
+percolate up: dvi_xclk_p 1
+percolate up: dvi_de 1
+percolate up: dvi_reset_b 1
+percolate down: dvi_gpio1 1
+
+percolate up: dvi_iic_scl 1
+percolate inout: dvi_iic_sda 1
+
+percolate up: gpio_led_c 1
+percolate up: gpio_led_e 1
+percolate up: gpio_led_n 1
+percolate up: gpio_led_s 1
+percolate up: gpio_led_w 1
+percolate up: gpio_led_0 1
+percolate up: gpio_led_1 1
+percolate up: gpio_led_2 1
+percolate up: gpio_led_3 1
+percolate up: gpio_led_4 1
+percolate up: gpio_led_5 1
+percolate up: gpio_led_6 1
+percolate up: gpio_led_7 1
+
+== TeX ==============================================================
+
+== Fleeterpreter ====================================================
+
+ public void service() { }
+
+== FleetSim ==============================================================
+
+== FPGA ==============================================================
+
+ assign dvi_de = 1;
+ assign dvi_reset_b = 1;
+
+ assign dvi_d0 = 1;
+ assign dvi_d1 = 0;
+ assign dvi_d2 = 1;
+ assign dvi_d3 = 0;
+ assign dvi_d4 = 1;
+ assign dvi_d5 = 0;
+ assign dvi_d6 = 1;
+ assign dvi_d7 = 0;
+ assign dvi_d8 = 1;
+ assign dvi_d9 = 0;
+ assign dvi_d10 = 1;
+ assign dvi_d11 = 0;
+
+ assign gpio_led_n = 1;
+ assign gpio_led_s = 0;
+
+ assign gpio_led_0 = dvi_gpio1;
+ assign gpio_led_1 = 0;
+ assign gpio_led_2 = 1;
+ assign gpio_led_3 = 0;
+ assign gpio_led_4 = 1;
+ assign gpio_led_5 = 0;
+ assign gpio_led_6 = 1;
+ assign gpio_led_7 = 0;
+
+ wire dvi_xclk_p_unbuffered;
+ wire dvi_xclk_n_unbuffered;
+ wire dvi_xclk_fb;
+ BUFG GBUF_FOR_DVI_CLOCK_N (.I(dvi_xclk_n_unbuffered), .O(dvi_xclk_n));
+ BUFG GBUF_FOR_DVI_CLOCK_P (.I(dvi_xclk_p_unbuffered), .O(dvi_xclk_p));
+ DCM // 25Mhz VGA clock
+ #(
+ .CLKFX_MULTIPLY(4),
+ .CLKFX_DIVIDE(16),
+ .CLKIN_PERIOD("20 ns")
+ ) vgadcm (
+ .CLKIN (clk),
+ .CLKFB (dvi_xclk_fb),
+ .CLKFX (dvi_xclk_p_unbuffered),
+ .CLKFX180 (dvi_xclk_n_unbuffered),
+ .CLK0 (dvi_xclk_fb)
+ );
+
+ wire [31:0] vga_pixel_addr_;
+ wire vga_pixel_r;
+ wire vga_pixel_a_;
+ reg vga_pixel_a;
+ assign vga_pixel_a_ = vga_pixel_a;
+ wire [18:0] inAddr;
+
+ reg we;
+ wire [2:0] mem_out;
+ wire [31:0] vga_pixel_data;
+ assign vga_pixel_data = {
+ 8'b0,
+ mem_out[2], 7'b0,
+ mem_out[1], 7'b0,
+ mem_out[0], 7'b0
+ };
+
+ assign inAddr = inX_d + (inY_d * 640);
+
+ vram vram(clk, !rst, we, inAddr[18:0], vga_pixel_addr_[20:2], inData_d, , mem_out);
+
+ wb_vga wb_vga(
+ .wb_clk_i(clk),
+ .wb_rst_i(rst),
+
+ .fbwb_adr_o(vga_pixel_addr_),
+ .fbwb_stb_o(vga_pixel_r),
+ .fbwb_ack_i(vga_pixel_a_),
+ .fbwb_dat_i(vga_pixel_data),
+
+ /* VGA signals */
+ .vga_clk(dvi_xclk),
+ .vga_psave(vga_psave),
+ .vga_hsync(dvi_h),
+ .vga_vsync(dvi_v),
+ .vga_sync(vga_sync),
+ .vga_blank(vga_blank),
+ .vga_r(vga_r),
+ .vga_g(vga_g),
+ .vga_b(vga_b)
+ // .vga_clkout(vga_clkout)
+ );
+
+ always @(posedge clk) begin
+
+ if (rst) begin
+ `reset
+ end else begin
+ `cleanup
+ vga_pixel_a <= vga_pixel_r;
+
+ if (`inX_full && `inY_full && `inData_full) begin
+ we <= 1;
+ `drain_inX
+ `drain_inY
+ `drain_inData
+ end else begin
+ we <= 0;
+ end
+
+ end
+ end
+
+== Constants ========================================================
+
+== Test ==============================================================
+#skip
+
+#ship debug : Debug
+
+== Contributors =========================================================
+Adam Megacz <megacz@cs.berkeley.edu>