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update registersM
authorAdam Megacz <adam.megacz@sun.com>
Mon, 13 Apr 2009 23:16:11 +0000 (23:16 +0000)
committerAdam Megacz <adam.megacz@sun.com>
Mon, 13 Apr 2009 23:16:11 +0000 (23:16 +0000)
electric/registersM.jelib patch | blob | history

diff --git a/electric/registersM.jelib b/electric/registersM.jelib
index 8539e85..fa2249e 100755 (executable)
--- a/electric/registersM.jelib
+++ b/electric/registersM.jelib
@@ -6247,7 +6247,7 @@ EainB[1:14,TT]|ps[1:15]|D5G2;|pin@3||I
 X
 
 # Cell newPathReg;1{lay}
-CnewPathReg;1{lay}||cmos90|1233578276999|1239323507907|I|ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_bit()I10|DRC_last_good_drc_date()G1239323608616
+CnewPathReg;1{lay}||cmos90|1233578276999|1239468188590||ATTR_NCC(D5G3;NTY70;)S["exportsConnectedByParent vdd /vdd_[0-9]+/"]|DRC_last_good_drc_area_date()G1239468138671
 Iaddr2in60Cx7;2{lay}|addr2in6@0||936|0|||D5G4;
 Iaddr2in60Cx7;2{lay}|addr2in6@1||-792|0|X||D5G4;
 Ngeneric:Facet-Center|art@0||0|0||||AV
@@ -6306,10 +6306,13 @@ NX-Metal-3-Metal-4-Con|contact@82||-1194|11.6||||
 NX-Metal-1-Metal-2-Con|contact@83||74.5|-10||||
 NX-Metal-2-Metal-3-Con|contact@84||-41|-10||||
 NX-Metal-3-Metal-4-Con|contact@85||-41|11.6||||
+NX-Metal-1-Metal-2-Con|contact@86||265|-16||||
+NX-Metal-1-Metal-2-Con|contact@87||280|-22||||
 IdriversJ:driveConnecter2;1{lay}|driveCon@1||158|-39.8|XY||D5G4;
 IdriversJ:driveConnecter2;1{lay}|driveCon@2||-5|-47.6|Y||D5G4;
 Igates1inM:inv10D;1{lay}|inv10D@0||101|0|XY||D5G4;
 Igates1inM:inv10D;1{lay}|inv10D@1||84|0|||D5G4;
+Igates1inM:inv10D;1{lay}|inv10D@2||274|0|||D5G4;
 Igates1inM:inv30;1{lay}|inv30@0||-1|0|X||D5G4;
 IlatchesK:latch2in60Cm2dn;2{lay}|latch2in@0||360|0|Y||D5G4;
 IdriversJ:latchAndDriver30;1{lay}|latchAnd@0||140|0|||D5G4;
@@ -6327,12 +6330,13 @@ NMetal-1-Pin|pin@27||74.5|-25||||
 NMetal-1-Pin|pin@28||74.5|-9||||
 NMetal-2-Pin|pin@30||182|22||||
 NMetal-2-Pin|pin@31||182|28||||
+NMetal-1-Pin|pin@34||265|-25||||
 IfanPinsM:m3address15;1{lay}|pins15m3@1||6|60|||D5G4;
 IfanPinsM:pinsIn07m4;1{lay}|pinsIn07@8||-288|0|||D5G4;
 IfanPinsM:pinsIn07m4;1{lay}|pinsIn07@9||288|-72|||D5G4;
 IfanPinsM:pins07m3ar144;1{lay}|pinsIn07@10||-762|-24|||D5G4;
 IfanPinsM:pins07m3ar144;1{lay}|pinsIn07@11||918|-30.5|X||D5G4;
-IwiresL:select132;1{lay}|select13@0||228|0|||D5G4;
+IwiresL:select100;1{lay}|select10@0||218|0|||D5G4;
 IwiresL:select144;1{lay}|select14@0||-208|0|||D5G4;
 IwiresL:select144;1{lay}|select14@1||-85|0|||D5G4;
 IwiresL:wellContacts13;1{lay}|wellCont@0||69|0|||D5G4;
@@ -6445,9 +6449,6 @@ Ametal-1|net@277|||S0|pin@11||17|-25|inv30@0|inA|6|-25
 Ametal-1|net@279|||S1800|inv30@0|inB|6|25|pin@13||31.5|25
 Ametal-1|net@280|||S2700|pin@13||31.5|25|nand3in6@0|out_1|31.5|38.5
 Ametal-1|net@281|||S2700|pin@9||17|-38.5|pin@11||17|-25
-Ametal-2|net@282||6.2|S1800|latchAnd@0|vdd_2|170.5|50|latch2in@0|vdd|288|50
-Ametal-2|net@283||6.2|S0|latch2in@0|gnd|288|0|latchAnd@0|gnd_1|170.5|0
-Ametal-2|net@284||6.2|S0|latch2in@0|vdd_2|288|-50|latchAnd@0|vdd_3|170.5|-50
 Ametal-2|net@285||6.2|S0|inv30@0|vdd_2|-17.5|50|addr2in6@1|vdd|-288|50
 Ametal-2|net@286||6.2|S1800|addr2in6@1|gnd|-288|0|inv30@0|gnd_1|-17.5|0
 Ametal-2|net@287||6.2|S1800|addr2in6@1|vdd_2|-288|-50|inv30@0|vdd_3|-17.5|-50
@@ -6462,7 +6463,6 @@ Ametal-2|net@302|||S0|inv10D@0|vdd_1|109.5|50|latchAnd@0|vdd|109.5|50
 Ametal-2|net@303|||S0|inv10D@0|vdd|109.5|-50|latchAnd@0|vdd_1|109.5|-50
 Ametal-1|net@305|||S2700|latchAnd@0|inA|135.5|25|contact@80||135.5|28
 Ametal-1|net@307|||S2700|inv10D@0|in|101|25|contact@81||101|28
-Ametal-2|net@312|||S900|pin@18||322.5|-16|pin@5||322.5|-22
 Ametal-4|net@313|||S0|contact@17||-1050|11.6|contact@82||-1194|11.6
 Ametal-4|net@316|||S1800|contact@17||-1050|11.6|pinsIn07@8|in[6]|-288|11.6
 Ametal-2|net@319|||S1800|addr2in6@1|inA[6]|-1027.5|-22|addr2in6@1|inA[5]|-883.5|-22
@@ -6489,6 +6489,17 @@ Ametal-2|net@357||1.2|S1800|addr2in6@1|fire[A]|-288|-75.9|driveCon@2|take|-5|-75
 Ametal-2|net@358||1.2|S1800|driveCon@2|take|-5|-75.9|contact@2||305.5|-75.9
 Ametal-2|net@359||1.2|S0|contact@1||314.5|-68.1|driveCon@1|take|158|-68.1
 Ametal-2|net@360||1.2|S0|driveCon@1|take|158|-68.1|addr2in6@1|fire[B]|-288|-68.1
+Ametal-2|net@361|||S0|pin@18||322.5|-16|contact@86||265|-16
+Ametal-1|net@364|||S1800|pin@34||265|-25|inv10D@2|in|274|-25
+Ametal-1|net@365|||S900|contact@86||265|-16|pin@34||265|-25
+Ametal-2|net@366||6.2|S0|latch2in@0|gnd|288|0|inv10D@2|gnd_1|282.5|0
+Ametal-2|net@367||6.2|S1800|inv10D@2|vdd_2|282.5|50|latch2in@0|vdd|288|50
+Ametal-2|net@368||6.2|S1800|inv10D@2|vdd_3|282.5|-50|latch2in@0|vdd_2|288|-50
+Ametal-2|net@369|||S0|latch2in@0|inA[1]|307.5|-22|contact@87||280|-22
+Ametal-1|net@370|||S900|inv10D@2|out|280|7|contact@87||280|-22
+Ametal-2|net@371||6.2|S1800|latchAnd@0|gnd_1|170.5|0|inv10D@2|gnd|265.5|0
+Ametal-2|net@372||6.2|S0|inv10D@2|vdd|265.5|50|latchAnd@0|vdd_2|170.5|50
+Ametal-2|net@373||6.2|S0|inv10D@2|vdd_1|265.5|-50|latchAnd@0|vdd_3|170.5|-50
 Ex[1]|aout[1]|D5G2;|pins15m3@1|x[1]|I
 Ex[2]|aout[2]|D5G2;|pins15m3@1|x[2]|I
 Ex[3]|aout[3]|D5G2;|pins15m3@1|x[3]|I
@@ -6541,21 +6552,22 @@ Evdd_5||D5G2;|addr2in6@1|vdd_3|P
 X
 
 # Cell newPathReg;1{sch}
-CnewPathReg;1{sch}||schematic|1233579614045|1238334870912|I
+CnewPathReg;1{sch}||schematic|1233579614045|1239468451476|
 Iaddr2in60Cx15;1{ic}|addr2in6@0||0|0|||D5G4;
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||12|0||||
 NOff-Page|conn@1||-28|-7||||
-NOff-Page|conn@3||-21|4|||XRR|
+NOff-Page|conn@3||-31|3|||XRR|
 NOff-Page|conn@4||-27|-17|||XRR|
 IredFive:inv;1{ic}|inv@1||-32|-24|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFive:inv;1{ic}|inv@2||-32|-31|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
+IredFive:inv;1{ic}|inv@3||-23|8|||D0G4;|ATTR_Delay(D5G1;NPX1;Y-3;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFive:invI;2{ic}|invI@0||-4.5|-26|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S30|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IdriversJ:latchAndDriver30;1{ic}|latchAnd@0||-10|-16|Y||D5G4;
 Igates3inM:nand3in6.6;2{ic}|nand3in6@1||-11.5|-26|Y||D5G4;
 InewPathReg;1{ic}|newPathR@0||22|10|||D5G4;
 Ngeneric:Invisible-Pin|pin@0||0.5|25.5|||||ART_message(D5G6;)SnewPathRegister
-Ngeneric:Invisible-Pin|pin@1||-0.5|14.5|||||ART_message(D5G3;)S[ies 2 February 2009,revised 24 March 2009]
+Ngeneric:Invisible-Pin|pin@1||-0.5|14.5|||||ART_message(D5G3;)S[ies 2 February 2009,revised 11 April 2009]
 Ngeneric:Invisible-Pin|pin@2||-1.5|20.5|||||ART_message(D5G4;)SThis is the path register
 NBus_Pin|pin@4||-15|-5|-1|-1||
 NBus_Pin|pin@5||-15|-1|-1|-1||
@@ -6579,6 +6591,11 @@ NWire_Pin|pin@28||-39.5|-31||||
 NWire_Pin|pin@29||-18|-15||||
 NWire_Pin|pin@30||-18|-12.5||||
 Ngeneric:Invisible-Pin|pin@31||13.5|-13.5|||||ART_message(D3G2;)S[March 24 fix:,"take[ps] acts if ps[14] is one,","take[dp] acts if ps[13,14] both zero",register wiring is OK.]
+NWire_Pin|pin@32||-28|8||||
+NWire_Pin|pin@33||-28|5||||
+NWire_Pin|pin@34||-18|8||||
+NWire_Pin|pin@35||-18|5||||
+Ngeneric:Invisible-Pin|pin@36||-43.5|19.5|||||ART_message(D3G2;)S[April 11 fix:,"ps[15] needs inversion",before entering the path,register.]
 IorangeTSMC090nm:wire90;1{ic}|wire90@0||0|-16|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D3616.3000000000015|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@1||4|-26|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D3495.7000000000016|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@3||-24.5|-24|||D0G4;|ATTR_L(D5FLeave alone;G1;PUD)D270.0|ATTR_LEWIRE(P)I1|ATTR_layer(D5FLeave alone;G1;NPY-1;)I1|ATTR_width(D5FLeave alone;G1;NPY-2;)I3
@@ -6606,11 +6623,15 @@ Awire|net@44|||1800|wire90@4|b|-22|-31|pin@19||-20|-31
 Awire|net@45|||0|pin@21||-20|-24|wire90@3|b|-22|-24
 Awire|net@46|||0|wire90@3|a|-27|-24|inv@1|out|-29.5|-24
 Awire|net@47|||1800|inv@2|out|-29.5|-31|wire90@4|a|-27|-31
+Awire|net@48|||0|inv@3|in|-25.5|8|pin@32||-28|8
+Awire|net@50|||1800|inv@3|out|-20.5|8|pin@34||-18|8
 Awire|ps[13]|D5G2;||2700|pin@25||-39.5|-24|pin@16||-39.5|-20.5
 Awire|ps[14]|D5G2;||2700|pin@28||-39.5|-31|pin@26||-39.5|-27.5
 Awire|ps[14]|D5G2;||2700|pin@29||-18|-15|pin@30||-18|-12.5
-Abus|ps[15,1:13,13]|D5G2;|-0.5|IJ900|pin@6||-6|6|pin@7||-6|1
-Abus|ps[15],dp[1:12,12,12]|D5G2;|-0.5|IJ2700|pin@4||-15|-5|pin@5||-15|-1
+Awire|ps[15]|D5G2;||900|pin@32||-28|8|pin@33||-28|5
+Abus|ps[15not,1:13,13]|D5G2;|-0.5|IJ900|pin@6||-6|6|pin@7||-6|1
+Awire|ps[15not]|D5G2;||900|pin@34||-18|8|pin@35||-18|5
+Abus|ps[15not],dp[1:12,12,12]|D5G2;|-0.5|IJ2700|pin@4||-15|-5|pin@5||-15|-1
 Abus|take[dp,ps]|D5G2;|-0.5|IJ900|addr2in6@0|take[A,B]|-2|-3|pin@8||-2|-6.5
 Awire|take[dp]|D5G2;||2700|pin@11||11.5|-26|pin@12||11.5|-22.5
 Awire|take[ps]|D5G2;||2700|pin@9||6.5|-16|pin@10||6.5|-12.5
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