From: Simon Marlow Date: Fri, 7 Jan 2011 09:42:36 +0000 (+0000) Subject: comment updates X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;ds=inline;h=62db6241c578f2b02e266b4dd0b535e0f59950bf;p=ghc-hetmet.git comment updates --- diff --git a/compiler/nativeGen/X86/Instr.hs b/compiler/nativeGen/X86/Instr.hs index 00ce130..b9cdf7f 100644 --- a/compiler/nativeGen/X86/Instr.hs +++ b/compiler/nativeGen/X86/Instr.hs @@ -102,7 +102,7 @@ Hence GLDZ and GLD1. Bwahahahahahahaha! -} {- -MORE FLOATING POINT MUSINGS... +Note [x86 Floating point precision] Intel's internal floating point registers are by default 80 bit extended precision. This means that all operations done on values in @@ -141,11 +141,12 @@ This is what gcc does. Spilling at 80 bits requires taking up a full 128 bit slot (so we get alignment). We spill at 80-bits and ignore the alignment problems. -In the future, we'll use the SSE registers for floating point. This -requires a CPU that supports SSE2 (ordinary SSE only supports 32 bit -precision float ops), which means P4 or Xeon and above. Using SSE -will solve all these problems, because the SSE registers use fixed 32 -bit or 64 bit precision. +In the future [edit: now available in GHC 7.0.1, with the -msse2 +flag], we'll use the SSE registers for floating point. This requires +a CPU that supports SSE2 (ordinary SSE only supports 32 bit precision +float ops), which means P4 or Xeon and above. Using SSE will solve +all these problems, because the SSE registers use fixed 32 bit or 64 +bit precision. --SDM 1/2003 -} diff --git a/rts/RtsStartup.c b/rts/RtsStartup.c index 6ed837a..bc169ff 100644 --- a/rts/RtsStartup.c +++ b/rts/RtsStartup.c @@ -69,8 +69,8 @@ void exitLinker( void ); // there is no Linker.h file to include static int hs_init_count = 0; /* ----------------------------------------------------------------------------- - Initialise floating point unit on x86 (currently disabled. why?) - (see comment in ghc/compiler/nativeGen/MachInstrs.lhs). + Initialise floating point unit on x86 (currently disabled; See Note + [x86 Floating point precision] in compiler/nativeGen/X86/Instr.hs) -------------------------------------------------------------------------- */ #define X86_INIT_FPU 0