From: adam <adam@megacz.com>
Date: Tue, 7 Aug 2007 14:40:42 +0000 (+0100)
Subject: remove old Alu3
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=01df6c2ebc7f4dd0624bc8c10083df7d41f86926;p=fleet.git

remove old Alu3
---

diff --git a/ships/Alu3.ship b/ships/Alu3.ship
deleted file mode 100644
index 40ed9cc..0000000
--- a/ships/Alu3.ship
+++ /dev/null
@@ -1,88 +0,0 @@
-ship: Alu3
-
-== Ports ===========================================================
-data  in:   in1
-data  in:   in2
-data  in:   in3
-
-data  out:  out1
-  shortcut to: in1
-data  out:  out2
-  shortcut to: in2
-data  out:  out3
-  shortcut to: in3
-
-== Constants ========================================================
-== TeX ==============================================================
-
-This ship performs addition of three inputs, producing two output
-values in carry-save form.  To complete the addition, send the two
-output values to an Alu2 with opcode ADD.  For summing a set of four
-or more numbers, Alu3 followed by Alu2 is often faster than repeated
-use of Alu2.
-
-== Fleeterpreter ====================================================
-public void service() {
-  if (box_in1.dataReadyForShip() &&
-      box_in2.dataReadyForShip() &&
-      box_in3.dataReadyForShip() &&
-      box_out1.readyForDataFromShip() &&
-      box_out2.readyForDataFromShip()) {
-      long v1     = box_in1.removeDataForShip();
-      long v2     = box_in2.removeDataForShip();
-      long v3     = box_in3.removeDataForShip();
-      long o1     = ((v1 & v2) | (v2 & v3) | (v1 & v3)) << 1;
-      long o2     = v1 ^ v2 ^ v3;
-      box_out1.addDataFromShip(o1);
-      box_out2.addDataFromShip(o2);
-  }
-}
-
-== FleetSim ==============================================================
-
-== FPGA ==============================================================
-
-  reg                    have_a;
-  reg [(`DATAWIDTH-1):0] a;
-  reg                    have_b;
-  reg [(`DATAWIDTH-1):0] b;
-  reg                    have_c;
-  reg [(`DATAWIDTH-1):0] c;
-  reg                    have_out1;
-  reg                    have_out2;
-
-  always @(posedge clk) begin
-    if (have_out1) begin
-      `onwrite(out1_r, out1_a) have_out1 <= 0; end
-
-    end else if (have_out2) begin
-      `onwrite(out2_r, out2_a) have_out2 <= 0; end
-
-    end else if (!have_out1 && !have_out2) begin
-      if (!have_a) begin
-        `onread(in1_r, in1_a) have_a <= 1; a <= in1_d; end
-        end
-      if (!have_b) begin
-        `onread(in2_r, in2_a) have_b <= 1; b <= in2_d; end
-        end
-      if (!have_c) begin
-        `onread(in3_r, in3_a) have_c <= 1; c <= in3_d; end
-        end
-  
-      if (have_a && have_b && have_c) begin
-        out1_d    <= { { ((a & b) | (b & c) | (a & c)) } , 1'b0 };
-        out2_d    <= a ^ b ^ c;
-        have_a    <= 0;
-        have_b    <= 0;
-        have_c    <= 0;
-        have_out1 <= 1;
-        have_out2 <= 1;
-      end
-    end
-  end
-
-
-
-
-== Contributors =========================================================
-Adam Megacz <megacz@cs.berkeley.edu>