From: adam <adam@megacz.com>
Date: Tue, 12 Feb 2008 09:12:39 +0000 (+0100)
Subject: update fpga to reset counters on kill/massacre
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=023d86c1e93c46dc31153f9e320da86eba14511c;p=fleet.git

update fpga to reset counters on kill/massacre
---

diff --git a/src/edu/berkeley/fleet/fpga/Generator.java b/src/edu/berkeley/fleet/fpga/Generator.java
index c5881ec..f1fe853 100644
--- a/src/edu/berkeley/fleet/fpga/Generator.java
+++ b/src/edu/berkeley/fleet/fpga/Generator.java
@@ -613,7 +613,16 @@ public class Generator {
                       );
         box.new Event(
                       new Object[] { instr, ififo_in, "`instruction_is_massacre(instr)", isMassacreing.isEmpty() },
-                      new Action[] { instr, ififo_in, new AssignAction(ififo_in, instr), isMassacreing.doFill(), ondeckFull.doDrain(), newMayProceed.doDrain() }
+                      new Action[] { instr, ififo_in,
+                                     new AssignAction(ififo_in, instr),
+                                     isMassacreing.doFill(),
+                                     ondeckFull.doDrain(),
+                                     newMayProceed.doDrain(),
+                                     new AssignAction(repeat_counter, "0"),
+                                     new AssignAction(repcount2, "0"),
+                                     new AssignAction(repcount, "0"),
+                                     new AssignAction(loop_counter, "0"),
+                      }
                       );
 
         // Clog (must be first)
@@ -873,7 +882,7 @@ public class Generator {
         pw.println("`define instruction_bit_latch(i)        (`instruction_is_normal(i) && "+DC.verilog("i")+")");
         pw.println("`define instruction_bit_datain(i)       (`instruction_is_normal(i) && "+DI.verilog("i")+")");
         pw.println("`define instruction_bit_tokenin(i)      (`instruction_is_normal(i) && "+TI.verilog("i")+")");
-        pw.println("`define is_standing(i)                  (`instruction_is_normal(i) && "+STAND.verilog("i")+")");
+        //pw.println("`define is_standing(i)                  (`instruction_is_normal(i) && "+STAND.verilog("i")+")");
         pw.println("`define should_requeue(i)               (loop_counter > 0)");
         pw.println("`define done_executing(i)               (!`is_standing(i) && (repcount2==0 || repcount2==1))");