From: adam <adam@megacz.com>
Date: Thu, 21 Aug 2008 10:33:02 +0000 (+0100)
Subject: add DRAM ship
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=0c78ec124d5119821397fb53d205f52121ded839;hp=965ad38d7bbcdea879f4ea82cb89b88785331714;p=fleet.git

add DRAM ship
---

diff --git a/ships/DRAM.ship b/ships/DRAM.ship
new file mode 100644
index 0000000..ed31ee1
--- /dev/null
+++ b/ships/DRAM.ship
@@ -0,0 +1,74 @@
+ship: DRAM
+
+== Ports ===========================================================
+data  in:    inAddrRead
+data  in:    inAddrWrite
+data  in:    inDataWrite
+
+data  out:   out
+
+== TeX ==============================================================
+
+== Fleeterpreter ====================================================
+    public void service() { }
+== FleetSim ==============================================================
+
+== FPGA ==============================================================
+
+  // FIXME: use the other chip (64-bit data bus)
+
+  reg         dram_addr_r;
+  reg         dram_isread;
+  reg         dram_write_data_push;
+  reg         dram_read_data_pop;
+  reg  [`DATAWIDTH-1:0]  out_d;
+
+  assign dram_addr_r_ = dram_addr_r;
+  assign dram_isread_ = dram_isread;
+  assign dram_addr_ = !dram_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
+  assign dram_write_data_push_ = dram_write_data_push;
+  assign dram_read_data_pop_ = dram_read_data_pop;
+  assign dram_write_data_ = inDataWrite_d[31:0];
+  assign out_d_ = out_d;
+
+  always @(posedge clk) begin
+
+    if (!rst) begin
+      `reset
+      dram_isread <= 0;
+      dram_addr_r <= 0;
+      dram_read_data_pop <= 0;
+
+    end else begin
+
+      if (!inAddrRead_r  && inAddrRead_a)  inAddrRead_a  <= 0;
+      if (!inDataWrite_r && inDataWrite_a) inDataWrite_a <= 0;
+      if (!inAddrWrite_r && inAddrWrite_a) inAddrWrite_a <= 0;
+      if ( out_r         && out_a)         out_r <= 0;
+
+      if (dram_addr_r && !dram_addr_a) begin
+         // busy
+      end else if (dram_addr_r &&  dram_addr_a && !dram_isread) begin
+          dram_addr_r <= 0;
+          inAddrWrite_a <= 1;
+          inDataWrite_a <= 1;
+      end else if (dram_addr_r &&  dram_addr_a && dram_isread) begin
+          dram_addr_r <= 0;
+          inAddrRead_a <= 1;
+          out_d <= dram_read_data;
+          out_r <= 1;
+      end else if (inAddrWrite_r && !inAddrWrite_a && inDataWrite_r && !inDataWrite_a && !dram_addr_r && !dram_addr_a) begin
+          dram_addr_r <= 1;
+          dram_isread <= 0;
+      end else if (inAddrRead_r && !inAddrRead_a && !out_r && !out_a && !dram_addr_r && !dram_addr_a) begin
+          dram_addr_r <= 1;
+          dram_isread <= 1;
+      end
+    end
+  end
+
+
+== Constants ========================================================
+
+== Contributors =========================================================
+Adam Megacz <megacz@cs.berkeley.edu>