From: adam Date: Mon, 10 Nov 2008 12:46:56 +0000 (+0100) Subject: replace DATAWIDTH with WORDWIDTH X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=11df380a69fbab49049ac267c9099a01d3370e4a;p=fleet.git replace DATAWIDTH with WORDWIDTH --- diff --git a/ships/Alu.ship b/ships/Alu.ship index 6157fc1..50fcfee 100644 --- a/ships/Alu.ship +++ b/ships/Alu.ship @@ -121,11 +121,11 @@ public void service() { == FPGA ============================================================== - wire [`DATAWIDTH:0] sum; + wire [`WORDWIDTH:0] sum; wire cin; - wire [(`DATAWIDTH-1):0] in2_inverted; + wire [(`WORDWIDTH-1):0] in2_inverted; - wire [(`DATAWIDTH-1):0] res; + wire [(`WORDWIDTH-1):0] res; wire isplus; wire eq; wire cout; @@ -134,13 +134,13 @@ public void service() { assign cin = isplus ? 0 : 1; assign in2_inverted = isplus ? in2_d : ~in2_d; assign sum = {in1_d,cin} + {in2_inverted,cin}; - assign res = sum[`DATAWIDTH:1]; - assign greater = !res[`DATAWIDTH-1]; - assign both_negative = in1_d[`DATAWIDTH-1] && in2_d[`DATAWIDTH-1]; + assign res = sum[`WORDWIDTH:1]; + assign greater = !res[`WORDWIDTH-1]; + assign both_negative = in1_d[`WORDWIDTH-1] && in2_d[`WORDWIDTH-1]; assign eq = in1_d == in2_d; - assign cout = sum[`DATAWIDTH]; + assign cout = sum[`WORDWIDTH]; - assign out_d_[`DATAWIDTH] = + assign out_d_[`WORDWIDTH] = (inOp_d==0) ? 1'b0 : (inOp_d==1) ? 1'b0 : (inOp_d==2) ? cout : @@ -151,14 +151,14 @@ public void service() { (inOp_d==9) ? ~greater : 0; - assign out_d_[(`DATAWIDTH-1):0] = + assign out_d_[(`WORDWIDTH-1):0] = (inOp_d==0) ? (in1_d) : (inOp_d==1) ? (in2_d) : (inOp_d==2) ? (res) : (inOp_d==3) ? (res) : (inOp_d==4) ? (greater ? in1_d : in2_d) : (inOp_d==5) ? (greater ? in2_d : in1_d) : - (inOp_d==6) ? {{ (`DATAWIDTH-1) {1'b0 }}, eq } : + (inOp_d==6) ? {{ (`WORDWIDTH-1) {1'b0 }}, eq } : (inOp_d==9) ? (both_negative ? in1_d : (greater ? in1_d : in2_d)) : 0; diff --git a/ships/CarrySaveAdder.ship b/ships/CarrySaveAdder.ship index dc67fab..edef42d 100644 --- a/ships/CarrySaveAdder.ship +++ b/ships/CarrySaveAdder.ship @@ -22,17 +22,17 @@ public void service() { == FPGA ============================================================== - reg [(`DATAWIDTH-1):0] temp; - reg [(`DATAWIDTH):0] out_d; + reg [(`WORDWIDTH-1):0] temp; + reg [(`WORDWIDTH):0] out_d; reg [1:0] state; initial state = 0; assign out_d_ = out_d; - wire [(`DATAWIDTH-1):0] majority; - wire [(`DATAWIDTH-1):0] xors; + wire [(`WORDWIDTH-1):0] majority; + wire [(`WORDWIDTH-1):0] xors; genvar i; generate - for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT + for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT assign majority[i] = (temp[i] & out_d[i]) | (in_d[i] & out_d[i]) | (temp[i] & in_d[i]); assign xors[i] = temp[i] ^ out_d[i] ^ in_d[i]; end @@ -55,7 +55,7 @@ public void service() { end else if (state == 1) begin temp <= in_d; end else if (state == 2) begin - out_d <= { majority[`DATAWIDTH-1:0], 1'b0 }; + out_d <= { majority[`WORDWIDTH-1:0], 1'b0 }; temp <= xors; `fill_out end diff --git a/ships/Counter.ship b/ships/Counter.ship index dbdb4a5..fa2ac8d 100644 --- a/ships/Counter.ship +++ b/ships/Counter.ship @@ -26,8 +26,8 @@ public void service() { } == FPGA ============================================================== - reg [`DATAWIDTH-1:0] temp; - initial temp = {`DATAWIDTH{1'b1}}; + reg [`WORDWIDTH-1:0] temp; + initial temp = {`WORDWIDTH{1'b1}}; reg full; initial full = 0; wire op_count; assign op_count = inOp_d==12; @@ -58,19 +58,19 @@ public void service() { } end else if (`inOp_full) begin if (!full) begin if (op_count && `in1_full && `in2_full) begin - temp <= in1_d[`DATAWIDTH-1:0] - in2_d[`DATAWIDTH-1:0]; + temp <= in1_d[`WORDWIDTH-1:0] - in2_d[`WORDWIDTH-1:0]; `drain_in1 full <= 1; end else if (op_c1 && `in1_full) begin - temp <= in1_d[`DATAWIDTH-1:0]-1; + temp <= in1_d[`WORDWIDTH-1:0]-1; `drain_in1 full <= 1; end else if (op_c2 && `in2_full) begin - temp <= in2_d[`DATAWIDTH-1:0]-1; + temp <= in2_d[`WORDWIDTH-1:0]-1; `drain_in2 full <= 1; end - end else if (temp[`DATAWIDTH-1]) begin + end else if (temp[`WORDWIDTH-1]) begin full <= 0; `drain_inOp if (op_count) begin diff --git a/ships/DRAM.ship b/ships/DRAM.ship index 21f572c..2607b28 100644 --- a/ships/DRAM.ship +++ b/ships/DRAM.ship @@ -19,7 +19,7 @@ data out: out reg dram_isread; reg dram_write_data_push; reg dram_read_data_pop; - reg [`DATAWIDTH:0] out_d; + reg [`WORDWIDTH:0] out_d; wire [31:0] dram_addr__; assign dram_addr_r_ = dram_addr_r; @@ -29,7 +29,7 @@ data out: out assign dram_write_data_push_ = dram_write_data_push; assign dram_read_data_pop_ = dram_read_data_pop; assign dram_write_data_ = inDataWrite_d; -// assign dram_write_data_ = inDataWrite_d[(`DATAWIDTH-1):0]; +// assign dram_write_data_ = inDataWrite_d[(`WORDWIDTH-1):0]; assign out_d_ = out_d; always @(posedge clk) begin diff --git a/ships/Debug.ship b/ships/Debug.ship index e33871f..77bc622 100644 --- a/ships/Debug.ship +++ b/ships/Debug.ship @@ -30,7 +30,7 @@ public void service() { == FPGA ============================================================== - reg [`DATAWIDTH-1:0] out_d; + reg [`WORDWIDTH-1:0] out_d; assign out_d_ = out_d; always @(posedge clk) begin diff --git a/ships/Lut3.ship b/ships/Lut3.ship index 7cfd876..e6bd469 100644 --- a/ships/Lut3.ship +++ b/ships/Lut3.ship @@ -66,7 +66,7 @@ is considered ``bit zero''). genvar i; generate - for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT + for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}]; end endgenerate diff --git a/ships/Memory.ship b/ships/Memory.ship index cb36dd0..7245737 100644 --- a/ships/Memory.ship +++ b/ships/Memory.ship @@ -161,8 +161,8 @@ sequence guarantee problem mentioned in the previous paragraph. == FPGA ============================================================== - wire [(`DATAWIDTH-1):0] out1; - wire [(`DATAWIDTH-1):0] out2; + wire [(`WORDWIDTH-1):0] out1; + wire [(`WORDWIDTH-1):0] out2; reg [(`CODEBAG_SIZE_BITS-1):0] counter; reg [(`BRAM_ADDR_WIDTH-1):0] cursor; @@ -176,7 +176,7 @@ sequence guarantee problem mentioned in the previous paragraph. initial dispatching_cbd = 0; wire [(`BRAM_ADDR_WIDTH-1):0] addr1; - assign addr1 = write_flag ? inAddrWrite_d[(`DATAWIDTH-1):0] : inAddrRead_d[(`DATAWIDTH-1):0]; + assign addr1 = write_flag ? inAddrWrite_d[(`WORDWIDTH-1):0] : inAddrRead_d[(`WORDWIDTH-1):0]; bram14 mybram(clk, rst, write_flag, addr1, cursor, inDataWrite_d, out1, out2); assign out_d_ = { out_w , (dispatching_cbd ? out2 : out1) }; @@ -199,7 +199,7 @@ sequence guarantee problem mentioned in the previous paragraph. // assumes we never want a zero-length codebag if (`inCBD_full && `out_empty) begin if (!dispatching_cbd) begin - cursor <= inCBD_d[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)]; + cursor <= inCBD_d[(`WORDWIDTH-1):(`CODEBAG_SIZE_BITS)]; counter <= 0; dispatching_cbd <= 1; end diff --git a/ships/Rotator.ship b/ships/Rotator.ship index e3d7208..5c8226a 100644 --- a/ships/Rotator.ship +++ b/ships/Rotator.ship @@ -33,7 +33,7 @@ public void service() { == FPGA ============================================================== - reg [(`DATAWIDTH):0] out_d; + reg [(`WORDWIDTH):0] out_d; assign out_d_ = out_d; reg full; @@ -58,7 +58,7 @@ public void service() { shamt <= 0; full <= 1; end else if (!shamt_eq) begin - out_d <= { out_d[0], out_d[0], out_d[`DATAWIDTH-1:1] }; + out_d <= { out_d[0], out_d[0], out_d[`WORDWIDTH-1:1] }; shamt <= shamt+1; end else begin `drain_in diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java index b2cfd92..eb33e10 100644 --- a/src/edu/berkeley/fleet/fpga/Fpga.java +++ b/src/edu/berkeley/fleet/fpga/Fpga.java @@ -20,8 +20,6 @@ import static edu.berkeley.fleet.fpga.verilog.Verilog.*; => clean up fabricelement methods => get rid of addcrap => automatic width-setting on ports -=> nuke DATAWIDTH? - => serdes and fastclock/slowclock? */ public class Fpga extends FleetTwoFleet { @@ -51,7 +49,7 @@ public class Fpga extends FleetTwoFleet { pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v"))); pw.println("`define BRAM_ADDR_WIDTH 14"); - pw.println("`define BRAM_DATA_WIDTH `DATAWIDTH"); + pw.println("`define BRAM_DATA_WIDTH `WORDWIDTH"); pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))"); pw.println("`define BRAM_NAME bram14"); pw.println("`include \"bram.inc\""); @@ -234,7 +232,7 @@ public class Fpga extends FleetTwoFleet { boolean debug = "debug".equals(filename); - pw.println("`define DATAWIDTH "+WIDTH_WORD); + pw.println("`define WORDWIDTH "+WIDTH_WORD); pw.println("`define CODEBAG_SIZE_BITS "+CBD_SIZE.valmaskwidth); pw.println();