From: Adam Megacz <adam.megacz@sun.com>
Date: Mon, 13 Apr 2009 23:15:18 +0000 (+0000)
Subject: add Ivans updated registersM.jelib and regenerate marina.spi
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=203ce7d33f17201f1132c89e9f00850233fe6fce;p=fleet.git

add Ivans updated registersM.jelib and regenerate marina.spi
---

diff --git a/testCode/marina.spi b/testCode/marina.spi
index 2be9f20..30f6508 100644
--- a/testCode/marina.spi
+++ b/testCode/marina.spi
@@ -1,7 +1,7 @@
 *** SPICE deck for cell marinaOut{sch} from library aMarinaM
 *** Created on Mon Nov 17, 2008 08:47:24
-*** Last revised on Sun Mar 22, 2009 16:27:39
-*** Written on Thu Mar 26, 2009 20:16:11 by Electric VLSI Design System, 
+*** Last revised on Mon Mar 30, 2009 06:59:15
+*** Written on Mon Apr 13, 2009 11:37:47 by Electric VLSI Design System, 
 *version 8.08k
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
@@ -932,6 +932,14 @@ Xwire90@0 net@67 net@51 wire90-627_9-layer_1-width_3
 Xwire90@1 net@72 net@71 wire90-124_7-layer_1-width_3
 .ENDS sucANDdri60
 
+*** CELL: wiresL:tranCap{sch}
+.SUBCKT tranCap
+MNMOSf@1 gnd vdd gnd gnd nch W='360*(1+ABN/sqrt(360*3))' L='3' 
++DELVTO='AVT0N/sqrt(360*3)'
+MPMOSf@2 vdd gnd vdd vdd pch W='720*(1+ABP/sqrt(720*3))' L='3'  
++DELVTO='AVT0P/sqrt(720*3)'
+.ENDS tranCap
+
 *** CELL: orangeTSMC090nm:wire{sch}
 .SUBCKT wire-C_0_011f-175-R_34_667m a b
 Ccap@0 gnd net@14 0.642f
@@ -1040,6 +1048,11 @@ XinvI@0 net@357 net@409 inv-X_10
 XinvI@1 net@475 s[1] inv-X_10
 XpredDri6@0 fire clear pred driversJ__predDri60wMC
 XsucANDdr@4 net@499 fire succ sucANDdri60
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
 Xwire90@1 net@374 net@241 wire90-175-layer_1-width_3
 Xwire90@7 net@375 net@360 wire90-516_9-layer_1-width_3
 Xwire90@10 net@357 net@353 wire90-160_4-layer_1-width_3
@@ -1237,6 +1250,8 @@ XscanEx2v@1 net@17[1] net@17[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5]
 +sir[6] sir[7] sir[8] sor[1] scanEx2
 XscanFx3@0 go clear silent sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] 
 +sic[8] sic[9] soc[1] scanFx3
+Xtc[1] tranCap
+Xtc[2] tranCap
 .ENDS drainStage
 
 *** CELL: orangeTSMC090nm:wire{sch}
@@ -1632,6 +1647,8 @@ XinvI@1 net@602 s[2] inv-X_10
 XlatchDri@0 fire take latchDriver60
 XpredDri6@2 fire si[9] pred driversL__predDri60wMC
 XsucORdri@1 fire net@320 succ sucORdri60
+Xtc[1] tranCap
+Xtc[2] tranCap
 Xwire90@1 net@537 net@602 wire90-602_3-layer_1-width_3
 Xwire90@12 net@533 net@454 wire90-602_3-layer_1-width_3
 Xwire90@15 fire[B] net@320 wire90-602_3-layer_1-width_3
@@ -1732,6 +1749,10 @@ XscanEx2@0 s[1] s[2] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
 +sir[8] sor[1] scanEx2
 XscanFx3@0 block extra fill sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] 
 +sic[8] sic[9] soc[1] scanFx3
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
 Xwire90@1 net@8 net@0 wire90-2550-layer_1-width_3
 Xwire90@3 fire net@16 wire90-2500-layer_1-width_3
 Xwire90@4 net@3 net@8 wire90-2550-layer_1-width_3
@@ -2140,6 +2161,15 @@ Xdata1in2@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18]
 XgaspWeak@0 net@59 sir[9] pred net@39 succ net@47 ain[TT] gaspWeak
 XscanEx1@0 net@39 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
 +sir[8] sor[1] scanEx1
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
+Xtc[6] tranCap
+Xtc[7] tranCap
+Xtc[8] tranCap
+Xtc[9] tranCap
 .ENDS weakStage
 
 *** CELL: orangeTSMC090nm:wire{sch}
@@ -2829,6 +2859,27 @@ XlatchDri@0 net@3 net@27 latchDriver60
 XlatchDri@1 net@7 net@23 latchDriver60
 XscanEx3@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
 +sir[7] sir[8] sor[1] scanEx3
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
+Xtc[6] tranCap
+Xtc[7] tranCap
+Xtc[8] tranCap
+Xtc[9] tranCap
+Xtc[10] tranCap
+Xtc[11] tranCap
+Xtc[12] tranCap
+Xtc[13] tranCap
+Xtc[14] tranCap
+Xtc[15] tranCap
+Xtc[16] tranCap
+Xtc[17] tranCap
+Xtc[18] tranCap
+Xtc[19] tranCap
+Xtc[20] tranCap
+Xtc[21] tranCap
 Xwire90@0 net@7 fire[B] wire90-1336_2-layer_1-width_3
 Xwire90@1 net@3 fire[A] wire90-1307-layer_1-width_3
 Xwire90@2 net@23 take[B] wire90-1336_2-layer_1-width_3
@@ -3101,6 +3152,8 @@ XlatchDri@0 net@5 net@20 latchDriver60
 XlatchDri@1 net@6 net@22 latchDriver60
 XscanEx2v@1 net@48[1] net@48[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] 
 +sir[6] sir[7] sir[8] sor[1] scanEx2
+Xtc[1] tranCap
+Xtc[2] tranCap
 Xwire90@0 fire[A] net@5 wire90-1300-layer_1-width_3
 Xwire90@1 fire[B] net@6 wire90-1301_9-layer_1-width_3
 Xwire90@2 net@20 net@23 wire90-1300-layer_1-width_3
@@ -3212,6 +3265,9 @@ Xins1in20@0 take[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
 XlatchDri@0 fire[1] take[1] latchDriver60
 XscanEx1@0 net@41 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
 +sir[8] sor[1] scanEx1
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
 Xwire90@1 net@1 fire[1] wire90-791_7-layer_1-width_3
 .ENDS plainDockStage
 
@@ -3500,6 +3556,7 @@ Xins1in20@0 take[epi] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17]
 XlatchDri@0 net@0 take[epi] latchDriver60
 XscanEx1@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
 +sir[8] sor[1] scanEx1
+XtranCap@0 tranCap
 Xwire90@0 net@0 net@5 wire90-372_8-layer_1-width_3
 .ENDS epiDockStage
 
@@ -3594,6 +3651,17 @@ XonDeck@0 m1[29] m1[30] net@11 flag[A][clr] flag[A][set] flag[D][clr]
 +onDeck
 XscanEx2v@2 net@62[1] net@62[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] 
 +sir[6] sir[7] sir[8] sor[1] scanEx2
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
+Xtc[6] tranCap
+Xtc[7] tranCap
+Xtc[8] tranCap
+Xtc[9] tranCap
+Xtc[10] tranCap
+Xtc[11] tranCap
 Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3
 .ENDS onDeckDockStage
 
@@ -4020,6 +4088,7 @@ XreQueue@0 epi[OTHER] epi[TAIL] fire[E] fire[R] sir[9] od[ABORT] od[HEAD]
 XscanEx1@0 s[1] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
 +sir[8] sin scanEx1
 XscanEx3p@1 s[2] s[3] s[4] sin sir[2] sir[3] sir[5] sor[1] scanEx3plain
+XtranCap@0 tranCap
 Xwire90@0 net@7 fire[R] wire90-1336_2-layer_1-width_3
 Xwire90@1 net@3 fire[E] wire90-1307-layer_1-width_3
 .ENDS rqDockStage
@@ -4443,18 +4512,18 @@ Xwire@0 a b wire-C_0_011f-5262_9-R_34_667m
 .ENDS wire90-5262_9-layer_1-width_3
 
 *** CELL: registersM:shadow{sch}
-.SUBCKT shadow dd[1] dd[2] dd[3] dd[4] dd[5] dd[6] hcl inB[15] inB[16] 
-+inB[17] inB[18] inB[19] inB[20] inn[10] inn[11] inn[12] inn[13] inn[14] 
-+inn[15] inn[16] inn[17] inn[18] inn[7] inn[8] inn[9] outt[16] outt[17] 
-+outt[18] outt[19] outt[20] outt[21] outt[22] outt[23] outt[24] outt[25] 
-+outt[26] outt[27] outt[28] outt[29] outt[30] outt[31] outt[32] outt[33] 
-+outt[34] outt[35] outt[36] outt[37]
-Xdl[1] hcl sign dd[1] outt[20] s[F] s[T] dataMux
-Xdl[2] hcl sign dd[2] outt[21] s[F] s[T] dataMux
-Xdl[3] hcl sign dd[3] outt[22] s[F] s[T] dataMux
-Xdl[4] hcl sign dd[4] outt[23] s[F] s[T] dataMux
-Xdl[5] hcl sign dd[5] outt[24] s[F] s[T] dataMux
-Xdl[6] hcl sign dd[6] outt[25] s[F] s[T] dataMux
+.SUBCKT shadow hcl inB[15] inB[16] inB[17] inB[18] inB[19] inB[20] inn[10] 
++inn[11] inn[12] inn[13] inn[14] inn[15] inn[16] inn[17] inn[18] inn[1] inn[2] 
++inn[3] inn[4] inn[5] inn[6] inn[7] inn[8] inn[9] outt[16] outt[17] outt[18] 
++outt[19] outt[20] outt[21] outt[22] outt[23] outt[24] outt[25] outt[26] 
++outt[27] outt[28] outt[29] outt[30] outt[31] outt[32] outt[33] outt[34] 
++outt[35] outt[36] outt[37]
+Xdl[1] hcl sign inn[1] outt[20] s[F] s[T] dataMux
+Xdl[2] hcl sign inn[2] outt[21] s[F] s[T] dataMux
+Xdl[3] hcl sign inn[3] outt[22] s[F] s[T] dataMux
+Xdl[4] hcl sign inn[4] outt[23] s[F] s[T] dataMux
+Xdl[5] hcl sign inn[5] outt[24] s[F] s[T] dataMux
+Xdl[6] hcl sign inn[6] outt[25] s[F] s[T] dataMux
 Xdl[7] hcl sign inn[7] outt[26] s[F] s[T] dataMux
 Xdl[8] hcl sign inn[8] outt[27] s[F] s[T] dataMux
 Xdl[9] hcl sign inn[9] outt[28] s[F] s[T] dataMux
@@ -4515,11 +4584,11 @@ Xdata2in6@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18]
 +out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] take[A] take[B] 
 +data2in60Cx37
 Xinv@0 take[B] net@66 inv-X_40
-Xshadow@0 out[1] out[2] out[3] out[4] out[5] out[6] net@66 ps[15] ps[16] 
-+ps[17] ps[18] ps[19] ps[20] out[10] out[11] out[12] out[13] out[14] out[15] 
-+out[16] out[17] out[18] out[7] out[8] out[9] ss[16] ss[17] ss[18] ss[19] 
-+ss[20] ss[21] ss[22] ss[23] ss[24] ss[25] ss[26] ss[27] ss[28] ss[29] ss[30] 
-+ss[31] ss[32] ss[33] ss[34] ss[35] ss[36] ss[37] shadow
+Xshadow@0 net@66 ps[15] ps[16] ps[17] ps[18] ps[19] ps[20] out[10] out[11] 
++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3] 
++out[4] out[5] out[6] out[7] out[8] out[9] ss[16] ss[17] ss[18] ss[19] ss[20] 
++ss[21] ss[22] ss[23] ss[24] ss[25] ss[26] ss[27] ss[28] ss[29] ss[30] ss[31] 
++ss[32] ss[33] ss[34] ss[35] ss[36] ss[37] shadow
 Xwire90@0 net@66 wire90@0_b wire90-4175_4-layer_1-width_3
 .ENDS newDregister
 
@@ -4632,12 +4701,13 @@ Xwire@0 a b wire-C_0_011f-358-R_34_667m
 +fire[M] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4] 
 +ps[5] ps[6] ps[7] ps[8] ps[9]
 Xaddr2in6@0 dp[10] dp[11] dp[12] dp[12] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5] 
-+dp[6] dp[7] dp[8] dp[9] ps[15] ps[10] ps[11] ps[12] ps[13] ps[13] ps[1] ps[2] 
-+ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[15] aout[10] aout[11] aout[12] 
-+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] 
-+aout[8] aout[9] aout[TT] take[dp] take[ps] addr2in60Cx15
++dp[6] dp[7] dp[8] dp[9] ps[15not] ps[10] ps[11] ps[12] ps[13] ps[13] ps[1] 
++ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[15not] aout[10] aout[11] 
++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] 
++aout[7] aout[8] aout[9] aout[TT] take[dp] take[ps] addr2in60Cx15
 Xinv@1 ps[13] net@46 inv-X_10
 Xinv@2 ps[14] net@47 inv-X_10
+Xinv@3 ps[15] ps[15not] inv-X_10
 XinvI@0 net@19 net@40 inv-X_30
 XlatchAnd@0 ps[14] fire[M] net@43 latchAndDriver30
 Xnand3in6@1 net@25 net@28 fire[M] net@19 nand3in6_6
@@ -4700,6 +4770,16 @@ XscanEx1@0 net@27 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
 +sir[8] sor[1] scanEx1
 XsucANDdr@0 ps[16] fire[M] succ[D] sucANDdri60
 XsucANDdr@1 ps[15] fire[M] succ[T] sucANDdri60
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
+Xtc[6] tranCap
+Xtc[7] tranCap
+Xtc[8] tranCap
+Xtc[9] tranCap
+Xtc[10] tranCap
 Xwire90@0 net@10 net@13 wire90-4175_4-layer_1-width_3
 .ENDS litDandP
 
@@ -4845,6 +4925,25 @@ XminusOne@0 ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] net@11
 +m1cate[6][T] sir[9] pred[R] net@47 succ[m1] minusOne
 XscanEx1@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
 +sir[8] sor[1] scanEx1
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
+Xtc[6] tranCap
+Xtc[7] tranCap
+Xtc[8] tranCap
+Xtc[9] tranCap
+Xtc[10] tranCap
+Xtc[11] tranCap
+Xtc[12] tranCap
+Xtc[13] tranCap
+Xtc[14] tranCap
+Xtc[15] tranCap
+Xtc[16] tranCap
+Xtc[17] tranCap
+Xtc[18] tranCap
+Xtc[19] tranCap
 Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3
 .ENDS mOneDockStage
 
@@ -4912,6 +5011,9 @@ Xins1in20@0 take[1] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
 XlatchDri@0 fire[1] net@0 latchDriver60
 XmuxForOD@0 ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[8] outLO[1] outLO[2] 
 +outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[20] muxForPS
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
 Xwire90@0 net@0 take[1] wire90-544_2-layer_1-width_3
 .ENDS dockPSreg
 
@@ -5768,116 +5870,132 @@ Xwire90@7 net@454 count[T] wire90-1283_3-layer_1-width_3
 .ENDS ilcOdd
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-349_2-R_34_667m a b
-Ccap@0 gnd net@14 1.28f
-Ccap@1 gnd net@8 1.28f
-Ccap@2 gnd net@11 1.28f
-Rres@0 net@14 a 2.018
-Rres@1 net@11 net@14 4.035
-Rres@2 b net@8 2.018
-Rres@3 net@8 net@11 4.035
-.ENDS wire-C_0_011f-349_2-R_34_667m
+.SUBCKT wire-C_0_011f-353_7-R_34_667m a b
+Ccap@0 gnd net@14 1.297f
+Ccap@1 gnd net@8 1.297f
+Ccap@2 gnd net@11 1.297f
+Rres@0 net@14 a 2.044
+Rres@1 net@11 net@14 4.087
+Rres@2 b net@8 2.044
+Rres@3 net@8 net@11 4.087
+.ENDS wire-C_0_011f-353_7-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-353_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-353_7-R_34_667m
+.ENDS wire90-353_7-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-470_8-R_34_667m a b
+Ccap@0 gnd net@14 1.726f
+Ccap@1 gnd net@8 1.726f
+Ccap@2 gnd net@11 1.726f
+Rres@0 net@14 a 2.72
+Rres@1 net@11 net@14 5.44
+Rres@2 b net@8 2.72
+Rres@3 net@8 net@11 5.44
+.ENDS wire-C_0_011f-470_8-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-349_2-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-349_2-R_34_667m
-.ENDS wire90-349_2-layer_1-width_3
+.SUBCKT wire90-470_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-470_8-R_34_667m
+.ENDS wire90-470_8-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-475_3-R_34_667m a b
-Ccap@0 gnd net@14 1.743f
-Ccap@1 gnd net@8 1.743f
-Ccap@2 gnd net@11 1.743f
-Rres@0 net@14 a 2.746
-Rres@1 net@11 net@14 5.492
-Rres@2 b net@8 2.746
-Rres@3 net@8 net@11 5.492
-.ENDS wire-C_0_011f-475_3-R_34_667m
+.SUBCKT wire-C_0_011f-418_3-R_34_667m a b
+Ccap@0 gnd net@14 1.534f
+Ccap@1 gnd net@8 1.534f
+Ccap@2 gnd net@11 1.534f
+Rres@0 net@14 a 2.417
+Rres@1 net@11 net@14 4.834
+Rres@2 b net@8 2.417
+Rres@3 net@8 net@11 4.834
+.ENDS wire-C_0_011f-418_3-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-475_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-475_3-R_34_667m
-.ENDS wire90-475_3-layer_1-width_3
+.SUBCKT wire90-418_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-418_3-R_34_667m
+.ENDS wire90-418_3-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-422_8-R_34_667m a b
-Ccap@0 gnd net@14 1.55f
-Ccap@1 gnd net@8 1.55f
-Ccap@2 gnd net@11 1.55f
-Rres@0 net@14 a 2.443
-Rres@1 net@11 net@14 4.886
-Rres@2 b net@8 2.443
-Rres@3 net@8 net@11 4.886
-.ENDS wire-C_0_011f-422_8-R_34_667m
+.SUBCKT wire-C_0_011f-480_3-R_34_667m a b
+Ccap@0 gnd net@14 1.761f
+Ccap@1 gnd net@8 1.761f
+Ccap@2 gnd net@11 1.761f
+Rres@0 net@14 a 2.775
+Rres@1 net@11 net@14 5.55
+Rres@2 b net@8 2.775
+Rres@3 net@8 net@11 5.55
+.ENDS wire-C_0_011f-480_3-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-422_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-422_8-R_34_667m
-.ENDS wire90-422_8-layer_1-width_3
+.SUBCKT wire90-480_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-480_3-R_34_667m
+.ENDS wire90-480_3-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-484_8-R_34_667m a b
-Ccap@0 gnd net@14 1.778f
-Ccap@1 gnd net@8 1.778f
-Ccap@2 gnd net@11 1.778f
-Rres@0 net@14 a 2.801
-Rres@1 net@11 net@14 5.602
-Rres@2 b net@8 2.801
-Rres@3 net@8 net@11 5.602
-.ENDS wire-C_0_011f-484_8-R_34_667m
+.SUBCKT wire-C_0_011f-403_3-R_34_667m a b
+Ccap@0 gnd net@14 1.479f
+Ccap@1 gnd net@8 1.479f
+Ccap@2 gnd net@11 1.479f
+Rres@0 net@14 a 2.33
+Rres@1 net@11 net@14 4.66
+Rres@2 b net@8 2.33
+Rres@3 net@8 net@11 4.66
+.ENDS wire-C_0_011f-403_3-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-484_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-484_8-R_34_667m
-.ENDS wire90-484_8-layer_1-width_3
+.SUBCKT wire90-403_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-403_3-R_34_667m
+.ENDS wire90-403_3-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-407_8-R_34_667m a b
-Ccap@0 gnd net@14 1.495f
-Ccap@1 gnd net@8 1.495f
-Ccap@2 gnd net@11 1.495f
-Rres@0 net@14 a 2.356
-Rres@1 net@11 net@14 4.712
-Rres@2 b net@8 2.356
-Rres@3 net@8 net@11 4.712
-.ENDS wire-C_0_011f-407_8-R_34_667m
+.SUBCKT wire-C_0_011f-1293_4-R_34_667m a b
+Ccap@0 gnd net@14 4.742f
+Ccap@1 gnd net@8 4.742f
+Ccap@2 gnd net@11 4.742f
+Rres@0 net@14 a 7.473
+Rres@1 net@11 net@14 14.946
+Rres@2 b net@8 7.473
+Rres@3 net@8 net@11 14.946
+.ENDS wire-C_0_011f-1293_4-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-407_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-407_8-R_34_667m
-.ENDS wire90-407_8-layer_1-width_3
+.SUBCKT wire90-1293_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1293_4-R_34_667m
+.ENDS wire90-1293_4-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-999_1-R_34_667m a b
-Ccap@0 gnd net@14 3.663f
-Ccap@1 gnd net@8 3.663f
-Ccap@2 gnd net@11 3.663f
-Rres@0 net@14 a 5.773
-Rres@1 net@11 net@14 11.545
-Rres@2 b net@8 5.773
-Rres@3 net@8 net@11 11.545
-.ENDS wire-C_0_011f-999_1-R_34_667m
+.SUBCKT wire-C_0_011f-1291_5-R_34_667m a b
+Ccap@0 gnd net@14 4.735f
+Ccap@1 gnd net@8 4.735f
+Ccap@2 gnd net@11 4.735f
+Rres@0 net@14 a 7.462
+Rres@1 net@11 net@14 14.924
+Rres@2 b net@8 7.462
+Rres@3 net@8 net@11 14.924
+.ENDS wire-C_0_011f-1291_5-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-999_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-999_1-R_34_667m
-.ENDS wire90-999_1-layer_1-width_3
+.SUBCKT wire90-1291_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1291_5-R_34_667m
+.ENDS wire90-1291_5-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1276_9-R_34_667m a b
-Ccap@0 gnd net@14 4.682f
-Ccap@1 gnd net@8 4.682f
-Ccap@2 gnd net@11 4.682f
-Rres@0 net@14 a 7.378
-Rres@1 net@11 net@14 14.755
-Rres@2 b net@8 7.378
-Rres@3 net@8 net@11 14.755
-.ENDS wire-C_0_011f-1276_9-R_34_667m
+.SUBCKT wire-C_0_011f-1019_7-R_34_667m a b
+Ccap@0 gnd net@14 3.739f
+Ccap@1 gnd net@8 3.739f
+Ccap@2 gnd net@11 3.739f
+Rres@0 net@14 a 5.892
+Rres@1 net@11 net@14 11.783
+Rres@2 b net@8 5.892
+Rres@3 net@8 net@11 11.783
+.ENDS wire-C_0_011f-1019_7-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1276_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1276_9-R_34_667m
-.ENDS wire90-1276_9-layer_1-width_3
+.SUBCKT wire90-1019_7-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1019_7-R_34_667m
+.ENDS wire90-1019_7-layer_1-width_3
 
 *** CELL: loopCountM:ilc{sch}
 .SUBCKT ilc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8] 
@@ -5889,15 +6007,16 @@ XilcEven@0 bitt[2] bitt[4] bitt[6] bitt[8] do[2] do[4] do[6] ilc[decLO]
 +inLO[2] inLO[4] inLO[6] inLO[8] ilc[load] zero ilcEven
 XilcOdd@0 bitt[1] bitt[3] bitt[5] bitt[7] do[3] do[5] do[7] ilc[decLO] 
 +inLO[1] inLO[3] inLO[5] ilc[load] zero ilcOdd
-Xnand2@0 bitt[8] do[7] ilc[mo] nand2-X_10
-Xnand3@0 bitt[8] bitt[7] zero ilc[do] nand3-X_6_667
-Xwire90@1 wire90@1_a do[2] wire90-349_2-layer_1-width_3
-Xwire90@2 wire90@2_a do[3] wire90-475_3-layer_1-width_3
-Xwire90@3 wire90@3_a do[4] wire90-422_8-layer_1-width_3
-Xwire90@4 wire90@4_a do[5] wire90-484_8-layer_1-width_3
-Xwire90@5 wire90@5_a do[6] wire90-407_8-layer_1-width_3
-Xwire90@6 wire90@6_a do[7] wire90-999_1-layer_1-width_3
-Xwire90@41 zero net@422 wire90-1276_9-layer_1-width_3
+Xnand2@0 bitt[8] net@426 ilc[mo] nand2-X_10
+Xnand3@0 bitt[8] net@423 zero ilc[do] nand3-X_6_667
+Xwire90@1 wire90@1_a do[2] wire90-353_7-layer_1-width_3
+Xwire90@2 wire90@2_a do[3] wire90-470_8-layer_1-width_3
+Xwire90@3 wire90@3_a do[4] wire90-418_3-layer_1-width_3
+Xwire90@4 wire90@4_a do[5] wire90-480_3-layer_1-width_3
+Xwire90@5 wire90@5_a do[6] wire90-403_3-layer_1-width_3
+Xwire90@41 zero net@422 wire90-1293_4-layer_1-width_3
+Xwire90@42 net@423 bitt[7] wire90-1291_5-layer_1-width_3
+Xwire90@43 net@426 do[7] wire90-1019_7-layer_1-width_3
 .ENDS ilc
 
 *** CELL: driversL:predORdri20wMC{sch}
@@ -5913,43 +6032,6 @@ Xinv@0 pred net@145 inv-X_4
 Xwire90@0 net@217 net@145 wire90-243_6-layer_1-width_3
 .ENDS predORdri20wMC
 
-*** CELL: redFive:nms2{sch}
-.SUBCKT nms2-X_1_5 d g g2
-XNMOS@0 d g2 net@0 NMOSx-X_3
-XNMOS@1 net@0 g gnd NMOSx-X_3
-.ENDS nms2-X_1_5
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_1_5 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_3
-XPMOS@1 d g2 net@2 PMOSx-X_3
-.ENDS pms2-X_1_5
-
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-154_5-R_34_667m a b
-Ccap@0 gnd net@14 0.566f
-Ccap@1 gnd net@8 0.566f
-Ccap@2 gnd net@11 0.566f
-Rres@0 net@14 a 0.893
-Rres@1 net@11 net@14 1.785
-Rres@2 b net@8 0.893
-Rres@3 net@8 net@11 1.785
-.ENDS wire-C_0_011f-154_5-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-154_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-154_5-R_34_667m
-.ENDS wire90-154_5-layer_1-width_3
-
-*** CELL: gates1inM:amp1.5{sch}
-.SUBCKT amp1_5 in[1] out[1]
-Xnms2a@0 net@16 in[1] in[1] nms2-X_1_5
-Xnms2a@1 out[1] net@17 net@17 nms2-X_1_5
-Xpms2a@0 net@16 in[1] in[1] pms2-X_1_5
-Xpms2a@1 out[1] net@17 net@17 pms2-X_1_5
-Xwire90@0 net@16 net@17 wire90-154_5-layer_1-width_3
-.ENDS amp1_5
-
 *** CELL: redFive:nand2n{sch}
 .SUBCKT nand2n-X_20 ina inb out
 Xnand2@0 ina inb out nand2-X_20
@@ -6167,13 +6249,15 @@ Xwire@0 a b wire-C_0_011f-590_5-R_34_667m
 *** CELL: moveM:races{sch}
 .SUBCKT races bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] in[D] in[T] succ torp 
 +winLO[M]
-Xamp1_5@0 winLO[M] net@184 amp1_5
 Xarbiter2@0 net@131 net@128 torp in[D] arbiter2
 Xarbiter2@1 net@130 net@129 torp in[T] arbiter2
+Xinv@0 winLO[M] net@192 inv-X_5
 XinvI@0 net@150 fire[T] inv-X_20
+XinvI@1 net@187 net@186 inv-X_5
+XinvI@3 net@187 invI@3_out inv-X_10
 Xnand2@0 bit[Di] do[Tp] net@35 nand2-X_10
 Xnand2@1 bit[Ti] do[Tp] net@42 nand2-X_10
-Xnand2@2 net@94 do[Mv] net@86 nand2-X_5
+Xnand2@2 net@94 do[Mv] net@86 nand2-X_10
 Xnand2n@0 bit[Di] net@11 net@57 nand2n-X_20
 Xnand2n@1 bit[Ti] net@53 net@60 nand2n-X_20
 Xnand3in4@0 net@159 net@123 net@98 winLO[M] nand3in44s
@@ -6192,9 +6276,10 @@ Xwire90@7 net@43 net@48 wire90-783-layer_1-width_3
 Xwire90@8 net@60 net@123 wire90-1254_1-layer_1-width_3
 Xwire90@9 net@57 net@159 wire90-1300_1-layer_1-width_3
 Xwire90@11 net@86 net@153 wire90-392_9-layer_1-width_3
-Xwire90@12 net@94 net@184 wire90-174_7-layer_1-width_3
+Xwire90@12 net@94 net@186 wire90-174_7-layer_1-width_3
 Xwire90@13 net@152 net@98 wire90-1154_9-layer_1-width_3
 Xwire90@15 net@151 net@150 wire90-590_5-layer_1-width_3
+Xwire90@16 net@187 net@192 wire90-174_7-layer_1-width_3
 .ENDS races
 
 *** CELL: orangeTSMC090nm:wire{sch}
@@ -6614,24 +6699,72 @@ Xwire90@3 w[4] wire90@3_b wire90-503_4-layer_1-width_3
 Xwire90@4 w[5] wire90@4_b wire90-503_4-layer_1-width_3
 .ENDS predSucDri
 
-*** CELL: orangeTSMC090nm:PMOS4x{sch}
-.SUBCKT PMOS4x-X_3 b d g s
-MPMOS4f@0 d g s b pch W='18*(1+ABP/sqrt(18*2))' L='2' 
-+DELVTO='AVT0P/sqrt(18*2)'
-.ENDS PMOS4x-X_3
+*** CELL: redFive:pms2{sch}
+.SUBCKT pms2-X_1_5 d g g2
+XPMOS@0 net@2 g vdd PMOSx-X_3
+XPMOS@1 d g2 net@2 PMOSx-X_3
+.ENDS pms2-X_1_5
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-219_8-R_34_667m a b
+Ccap@0 gnd net@14 0.806f
+Ccap@1 gnd net@8 0.806f
+Ccap@2 gnd net@11 0.806f
+Rres@0 net@14 a 1.27
+Rres@1 net@11 net@14 2.54
+Rres@2 b net@8 1.27
+Rres@3 net@8 net@11 2.54
+.ENDS wire-C_0_011f-219_8-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-219_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-219_8-R_34_667m
+.ENDS wire90-219_8-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-60_2-R_34_667m a b
+Ccap@0 gnd net@14 0.221f
+Ccap@1 gnd net@8 0.221f
+Ccap@2 gnd net@11 0.221f
+Rres@0 net@14 a 0.348
+Rres@1 net@11 net@14 0.696
+Rres@2 b net@8 0.348
+Rres@3 net@8 net@11 0.696
+.ENDS wire-C_0_011f-60_2-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-60_2-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-60_2-R_34_667m
+.ENDS wire90-60_2-layer_1-width_3
 
 *** CELL: driversL:predCond20wMC{sch}
 .SUBCKT predCond20wMC cond in mc pred
 XNMOSx@1 pred mc gnd NMOSx-X_10
-XPMOS4x@0 PMOS4x@0_b pred in net@217 PMOS4x-X_3
-XPMOS4x@1 PMOS4x@1_b pred cond net@210 PMOS4x-X_3
+XPMOSx@0 pred in net@217 PMOSx-X_3
+XPMOSx@1 pred cond net@210 PMOSx-X_3
 Xinv@0 pred net@145 inv-X_10
 Xnms2@0 pred cond in nms2-X_20
 Xpms2a@0 net@217 mc net@200 pms2-X_1_5
-Xwire90@0 net@200 net@145 wire90-243_6-layer_1-width_3
-Xwire90@1 net@217 net@210 wire90-243_6-layer_1-width_3
+Xwire90@0 net@200 net@145 wire90-219_8-layer_1-width_3
+Xwire90@1 net@217 net@210 wire90-60_2-layer_1-width_3
 .ENDS predCond20wMC
 
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-219_5-R_34_667m a b
+Ccap@0 gnd net@14 0.805f
+Ccap@1 gnd net@8 0.805f
+Ccap@2 gnd net@11 0.805f
+Rres@0 net@14 a 1.268
+Rres@1 net@11 net@14 2.536
+Rres@2 b net@8 1.268
+Rres@3 net@8 net@11 2.536
+.ENDS wire-C_0_011f-219_5-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-219_5-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-219_5-R_34_667m
+.ENDS wire90-219_5-layer_1-width_3
+
 *** CELL: driversL:predCond20wMS{sch}
 .SUBCKT predCond20wMS cond in mc pred
 XPMOSx@0 pred cond net@210 PMOSx-X_3
@@ -6641,8 +6774,8 @@ XinvLT@0 mc net@240 invLT-X_5
 Xnms2@0 pred cond in nms2-X_20
 Xpms1@0 pred net@240 pms1-X_3
 Xpms2a@0 net@217 mc net@200 pms2-X_1_5
-Xwire90@0 net@200 net@145 wire90-243_6-layer_1-width_3
-Xwire90@1 net@217 net@210 wire90-243_6-layer_1-width_3
+Xwire90@0 net@200 net@145 wire90-219_5-layer_1-width_3
+Xwire90@1 net@217 net@210 wire90-60_2-layer_1-width_3
 .ENDS predCond20wMS
 
 *** CELL: predicateM:predFlagDri{sch}
@@ -6875,52 +7008,68 @@ Xwire90@5 net@67 net@71 wire90-215_4-layer_1-width_3
 .ENDS ohPredPred
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-556_1-R_34_667m a b
-Ccap@0 gnd net@14 2.039f
-Ccap@1 gnd net@8 2.039f
-Ccap@2 gnd net@11 2.039f
-Rres@0 net@14 a 3.213
-Rres@1 net@11 net@14 6.426
-Rres@2 b net@8 3.213
-Rres@3 net@8 net@11 6.426
-.ENDS wire-C_0_011f-556_1-R_34_667m
+.SUBCKT wire-C_0_011f-1036_4-R_34_667m a b
+Ccap@0 gnd net@14 3.8f
+Ccap@1 gnd net@8 3.8f
+Ccap@2 gnd net@11 3.8f
+Rres@0 net@14 a 5.988
+Rres@1 net@11 net@14 11.976
+Rres@2 b net@8 5.988
+Rres@3 net@8 net@11 11.976
+.ENDS wire-C_0_011f-1036_4-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-556_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-556_1-R_34_667m
-.ENDS wire90-556_1-layer_1-width_3
+.SUBCKT wire90-1036_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-1036_4-R_34_667m
+.ENDS wire90-1036_4-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-557-R_34_667m a b
-Ccap@0 gnd net@14 2.042f
-Ccap@1 gnd net@8 2.042f
-Ccap@2 gnd net@11 2.042f
-Rres@0 net@14 a 3.218
-Rres@1 net@11 net@14 6.436
-Rres@2 b net@8 3.218
-Rres@3 net@8 net@11 6.436
-.ENDS wire-C_0_011f-557-R_34_667m
+.SUBCKT wire-C_0_011f-575-R_34_667m a b
+Ccap@0 gnd net@14 2.108f
+Ccap@1 gnd net@8 2.108f
+Ccap@2 gnd net@11 2.108f
+Rres@0 net@14 a 3.322
+Rres@1 net@11 net@14 6.644
+Rres@2 b net@8 3.322
+Rres@3 net@8 net@11 6.644
+.ENDS wire-C_0_011f-575-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-557-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-557-R_34_667m
-.ENDS wire90-557-layer_1-width_3
+.SUBCKT wire90-575-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-575-R_34_667m
+.ENDS wire90-575-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-318_8-R_34_667m a b
-Ccap@0 gnd net@14 1.169f
-Ccap@1 gnd net@8 1.169f
-Ccap@2 gnd net@11 1.169f
-Rres@0 net@14 a 1.842
-Rres@1 net@11 net@14 3.684
-Rres@2 b net@8 1.842
-Rres@3 net@8 net@11 3.684
-.ENDS wire-C_0_011f-318_8-R_34_667m
+.SUBCKT wire-C_0_011f-863_3-R_34_667m a b
+Ccap@0 gnd net@14 3.165f
+Ccap@1 gnd net@8 3.165f
+Ccap@2 gnd net@11 3.165f
+Rres@0 net@14 a 4.988
+Rres@1 net@11 net@14 9.976
+Rres@2 b net@8 4.988
+Rres@3 net@8 net@11 9.976
+.ENDS wire-C_0_011f-863_3-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-318_8-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-318_8-R_34_667m
-.ENDS wire90-318_8-layer_1-width_3
+.SUBCKT wire90-863_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-863_3-R_34_667m
+.ENDS wire90-863_3-layer_1-width_3
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-355_3-R_34_667m a b
+Ccap@0 gnd net@14 1.303f
+Ccap@1 gnd net@8 1.303f
+Ccap@2 gnd net@11 1.303f
+Rres@0 net@14 a 2.053
+Rres@1 net@11 net@14 4.106
+Rres@2 b net@8 2.053
+Rres@3 net@8 net@11 4.106
+.ENDS wire-C_0_011f-355_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-355_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-355_3-R_34_667m
+.ENDS wire90-355_3-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
 .SUBCKT wire-C_0_011f-1035_5-R_34_667m a b
@@ -6939,68 +7088,68 @@ Xwire@0 a b wire-C_0_011f-1035_5-R_34_667m
 .ENDS wire90-1035_5-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-945_6-R_34_667m a b
-Ccap@0 gnd net@14 3.467f
-Ccap@1 gnd net@8 3.467f
-Ccap@2 gnd net@11 3.467f
-Rres@0 net@14 a 5.463
-Rres@1 net@11 net@14 10.927
-Rres@2 b net@8 5.463
-Rres@3 net@8 net@11 10.927
-.ENDS wire-C_0_011f-945_6-R_34_667m
+.SUBCKT wire-C_0_011f-602_8-R_34_667m a b
+Ccap@0 gnd net@14 2.21f
+Ccap@1 gnd net@8 2.21f
+Ccap@2 gnd net@11 2.21f
+Rres@0 net@14 a 3.483
+Rres@1 net@11 net@14 6.966
+Rres@2 b net@8 3.483
+Rres@3 net@8 net@11 6.966
+.ENDS wire-C_0_011f-602_8-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-945_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-945_6-R_34_667m
-.ENDS wire90-945_6-layer_1-width_3
+.SUBCKT wire90-602_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-602_8-R_34_667m
+.ENDS wire90-602_8-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-1126_1-R_34_667m a b
-Ccap@0 gnd net@14 4.129f
-Ccap@1 gnd net@8 4.129f
-Ccap@2 gnd net@11 4.129f
-Rres@0 net@14 a 6.506
-Rres@1 net@11 net@14 13.013
-Rres@2 b net@8 6.506
-Rres@3 net@8 net@11 13.013
-.ENDS wire-C_0_011f-1126_1-R_34_667m
+.SUBCKT wire-C_0_011f-613_9-R_34_667m a b
+Ccap@0 gnd net@14 2.251f
+Ccap@1 gnd net@8 2.251f
+Ccap@2 gnd net@11 2.251f
+Rres@0 net@14 a 3.547
+Rres@1 net@11 net@14 7.094
+Rres@2 b net@8 3.547
+Rres@3 net@8 net@11 7.094
+.ENDS wire-C_0_011f-613_9-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-1126_1-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-1126_1-R_34_667m
-.ENDS wire90-1126_1-layer_1-width_3
+.SUBCKT wire90-613_9-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-613_9-R_34_667m
+.ENDS wire90-613_9-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-361_6-R_34_667m a b
-Ccap@0 gnd net@14 1.326f
-Ccap@1 gnd net@8 1.326f
-Ccap@2 gnd net@11 1.326f
-Rres@0 net@14 a 2.089
-Rres@1 net@11 net@14 4.178
-Rres@2 b net@8 2.089
-Rres@3 net@8 net@11 4.178
-.ENDS wire-C_0_011f-361_6-R_34_667m
+.SUBCKT wire-C_0_011f-778-R_34_667m a b
+Ccap@0 gnd net@14 2.853f
+Ccap@1 gnd net@8 2.853f
+Ccap@2 gnd net@11 2.853f
+Rres@0 net@14 a 4.495
+Rres@1 net@11 net@14 8.99
+Rres@2 b net@8 4.495
+Rres@3 net@8 net@11 8.99
+.ENDS wire-C_0_011f-778-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-361_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-361_6-R_34_667m
-.ENDS wire90-361_6-layer_1-width_3
+.SUBCKT wire90-778-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-778-R_34_667m
+.ENDS wire90-778-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-2526_6-R_34_667m a b
-Ccap@0 gnd net@14 9.264f
-Ccap@1 gnd net@8 9.264f
-Ccap@2 gnd net@11 9.264f
-Rres@0 net@14 a 14.598
-Rres@1 net@11 net@14 29.196
-Rres@2 b net@8 14.598
-Rres@3 net@8 net@11 29.196
-.ENDS wire-C_0_011f-2526_6-R_34_667m
+.SUBCKT wire-C_0_011f-2516_8-R_34_667m a b
+Ccap@0 gnd net@14 9.228f
+Ccap@1 gnd net@8 9.228f
+Ccap@2 gnd net@11 9.228f
+Rres@0 net@14 a 14.542
+Rres@1 net@11 net@14 29.083
+Rres@2 b net@8 14.542
+Rres@3 net@8 net@11 29.083
+.ENDS wire-C_0_011f-2516_8-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-2526_6-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-2526_6-R_34_667m
-.ENDS wire90-2526_6-layer_1-width_3
+.SUBCKT wire90-2516_8-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-2516_8-R_34_667m
+.ENDS wire90-2516_8-layer_1-width_3
 
 *** CELL: predicateM:ohPredAll{sch}
 .SUBCKT ohPredAll do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr] 
@@ -7015,7 +7164,7 @@ XinvI@1 net@63 fire[skip] inv-X_10
 Xnand2_sy@0 net@94 net@11 net@63 nand2_sy-X_10
 Xnand2n_s@0 net@147 net@84 fire[both] nand2n_sy-X_30
 Xnand3in2@1 net@46 net@41 net@11 net@82 net@21 nand3in20sr
-Xnor2n_sy@0 ps[skip] ps[do] net@39 nor2n_sy-X_5
+Xnor2n_sy@0 ps[skip] ps[do] net@39 nor2n_sy-X_10
 Xnor2n_sy@2 do[Lt] do[Mv] net@38 nor2n_sy-X_5
 XohPredDo@1 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] net@149 flag[A][clr] 
 +flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] mc ps[do] 
@@ -7025,15 +7174,15 @@ XohPredPr@1 net@92 net@139 net@160 flag[A][clr] flag[A][set] flag[B][clr]
 +m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] 
 +m1cate[5][T] m1cate[6][F] m1cate[6][T] mc net@19 s[1] s[2] ohPredPred
 XscanEx2h@0 s[1] s[2] mc p1p p2p rd sin sout scanEx2h
-Xwire90@0 net@39 net@11 wire90-556_1-layer_1-width_3
-Xwire90@1 net@38 net@41 wire90-557-layer_1-width_3
-Xwire90@2 net@46 net@139 wire90-775_9-layer_1-width_3
-Xwire90@3 net@21 net@19 wire90-318_8-layer_1-width_3
+Xwire90@0 net@39 net@11 wire90-1036_4-layer_1-width_3
+Xwire90@1 net@38 net@41 wire90-575-layer_1-width_3
+Xwire90@2 net@46 net@139 wire90-863_3-layer_1-width_3
+Xwire90@3 net@21 net@19 wire90-355_3-layer_1-width_3
 Xwire90@4 net@82 net@84 wire90-1035_5-layer_1-width_3
-Xwire90@5 net@147 net@63 wire90-945_6-layer_1-width_3
-Xwire90@6 net@92 net@94 wire90-1126_1-layer_1-width_3
-Xwire90@7 net@149 fire[skip] wire90-361_6-layer_1-width_3
-Xwire90@9 fire[both] net@160 wire90-2526_6-layer_1-width_3
+Xwire90@5 net@147 net@63 wire90-602_8-layer_1-width_3
+Xwire90@6 net@92 net@94 wire90-613_9-layer_1-width_3
+Xwire90@7 net@149 fire[skip] wire90-778-layer_1-width_3
+Xwire90@9 fire[both] net@160 wire90-2516_8-layer_1-width_3
 .ENDS ohPredAll
 
 *** CELL: orangeTSMC090nm:wire{sch}
@@ -7793,6 +7942,20 @@ XohPredAl@0 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr]
 XolcWcont@0 sel[rD] do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] net@165 
 +inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] sir[9] sir[3] sir[2] sir[5] 
 +net@279 net@244 olcWcont
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
+Xtc[6] tranCap
+Xtc[7] tranCap
+Xtc[8] tranCap
+Xtc[9] tranCap
+Xtc[10] tranCap
+Xtc[11] tranCap
+Xtc[12] tranCap
+Xtc[13] tranCap
+Xtc[14] tranCap
 Xwire90@5 wire90@5_a flag[A][set] wire90-3750-layer_1-width_3
 Xwire90@6 wire90@6_a flag[A][clr] wire90-3560-layer_1-width_3
 Xwire90@7 wire90@7_a flag[B][set] wire90-3750-layer_1-width_3
@@ -7811,11 +7974,9 @@ Xwire90@24 net@165 ilc[load] wire90-867_8-layer_1-width_3
 +m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] 
 +m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] 
 +m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] 
-+ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] 
-+ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] 
-+ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] 
-+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] 
-+succ[sf] take[ps]
++ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] 
++ps[7] ps[8] ps[9] ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] 
++sir[7] sir[8] sir[9] sor[1] succ[sf]
 XdockPSre@0 net@39 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] 
 +m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] 
 +m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] 
@@ -7823,7 +7984,7 @@ XdockPSre@0 net@39 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
 +inLO[6] inLO[8] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] 
 +ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27] 
 +ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[3] 
-+ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] take[ps] dockPSreg
++ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] dockPSre@0_take[1] dockPSreg
 XoutDockC@0 ps[18] ps[19] ps[20] do[Lt] epi[torp] fire[M] net@6 flag[A][clr] 
 +flag[A][set] flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] 
 +inLO[4] inLO[5] inLO[6] inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] 
@@ -7890,11 +8051,9 @@ XoutDockP@0 net@91 epi[torp] fire[M] flag[A][clr] flag[A][set] net@82
 +m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] 
 +m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] 
 +m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] 
-+ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] 
-+ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] 
-+ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] net@47[8] sir[2] 
-+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@48[8] succ[D] take[ps] 
-+outDockPredStage
++ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] 
++ps[9] ps[do] ps[skip] net@47[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sir[9] net@48[8] succ[D] outDockPredStage
 Xwire90@0 net@79 net@82 wire90-4175_4-layer_1-width_3
 Xwire90@1 net@90 fire[M] wire90-4175_4-layer_1-width_3
 Xwire90@2 net@89 net@91 wire90-4175_4-layer_1-width_3
@@ -8042,6 +8201,11 @@ XinvI@0 net@240 s[1] inv-X_10
 XpredDri6@0 fire mc pred driversJ__predDri60wMC
 XsucANDdr@2 to[A] fire succ[A] sucANDdri60
 XsucANDdr@3 to[B] fire succ[B] sucANDdri60
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
 Xwire90@0 net@240 net@163 wire90-602_3-layer_1-width_3
 .ENDS gaspTap
 
@@ -8087,13 +8251,16 @@ XscanEx1@0 net@54 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7]
 +sir[8] sor[1] scanEx1
 XscanFx2@0 to[A] to[B] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] 
 +sic[8] sic[9] soc[1] scanFx2
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
 .ENDS tapStage
 
 *** CELL: stageGroupsM:tapPropStop{sch}
 .SUBCKT tapPropStop ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] 
-+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] 
++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] 
 +aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] 
-+aout[7] aout[8] aout[9] aout[T] cin fin fout in[10] in[11] in[12] in[13] 
++aout[7] aout[8] aout[9] aout[TT] cin fin fout in[10] in[11] in[12] in[13] 
 +in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] 
 +in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] 
 +in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] 
@@ -8108,7 +8275,7 @@ XscanFx2@0 to[A] to[B] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7]
 Xinstruct@0 cin net@91 fin fout net@105[8] sod[2] sod[3] sod[4] sod[5] sid[6] 
 +sid[7] sid[8] sid[9] sod[1] instructionCount
 XproperSt@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] 
-+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] net@107[41] net@107[40] 
++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] net@107[41] net@107[40] 
 +net@107[39] net@107[38] net@107[37] net@107[50] net@107[49] net@107[48] 
 +net@107[47] net@107[46] net@107[45] net@107[44] net@107[43] net@107[42] 
 +net@107[51] net@91 properSt@1_fire in[10] in[11] in[12] in[13] in[14] in[15] 
@@ -8129,7 +8296,7 @@ XtapStage@2 net@107[41] net@107[40] net@107[39] net@107[38] net@107[37]
 +net@107[50] net@107[49] net@107[48] net@107[47] net@107[46] net@107[45] 
 +net@107[44] net@107[43] net@107[42] net@107[51] aout[10] aout[11] aout[12] 
 +aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] 
-+aout[8] aout[9] aout[T] net@107[27] net@107[26] net@107[25] net@107[24] 
++aout[8] aout[9] aout[TT] net@107[27] net@107[26] net@107[25] net@107[24] 
 +net@107[23] net@107[22] net@107[21] net@107[20] net@107[19] net@107[18] 
 +net@107[36] net@107[17] net@107[16] net@107[15] net@107[14] net@107[13] 
 +net@107[12] net@107[11] net@107[10] net@107[9] net@107[8] net@107[35] 
@@ -8147,7 +8314,7 @@ Xwire90@2 net@98 net@85 wire90-2080_4-layer_1-width_3
 
 *** CELL: stageGroupsM:southFifo{sch}
 .SUBCKT southFifo aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] 
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] cin 
++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] cin 
 +fin fout out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] 
 +out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] 
 +out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] 
@@ -8156,16 +8323,16 @@ Xwire90@2 net@98 net@85 wire90-2080_4-layer_1-width_3
 +sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] 
 +sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] 
 +sod[5] sor[1] succ[tap]
-XtapPropS@1 net@43[41] net@43[40] net@43[39] net@43[38] net@43[37] net@43[50] 
-+net@43[49] net@43[48] net@43[47] net@43[46] net@43[45] net@43[44] net@43[43] 
-+net@43[42] net@43[51] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] 
-+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] cin 
-+fin fout net@43[27] net@43[26] net@43[25] net@43[24] net@43[23] net@43[22] 
-+net@43[21] net@43[20] net@43[19] net@43[18] net@43[36] net@43[17] net@43[16] 
-+net@43[15] net@43[14] net@43[13] net@43[12] net@43[11] net@43[10] net@43[9] 
-+net@43[8] net@43[35] net@43[7] net@43[6] net@43[5] net@43[4] net@43[3] 
-+net@43[2] net@43[1] net@43[0] net@43[34] net@43[33] net@43[32] net@43[31] 
-+net@43[30] net@43[29] net@43[28] out[10] out[11] out[12] out[13] out[14] 
+XtapPropS@1 net@79[41] net@79[40] net@79[39] net@79[38] net@79[37] net@79[50] 
++net@79[49] net@79[48] net@79[47] net@79[46] net@79[45] net@79[44] net@79[43] 
++net@79[42] net@79[51] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] 
++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] cin 
++fin fout net@79[27] net@79[26] net@79[25] net@79[24] net@79[23] net@79[22] 
++net@79[21] net@79[20] net@79[19] net@79[18] net@79[36] net@79[17] net@79[16] 
++net@79[15] net@79[14] net@79[13] net@79[12] net@79[11] net@79[10] net@79[9] 
++net@79[8] net@79[35] net@79[7] net@79[6] net@79[5] net@79[4] net@79[3] 
++net@79[2] net@79[1] net@79[0] net@79[34] net@79[33] net@79[32] net@79[31] 
++net@79[30] net@79[29] net@79[28] out[10] out[11] out[12] out[13] out[14] 
 +out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] 
 +out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] 
 +out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] 
@@ -8174,34 +8341,34 @@ XtapPropS@1 net@43[41] net@43[40] net@43[39] net@43[38] net@43[37] net@43[50]
 +sid[9] net@64[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] 
 +soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] net@53 succ[tap] tapPropStop
 XupDown8w@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] 
-+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@50[41] 
-+net@50[40] net@50[39] net@50[38] net@50[37] net@50[50] net@50[49] net@50[48] 
-+net@50[47] net@50[46] net@50[45] net@50[44] net@50[43] net@50[42] net@50[51] 
-+net@50[41] net@50[40] net@50[39] net@50[38] net@50[37] net@50[50] net@50[49] 
-+net@50[48] net@50[47] net@50[46] net@50[45] net@50[44] net@50[43] net@50[42] 
-+net@50[51] net@43[41] net@43[40] net@43[39] net@43[38] net@43[37] net@43[50] 
-+net@43[49] net@43[48] net@43[47] net@43[46] net@43[45] net@43[44] net@43[43] 
-+net@43[42] net@43[51] out[10] out[11] out[12] out[13] out[14] out[15] out[16] 
++aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] net@77[41] 
++net@77[40] net@77[39] net@77[38] net@77[37] net@77[50] net@77[49] net@77[48] 
++net@77[47] net@77[46] net@77[45] net@77[44] net@77[43] net@77[42] net@77[51] 
++net@77[41] net@77[40] net@77[39] net@77[38] net@77[37] net@77[50] net@77[49] 
++net@77[48] net@77[47] net@77[46] net@77[45] net@77[44] net@77[43] net@77[42] 
++net@77[51] net@79[41] net@79[40] net@79[39] net@79[38] net@79[37] net@79[50] 
++net@79[49] net@79[48] net@79[47] net@79[46] net@79[45] net@79[44] net@79[43] 
++net@79[42] net@79[51] out[10] out[11] out[12] out[13] out[14] out[15] out[16] 
 +out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] 
 +out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] 
 +out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] 
-+out[8] out[9] net@50[27] net@50[26] net@50[25] net@50[24] net@50[23] 
-+net@50[22] net@50[21] net@50[20] net@50[19] net@50[18] net@50[36] net@50[17] 
-+net@50[16] net@50[15] net@50[14] net@50[13] net@50[12] net@50[11] net@50[10] 
-+net@50[9] net@50[8] net@50[35] net@50[7] net@50[6] net@50[5] net@50[4] 
-+net@50[3] net@50[2] net@50[1] net@50[0] net@50[34] net@50[33] net@50[32] 
-+net@50[31] net@50[30] net@50[29] net@50[28] net@50[27] net@50[26] net@50[25] 
-+net@50[24] net@50[23] net@50[22] net@50[21] net@50[20] net@50[19] net@50[18] 
-+net@50[36] net@50[17] net@50[16] net@50[15] net@50[14] net@50[13] net@50[12] 
-+net@50[11] net@50[10] net@50[9] net@50[8] net@50[35] net@50[7] net@50[6] 
-+net@50[5] net@50[4] net@50[3] net@50[2] net@50[1] net@50[0] net@50[34] 
-+net@50[33] net@50[32] net@50[31] net@50[30] net@50[29] net@50[28] net@43[27] 
-+net@43[26] net@43[25] net@43[24] net@43[23] net@43[22] net@43[21] net@43[20] 
-+net@43[19] net@43[18] net@43[36] net@43[17] net@43[16] net@43[15] net@43[14] 
-+net@43[13] net@43[12] net@43[11] net@43[10] net@43[9] net@43[8] net@43[35] 
-+net@43[7] net@43[6] net@43[5] net@43[4] net@43[3] net@43[2] net@43[1] 
-+net@43[0] net@43[34] net@43[33] net@43[32] net@43[31] net@43[30] net@43[29] 
-+net@43[28] net@53 net@58 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++out[8] out[9] net@77[27] net@77[26] net@77[25] net@77[24] net@77[23] 
++net@77[22] net@77[21] net@77[20] net@77[19] net@77[18] net@77[36] net@77[17] 
++net@77[16] net@77[15] net@77[14] net@77[13] net@77[12] net@77[11] net@77[10] 
++net@77[9] net@77[8] net@77[35] net@77[7] net@77[6] net@77[5] net@77[4] 
++net@77[3] net@77[2] net@77[1] net@77[0] net@77[34] net@77[33] net@77[32] 
++net@77[31] net@77[30] net@77[29] net@77[28] net@77[27] net@77[26] net@77[25] 
++net@77[24] net@77[23] net@77[22] net@77[21] net@77[20] net@77[19] net@77[18] 
++net@77[36] net@77[17] net@77[16] net@77[15] net@77[14] net@77[13] net@77[12] 
++net@77[11] net@77[10] net@77[9] net@77[8] net@77[35] net@77[7] net@77[6] 
++net@77[5] net@77[4] net@77[3] net@77[2] net@77[1] net@77[0] net@77[34] 
++net@77[33] net@77[32] net@77[31] net@77[30] net@77[29] net@77[28] net@79[27] 
++net@79[26] net@79[25] net@79[24] net@79[23] net@79[22] net@79[21] net@79[20] 
++net@79[19] net@79[18] net@79[36] net@79[17] net@79[16] net@79[15] net@79[14] 
++net@79[13] net@79[12] net@79[11] net@79[10] net@79[9] net@79[8] net@79[35] 
++net@79[7] net@79[6] net@79[5] net@79[4] net@79[3] net@79[2] net@79[1] 
++net@79[0] net@79[34] net@79[33] net@79[32] net@79[31] net@79[30] net@79[29] 
++net@79[28] net@53 net@58 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
 +sir[8] sir[9] net@64[8] net@58 net@61 upDown8weak
 .ENDS southFifo
 
@@ -8212,6 +8379,22 @@ XaStage@3 aStage@3_fire sir[9] pred s[1] net@0 aStage
 XaStage@4 aStage@4_fire sir[9] net@1 s[2] net@2 aStage
 XaStage@5 aStage@5_fire sir[9] net@3 s[3] succ aStage
 XscanEx3h@1 s[1] s[2] s[3] sir[9] sir[3] sir[2] sir[5] sir[1] sor[1] scanEx3h
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
+Xtc[6] tranCap
+Xtc[7] tranCap
+Xtc[8] tranCap
+Xtc[9] tranCap
+Xtc[10] tranCap
+Xtc[11] tranCap
+Xtc[12] tranCap
+Xtc[13] tranCap
+Xtc[14] tranCap
+Xtc[15] tranCap
+Xtc[16] tranCap
 Xwire90@0 net@0 net@1 wire90-291_8-layer_1-width_3
 Xwire90@1 net@2 net@3 wire90-291_8-layer_1-width_3
 .ENDS tokenFIFO
@@ -8230,9 +8413,10 @@ XnorthFif@1 dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3]
 +din[17] din[18] din[19] din[1] din[20] din[21] din[22] din[23] din[24] 
 +din[25] din[26] din[27] din[28] din[29] din[2] din[30] din[31] din[32] 
 +din[33] din[34] din[35] din[36] din[37] din[3] din[4] din[5] din[6] din[7] 
-+din[8] din[9] ddo[D] net@116[8] sic[2] sic[3] sic[4] sic[5] sic[8] sic[9] 
-+net@117[8] net@117[7] net@117[6] net@117[5] net@117[4] sid[6] sid[7] sid[8] 
-+sid[9] net@109[8] sir[2] sir[3] sir[4] sir[5] sir[8] sir[9] doo[D] northFifo
++din[8] din[9] dockSucc[D] net@116[8] sic[2] sic[3] sic[4] sic[5] sic[8] 
++sic[9] net@117[8] net@117[7] net@117[6] net@117[5] net@117[4] sid[6] sid[7] 
++sid[8] sid[9] net@109[8] sir[2] sir[3] sir[4] sir[5] sir[8] sir[9] 
++dockPred[D] northFifo
 XoutputDo@0 net@14 din[10] din[11] din[12] din[13] din[14] din[15] din[16] 
 +din[17] din[18] din[19] din[1] din[20] din[21] din[22] din[23] din[24] 
 +din[25] din[26] din[27] din[28] din[29] din[2] din[30] din[31] din[32] 
@@ -8244,11 +8428,12 @@ XoutputDo@0 net@14 din[10] din[11] din[12] din[13] din[14] din[15] din[16]
 +dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] dsD[33] dsD[34] dsD[35] dsD[36] 
 +dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] dsD[8] dsD[9] net@44 iout[10] 
 +iout[11] iout[12] iout[13] iout[14] iout[15] iout[16] iout[17] iout[18] 
-+iout[19] iout[1] iout[20] iout[21] iout[22] iout[23] iout[24] iout[25] 
-+iout[26] iout[27] iout[28] iout[29] iout[2] iout[30] iout[31] iout[32] 
-+iout[33] iout[34] iout[35] iout[36] iout[3] iout[4] iout[5] iout[6] iout[7] 
-+iout[8] iout[9] aout[T] doo[D] doo[T] ain[14] net@119[8] sir[2] sir[3] sir[4] 
-+sir[5] sir[3] sir[2] sir[8] sir[9] net@120[8] ddo[D] ddo[T] outputDock
++iout[20] iout[1] iout[21] iout[22] iout[23] iout[24] iout[25] iout[26] 
++iout[27] iout[28] iout[29] iout[30] iout[2] iout[31] iout[32] iout[33] 
++iout[34] iout[35] iout[36] iout[37] iout[3] iout[4] iout[5] iout[6] iout[7] 
++iout[8] iout[9] aout[T] dockPred[D] dockPred[T] ain[14] net@119[8] sir[2] 
++sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] sir[9] net@120[8] dockSucc[D] 
++dockSucc[T] outputDock
 XsouthFif@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] 
 +aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@44 fin 
 +net@38 iout[10] iout[11] iout[12] iout[13] iout[14] iout[15] iout[16] 
@@ -8260,6 +8445,6 @@ XsouthFif@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2]
 +sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] 
 +sir[9] net@116[8] net@117[8] net@117[7] net@117[6] net@117[5] net@117[4] 
 +net@119[8] net@14 southFifo
-XtokenFIF@1 ddo[T] net@120[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] 
-+sir[8] sir[9] net@109[8] doo[T] tokenFIFO
+XtokenFIF@1 dockSucc[T] net@120[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] 
++sir[8] sir[9] net@109[8] dockPred[T] tokenFIFO
 .END