From: adam <adam@megacz.com>
Date: Mon, 27 Oct 2008 14:12:54 +0000 (+0100)
Subject: clean up fpga directory
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=24c15b3f6e97926e037b797ef0eb6b22dd7bb408;p=fleet.git

clean up fpga directory
---

diff --git a/src/edu/berkeley/fleet/fpga/empty.vhd b/src/edu/berkeley/fleet/fpga/empty.vhd
deleted file mode 100644
index e69de29..0000000
diff --git a/src/edu/berkeley/fleet/fpga/fifo.inc b/src/edu/berkeley/fleet/fpga/fifo.inc
deleted file mode 100644
index 308fa79..0000000
--- a/src/edu/berkeley/fleet/fpga/fifo.inc
+++ /dev/null
@@ -1,167 +0,0 @@
-
-    input clk;
-    input rst;
-    wire fifostage_3_in_a;
-wire fifostage_3_in_r;
-wire   [47:0]fifostage_3_in;
-
-    wire fifostage_6_out_r;
-wire [47:0]fifostage_6_out;
-wire fifostage_6_out_a;
-
-    wire fifostage_0_in_a;
-wire fifostage_0_in_r;
-wire   [47:0]fifostage_0_in;
-
-    wire fifostage_1_out_r;
-wire [47:0]fifostage_1_out;
-wire fifostage_1_out_a;
-
-    wire fifostage_3_out_r;
-wire [47:0]fifostage_3_out;
-wire fifostage_3_out_a;
-
-    wire fifostage_4_out_r;
-wire [47:0]fifostage_4_out;
-wire fifostage_4_out_a;
-
-    wire fifostage_2_in_a;
-wire fifostage_2_in_r;
-wire   [47:0]fifostage_2_in;
-
-    wire fifostage_7_out_r;
-wire [47:0]fifostage_7_out;
-wire fifostage_7_out_a;
-
-    output out_r_;
-input out_a;
-output [47:0]out_;
-wire out_r;
-wire   [47:0]out;
-
-    wire fifostage_7_in_a;
-wire fifostage_7_in_r;
-wire   [47:0]fifostage_7_in;
-
-    wire fifostage_0_out_r;
-wire [47:0]fifostage_0_out;
-wire fifostage_0_out_a;
-
-    wire fifostage_1_in_a;
-wire fifostage_1_in_r;
-wire   [47:0]fifostage_1_in;
-
-    wire fifostage_2_out_r;
-wire [47:0]fifostage_2_out;
-wire fifostage_2_out_a;
-
-    wire fifostage_6_in_a;
-wire fifostage_6_in_r;
-wire   [47:0]fifostage_6_in;
-
-    wire fifostage_4_in_a;
-wire fifostage_4_in_r;
-wire   [47:0]fifostage_4_in;
-
-    input in_r;
-output in_a_;
-input [47:0]in;
-wire in_a;
-
-    wire fifostage_5_in_a;
-wire fifostage_5_in_r;
-wire   [47:0]fifostage_5_in;
-
-    wire fifostage_5_out_r;
-wire [47:0]fifostage_5_out;
-wire fifostage_5_out_a;
-
-    
-    assign fifostage_7_in_r = fifostage_6_out_r;
-assign fifostage_6_out_a = fifostage_7_in_a;
-assign fifostage_7_in   = fifostage_6_out;
-
-    
-    assign fifostage_2_in_r = fifostage_1_out_r;
-assign fifostage_1_out_a = fifostage_2_in_a;
-assign fifostage_2_in   = fifostage_1_out;
-
-    assign fifostage_4_in_r = fifostage_3_out_r;
-assign fifostage_3_out_a = fifostage_4_in_a;
-assign fifostage_4_in   = fifostage_3_out;
-
-    assign fifostage_5_in_r = fifostage_4_out_r;
-assign fifostage_4_out_a = fifostage_5_in_a;
-assign fifostage_5_in   = fifostage_4_out;
-
-    
-    assign out_r = fifostage_7_out_r;
-assign fifostage_7_out_a = out_a;
-assign out   = fifostage_7_out;
-
-    assign out_r_ = out_r;
-assign out_ = out;
-
-    
-    assign fifostage_1_in_r = fifostage_0_out_r;
-assign fifostage_0_out_a = fifostage_1_in_a;
-assign fifostage_1_in   = fifostage_0_out;
-
-    
-    assign fifostage_3_in_r = fifostage_2_out_r;
-assign fifostage_2_out_a = fifostage_3_in_a;
-assign fifostage_3_in   = fifostage_2_out;
-
-    
-    
-    assign in_a_ = in_a;
-assign fifostage_0_in_r = in_r;
-assign in_a = fifostage_0_in_a;
-assign fifostage_0_in   = in;
-
-    
-    assign fifostage_6_in_r = fifostage_5_out_r;
-assign fifostage_5_out_a = fifostage_6_in_a;
-assign fifostage_6_in   = fifostage_5_out;
-
-  fifostage fifostage_6(clk, rst 
-, fifostage_6_in_r, fifostage_6_in_a, fifostage_6_in
-, fifostage_6_out_r, fifostage_6_out_a, fifostage_6_out
-   );
-  fifostage fifostage_0(clk, rst 
-, fifostage_0_in_r, fifostage_0_in_a, fifostage_0_in
-, fifostage_0_out_r, fifostage_0_out_a, fifostage_0_out
-   );
-  fifostage fifostage_3(clk, rst 
-, fifostage_3_in_r, fifostage_3_in_a, fifostage_3_in
-, fifostage_3_out_r, fifostage_3_out_a, fifostage_3_out
-   );
-  fifostage fifostage_7(clk, rst 
-, fifostage_7_in_r, fifostage_7_in_a, fifostage_7_in
-, fifostage_7_out_r, fifostage_7_out_a, fifostage_7_out
-   );
-  fifostage fifostage_5(clk, rst 
-, fifostage_5_in_r, fifostage_5_in_a, fifostage_5_in
-, fifostage_5_out_r, fifostage_5_out_a, fifostage_5_out
-   );
-  fifostage fifostage_4(clk, rst 
-, fifostage_4_in_r, fifostage_4_in_a, fifostage_4_in
-, fifostage_4_out_r, fifostage_4_out_a, fifostage_4_out
-   );
-  fifostage fifostage_2(clk, rst 
-, fifostage_2_in_r, fifostage_2_in_a, fifostage_2_in
-, fifostage_2_out_r, fifostage_2_out_a, fifostage_2_out
-   );
-  fifostage fifostage_1(clk, rst 
-, fifostage_1_in_r, fifostage_1_in_a, fifostage_1_in
-, fifostage_1_out_r, fifostage_1_out_a, fifostage_1_out
-   );
-
-always @(posedge clk) begin
-  if (!rst) begin
-  end else begin
-    begin end
-    end
-  end
-
-endmodule
diff --git a/src/edu/berkeley/fleet/fpga/ramfifo8.v b/src/edu/berkeley/fleet/fpga/ramfifo8.v
deleted file mode 100644
index 4ef7919..0000000
--- a/src/edu/berkeley/fleet/fpga/ramfifo8.v
+++ /dev/null
@@ -1,5 +0,0 @@
-`define ADDR_BITS 3
-`define WIDTH 37
-`define MODULE_NAME ramfifo8
-`include "ramfifo.inc"
-
diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index 05a4f33..c9da7d3 100644
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -123,10 +123,6 @@ public class Verilog {
     public static class Module {
         public void dump(String prefix) throws IOException {
             PrintWriter pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/"+name+".v")));
-            /*
-            pw.println("`define DATAWIDTH                "+WIDTH_WORD);
-            pw.println("`define CODEBAG_SIZE_BITS        "+CBD_SIZE.valmaskwidth);
-            */
             dump(pw, true);
             pw.flush();
             for(InstantiatedModule m : instantiatedModules)