From: rkao <rkao>
Date: Wed, 10 Dec 2008 22:38:26 +0000 (+0000)
Subject: test 3014 passes
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=2764e032f61c384a2a9b0a536176bb0a9a547358;p=fleet.git

test 3014 passes
---

diff --git a/electric/registersL.jelib b/electric/registersL.jelib
index d1dc76b..387567c 100755
--- a/electric/registersL.jelib
+++ b/electric/registersL.jelib
@@ -8405,7 +8405,7 @@ Evdd_3||D5G2;|dataMux4@0|vdd_1|P
 X
 
 # Cell dataMuxAll;1{sch}
-CdataMuxAll;1{sch}||schematic|1216087490865|1228774830340|
+CdataMuxAll;1{sch}||schematic|1216087490865|1228949080096|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@2||-18|-6||||
 NOff-Page|conn@3||31|6||||
@@ -8448,10 +8448,10 @@ NWire_Pin|pin@67||-26|1||||
 NWire_Pin|pin@68||-26|6||||
 Ngeneric:Invisible-Pin|pin@69||-11.5|40.5|||||ART_message(D5G3;)Splus power drivers for selection
 Ngeneric:Invisible-Pin|pin@70||33.5|-6.5|||||ART_message(D5G3;)S[sign extension may,be inverted!]
-IorangeTSMC090nm:wire90;1{ic}|wire90@8||-10.5|1|||D0G4;|ATTR_L(D5G1;PUD)D953.8999999999996|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@8||-10.5|1|||D0G4;|ATTR_L(D5G1;PUD)S.954|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
 IorangeTSMC090nm:wire90;1{ic}|wire90@9||4.5|0|||D0G4;|ATTR_L(D5G1;PUD)D668.1999999999997|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
-IorangeTSMC090nm:wire90;1{ic}|wire90@10||31.5|24|||D0G4;|ATTR_L(D5G1;PUD)D4189.700000000002|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
-IorangeTSMC090nm:wire90;1{ic}|wire90@11||13.5|24|||D0G4;|ATTR_L(D5G1;PUD)D6941.500000000004|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@10||31.5|24|||D0G4;|ATTR_L(D5G1;PUD)S.4189|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
+IorangeTSMC090nm:wire90;1{ic}|wire90@11||13.5|24|||D0G4;|ATTR_L(D5G1;PUD)S.6941|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
 Awire|lit[15]|D5G2;||900|pin@34||-5|-1|pin@38||-5|-8
 Abus|lit[16:19]|D5G2;|-0.5|IJ900|pin@13||18.5|12|pin@14||18.5|6
 Awire|lit[20]|D5G2;||2700|pin@67||-26|1|pin@68||-26|6
diff --git a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
index a9910ec..faeefce 100644
--- a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
+++ b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
@@ -1448,10 +1448,9 @@ public class MarinaTest {
 
             // shift over 19 LSB's towards MSB
             for(int i=0; i<19; i++)
-                if (36-(i+19) >= 0)
-                    dreg.set(36-(i+19), dreg.get(36-i));
+                if (i+19 <= 36)  dreg.set(i+19, dreg.get(i));
             for(int i=0; i<19; i++)
-                dreg.set(36-i, immediate.get(i));
+                dreg.set(i, immediate.get(i));
 
             prln("sending data item");
             marina.instrIn.fill(SEND_DATA);
@@ -1459,18 +1458,10 @@ public class MarinaTest {
             List<BitVector> dataItems = marina.data.drainMany(3);
             fatal(dataItems.size()!=1, "expected exactly one data item, got " + dataItems.size());
 
-            BitVector bv = dataItems.get(0);
-            prln("got back " + MarinaUtils.extractData(bv).getState());
-
-            boolean mismatch = false;
-            String err = "";
-            for(int i=0; i<37; i++) {
-                if (bv.get(i) != ( (val & (1L << i)) != 0 )) {
-                    mismatch = true;
-                    err += ""+i+", ";
-                }
-            }
-            fatal(mismatch, "data read back did not match inserted literal; mismatch on bits " + err);
+            BitVector bv = MarinaUtils.extractData(dataItems.get(0));
+            fatal(!bv.equals(dreg), "data read back did not match inserted literal.\n" +
+            		"got:     "+bv.bitReverse().getState()+"\n"+
+            		"expected:"+dreg.bitReverse().getState());
         }
                 
     	adjustIndent(-2);
diff --git a/testCode/marina.spi b/testCode/marina.spi
index dec9da9..d9b435e 100644
--- a/testCode/marina.spi
+++ b/testCode/marina.spi
@@ -1,7 +1,7 @@
 *** SPICE deck for cell marina{sch} from library marinaL
 *** Created on Mon Nov 17, 2008 08:47:24
 *** Last revised on Mon Dec 08, 2008 14:05:37
-*** Written on Wed Dec 10, 2008 09:07:15 by Electric VLSI Design System, 
+*** Written on Wed Dec 10, 2008 14:45:43 by Electric VLSI Design System, 
 *version 8.08n
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
@@ -188,20 +188,20 @@ Xnms2_sy@0 out ina inb nms2_sy-X_20
 .ENDS nand2_sy-X_20
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-953_9-R_34_667m a b
-Ccap@0 gnd net@14 3.498f
-Ccap@1 gnd net@8 3.498f
-Ccap@2 gnd net@11 3.498f
-Rres@0 net@14 a 5.511
-Rres@1 net@11 net@14 11.023
-Rres@2 b net@8 5.511
-Rres@3 net@8 net@11 11.023
-.ENDS wire-C_0_011f-953_9-R_34_667m
+.SUBCKT wire-C_0_011f-0_954-R_34_667m a b
+Ccap@0 gnd net@14 0.0035f
+Ccap@1 gnd net@8 0.0035f
+Ccap@2 gnd net@11 0.0035f
+Rres@0 net@14 a 5.512m
+Rres@1 net@11 net@14 11.024m
+Rres@2 b net@8 5.512m
+Rres@3 net@8 net@11 11.024m
+.ENDS wire-C_0_011f-0_954-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-953_9-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-953_9-R_34_667m
-.ENDS wire90-953_9-layer_1-width_3
+.SUBCKT wire90-_954-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-0_954-R_34_667m
+.ENDS wire90-_954-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
 .SUBCKT wire-C_0_011f-668_2-R_34_667m a b
@@ -220,36 +220,36 @@ Xwire@0 a b wire-C_0_011f-668_2-R_34_667m
 .ENDS wire90-668_2-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-4189_7-R_34_667m a b
-Ccap@0 gnd net@14 15.362f
-Ccap@1 gnd net@8 15.362f
-Ccap@2 gnd net@11 15.362f
-Rres@0 net@14 a 24.207
-Rres@1 net@11 net@14 48.414
-Rres@2 b net@8 24.207
-Rres@3 net@8 net@11 48.414
-.ENDS wire-C_0_011f-4189_7-R_34_667m
+.SUBCKT wire-C_0_011f-0_419-R_34_667m a b
+Ccap@0 gnd net@14 0.00154f
+Ccap@1 gnd net@8 0.00154f
+Ccap@2 gnd net@11 0.00154f
+Rres@0 net@14 a 2.42m
+Rres@1 net@11 net@14 4.841m
+Rres@2 b net@8 2.42m
+Rres@3 net@8 net@11 4.841m
+.ENDS wire-C_0_011f-0_419-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-4189_7-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-4189_7-R_34_667m
-.ENDS wire90-4189_7-layer_1-width_3
+.SUBCKT wire90-_4189-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-0_419-R_34_667m
+.ENDS wire90-_4189-layer_1-width_3
 
 *** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-6941_5-R_34_667m a b
-Ccap@0 gnd net@14 25.452f
-Ccap@1 gnd net@8 25.452f
-Ccap@2 gnd net@11 25.452f
-Rres@0 net@14 a 40.106
-Rres@1 net@11 net@14 80.213
-Rres@2 b net@8 40.106
-Rres@3 net@8 net@11 80.213
-.ENDS wire-C_0_011f-6941_5-R_34_667m
+.SUBCKT wire-C_0_011f-0_694-R_34_667m a b
+Ccap@0 gnd net@14 0.00255f
+Ccap@1 gnd net@8 0.00255f
+Ccap@2 gnd net@11 0.00255f
+Rres@0 net@14 a 4.01m
+Rres@1 net@11 net@14 8.021m
+Rres@2 b net@8 4.01m
+Rres@3 net@8 net@11 8.021m
+.ENDS wire-C_0_011f-0_694-R_34_667m
 
 *** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-6941_5-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-6941_5-R_34_667m
-.ENDS wire90-6941_5-layer_1-width_3
+.SUBCKT wire90-_6941-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-0_694-R_34_667m
+.ENDS wire90-_6941-layer_1-width_3
 
 *** CELL: registersL:dataMuxAll{sch}
 .SUBCKT dataMuxAll lit[15] lit[16] lit[17] lit[18] lit[19] lit[20] out[15] 
@@ -264,10 +264,10 @@ Xinv@7 s[T] net@113 inv-X_80
 Xinv@8 net@120 out[15] inv-X_10
 Xinv@9 net@123 net@122 inv-X_40
 Xnand2_sy@0 net@115 lit[15] net@75 nand2_sy-X_20
-Xwire90@8 net@61 net@115 wire90-953_9-layer_1-width_3
+Xwire90@8 net@61 net@115 wire90-_954-layer_1-width_3
 Xwire90@9 net@75 net@123 wire90-668_2-layer_1-width_3
-Xwire90@10 net@113 s[F] wire90-4189_7-layer_1-width_3
-Xwire90@11 net@111 s[T] wire90-6941_5-layer_1-width_3
+Xwire90@10 net@113 s[F] wire90-_4189-layer_1-width_3
+Xwire90@11 net@111 s[T] wire90-_6941-layer_1-width_3
 .ENDS dataMuxAll
 
 *** CELL: orangeTSMC090nm:NMOSx{sch}