From: simonm <unknown>
Date: Mon, 11 May 1998 11:21:02 +0000 (+0000)
Subject: [project @ 1998-05-11 11:21:02 by simonm]
X-Git-Tag: Approx_2487_patches~714
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=2cb98454fa20db638b7707afa9fbbe93e623ba4c;p=ghc-hetmet.git

[project @ 1998-05-11 11:21:02 by simonm]
add isFloatTy and isDoubleTy
---

diff --git a/ghc/compiler/prelude/TysWiredIn.lhs b/ghc/compiler/prelude/TysWiredIn.lhs
index 4df3241..11e9232 100644
--- a/ghc/compiler/prelude/TysWiredIn.lhs
+++ b/ghc/compiler/prelude/TysWiredIn.lhs
@@ -22,10 +22,12 @@ module TysWiredIn (
 	consDataCon,
 	doubleDataCon,
 	doubleTy,
+	isDoubleTy,
 	doubleTyCon,
 	falseDataCon,
 	floatDataCon,
 	floatTy,
+	isFloatTy,
 	floatTyCon,
 	getStatePairingConInfo,
 
@@ -252,11 +254,24 @@ floatTy	= mkTyConTy floatTyCon
 
 floatTyCon = pcNonRecDataTyCon floatTyConKey pREL_BASE SLIT("Float") [] [floatDataCon]
 floatDataCon = pcDataCon floatDataConKey pREL_BASE SLIT("F#") [] [] [floatPrimTy] floatTyCon
+
+isFloatTy :: GenType flexi -> Bool
+isFloatTy ty
+  = case (splitAlgTyConApp_maybe ty) of
+	Just (tycon, [], _) -> uniqueOf tycon == floatTyConKey
+	_		    -> False
+
 \end{code}
 
 \begin{code}
 doubleTy = mkTyConTy doubleTyCon
 
+isDoubleTy :: GenType flexi -> Bool
+isDoubleTy ty
+  = case (splitAlgTyConApp_maybe ty) of
+	Just (tycon, [], _) -> uniqueOf tycon == doubleTyConKey
+	_		    -> False
+
 doubleTyCon = pcNonRecDataTyCon doubleTyConKey pREL_BASE SLIT("Double") [] [doubleDataCon]
 doubleDataCon = pcDataCon doubleDataConKey pREL_BASE SLIT("D#") [] [] [doublePrimTy] doubleTyCon
 \end{code}