From: adam <adam@megacz.com>
Date: Thu, 21 Aug 2008 10:20:16 +0000 (+0100)
Subject: improve getVerilog() code in Mask to use explicit comparisons rather than bitwise... 
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=3ddc98a96f4a56a0d727772eb54f201275f6e4dc;p=fleet.git

improve getVerilog() code in Mask to use explicit comparisons rather than bitwise operations
---

diff --git a/src/edu/berkeley/fleet/util/Mask.java b/src/edu/berkeley/fleet/util/Mask.java
index 267879d..b289cc6 100644
--- a/src/edu/berkeley/fleet/util/Mask.java
+++ b/src/edu/berkeley/fleet/util/Mask.java
@@ -16,7 +16,25 @@ public class Mask {
 
     public String verilog(String var) {
         // FIXME: throw an exception if this is called when no 1-bits or 0-bits were specified (ie only v-bits)
-        return "(("+var+" & "+allmax+"'b"+Long.toString(mask,2)+")=="+allmax+"'b"+Long.toString(val,2)+")";
+
+        StringBuffer sb = new StringBuffer();
+        sb.append("{");
+        boolean first = true;
+        int count = 0;
+        for(int i=63; i>=0; i--) {
+            if ((mask & (1L << i)) == 0) continue;
+            if (!first) sb.append(",");
+            first = false;
+            sb.append(var+"["+i+"]");
+            count++;
+        }
+        sb.append("}=="+count+"'b");
+        for(int i=63; i>=0; i--) {
+            if ((mask & (1L << i)) == 0) continue;
+            sb.append( (val & (1L << i))==0 ? "0" : "1" );
+        }
+        return "("+sb.toString()+")";
+        //return "(("+var+" & "+allmax+"'b"+Long.toString(mask,2)+")=="+allmax+"'b"+Long.toString(val,2)+")";
     }
     public String verilogVal(String var) {
         //return "(("+var+" & "+allmax+"'b"+Long.toString(valmask,2)+") >> "+valmaskmin+")";