From: adam <adam@megacz.com>
Date: Thu, 21 Aug 2008 10:33:52 +0000 (+0100)
Subject: clean up Fifo fpga code
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=57ba2ca8004573acee402fd75e9aca2a19806c2c;p=fleet.git

clean up Fifo fpga code
---

diff --git a/ships/Fifo.ship b/ships/Fifo.ship
index dde1bc0..8cbd38c 100644
--- a/ships/Fifo.ship
+++ b/ships/Fifo.ship
@@ -31,23 +31,17 @@ at least 16 words.
 
 == FPGA ==============================================================
 
-  wire in0_a;
-  wire out0_r;
-  wire [(`DATAWIDTH-1):0] out0_d;
-
-  fifo8 fifo8(clk, rst,
-              in_r,  in0_a, in_d,
-              out0_r, out_a, out0_d);
-
-  always @(posedge clk) begin
-    if (!rst) begin
-      `reset
-    end else begin
-    in_a <= in0_a;
-    out_r <= out0_r;
-    out_d <= out0_d;
-    end
-  end
+  input  [(`DATAWIDTH-1):0] in_d;
+  output [(`DATAWIDTH-1):0] out_d_;
+  input in_r;
+  output in_a_;
+  output out_r_;
+  input out_a;
+
+  fifo8x37 fifo8x37(clk, rst,
+                    in_r,  in_a_, in_d,
+                    out_r_, out_a, out_d_);
+
 
 == Test =================================================================
 // expected output