From: megacz Date: Thu, 26 Feb 2009 23:02:07 +0000 (-0800) Subject: added code to implement REVERSE_LATENCY using srl16 X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=5c8f4a2a8fbf62f3780ae1aa1035c0b51ad6d111;p=fleet.git added code to implement REVERSE_LATENCY using srl16 --- diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java index f0a25d4..3ac807f 100644 --- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java +++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java @@ -42,9 +42,8 @@ import static edu.berkeley.fleet.two.FleetTwoFleet.*; */ public class Verilog { - //public static final int FORWARD_LATENCY = 1; - public static final int FORWARD_LATENCY = 6; - public static final int REVERSE_LATENCY = 3; + public static final int FORWARD_LATENCY = 6; // must be >=1 + public static final int REVERSE_LATENCY = 4; // must be >=3 public static interface Value { public String getVerilog(); @@ -508,8 +507,25 @@ public class Verilog { public String getResetCode() { return driven==null ? name+"_a<=1;" : ""; } public String getAssignments() { StringBuffer sb = new StringBuffer(); - if (external) - sb.append("assign " + name +"_a_ = " + name + "_a;\n"); + if (external) { + int a = REVERSE_LATENCY - 3; + if (a<0 || a>16) { + throw new RuntimeException("cannot offer latency of " + REVERSE_LATENCY +"-3"); + } else if (a==0) { + sb.append("assign " + name +"_a_ = " + name + "_a;\n"); + } else { + a = a-1; // CLK-to-Q gives us one cycle of latency anyways + sb.append("SRL16E srl16_"+name+"_a\n"); + sb.append(" (.Q ("+name+"_a_),\n"); + sb.append(" .A0 ("+((a & (1<<0)) == 0 ? 0 : 1)+"),\n"); + sb.append(" .A1 ("+((a & (1<<1)) == 0 ? 0 : 1)+"),\n"); + sb.append(" .A2 ("+((a & (1<<2)) == 0 ? 0 : 1)+"),\n"); + sb.append(" .A3 ("+((a & (1<<3)) == 0 ? 0 : 1)+"),\n"); + sb.append(" .CE (1),\n"); + sb.append(" .CLK (clk),\n"); + sb.append(" .D ("+name+"_a));\n"); + } + } return sb.toString(); } public void connect(SinkPort driven) {