From: sewardj <unknown>
Date: Wed, 26 Jan 2000 13:38:02 +0000 (+0000)
Subject: [project @ 2000-01-26 13:38:02 by sewardj]
X-Git-Tag: Approximately_9120_patches~5187
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=62d7b4e1def45081ae70f80d2e0be1e4ad8611c9;p=ghc-hetmet.git

[project @ 2000-01-26 13:38:02 by sewardj]
spillReg, loadReg (x86): always spill fp registers using double-sized
loads/stores, even if they nominally contain only a float value --
otherwise the spill loses the extra guard bits.
---

diff --git a/ghc/compiler/nativeGen/RegAllocInfo.lhs b/ghc/compiler/nativeGen/RegAllocInfo.lhs
index 66f2ae0..ac015fe 100644
--- a/ghc/compiler/nativeGen/RegAllocInfo.lhs
+++ b/ghc/compiler/nativeGen/RegAllocInfo.lhs
@@ -779,7 +779,7 @@ spillReg dyn (MemoryReg i pk)
 
 	{-I386: spill above stack pointer leaving 2 words/spill-}
 	,IF_ARCH_i386 ( if pk == FloatRep || pk == DoubleRep
-                        then GST sz dyn (spRel (16 + 2 * i))
+                        then GST DF dyn (spRel (16 + 2 * i))
                         else MOV sz (OpReg dyn) (OpAddr (spRel (16 + 2 * i)))
 
 	{-SPARC: spill below frame pointer leaving 2 words/spill-}
@@ -796,7 +796,7 @@ loadReg (MemoryReg i pk) dyn
     mkUnitList (
 	 IF_ARCH_alpha( LD  sz dyn (spRel i)
 	,IF_ARCH_i386 ( if   pk == FloatRep || pk == DoubleRep
-                        then GLD sz (spRel (16 + 2 * i)) dyn
+                        then GLD DF (spRel (16 + 2 * i)) dyn
                         else MOV sz (OpAddr (spRel (16 + 2 * i))) (OpReg dyn)
 	,IF_ARCH_sparc( LD  sz (fpRel (-2 * i)) dyn
 	,)))