From: rkao <rkao>
Date: Wed, 19 Nov 2008 00:25:52 +0000 (+0000)
Subject: put do[M] into m1 stage per Ivan's instructions
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=7518fab5e99b7d5d3087215eb89836747c8e405a;p=fleet.git

put do[M] into m1 stage per Ivan's instructions
---

diff --git a/electric/fifoL.jelib b/electric/fifoL.jelib
index b990a81..a82c098 100755
--- a/electric/fifoL.jelib
+++ b/electric/fifoL.jelib
@@ -1518,7 +1518,7 @@ Esucc[T,D]||D4G2;|conn@14|a|I
 X
 
 # Cell m1stageD;1{ic}
-Cm1stageD;1{ic}||artwork|1224326401175|1226939778166|E
+Cm1stageD;1{ic}||artwork|1224326401175|1227057651188|E
 Ngeneric:Facet-Center|art@0||0|0||||AV
 Nschematic:Bus_Pin|pin@0||0|-9|-1|-1||
 Nschematic:Bus_Pin|pin@2||-4|-6|-1|-1||
@@ -1563,6 +1563,7 @@ Ngeneric:Invisible-Pin|pin@64||-2|5|||||ART_message(D5G1.5;)S2
 NPin|pin@65||0|-8|1|1||
 NPin|pin@66||0|-9|1|1||
 Ngeneric:Invisible-Pin|pin@76||2|0|1|1||
+Nschematic:Bus_Pin|pin@77||-2|-2|-1|-1||
 AThicker|net@8|||FS0|pin@33||0|-3|pin@14||-2|-3
 AThicker|net@9|||FS900|pin@17||3|-3|pin@18||3|-4
 AThicker|net@10|||FS0|pin@18||3|-4|pin@34||0|-4
@@ -1597,6 +1598,7 @@ AThicker|net@56|||FS900|pin@65||0|-8|pin@66||0|-9
 Aschematic:bus|net@66||-0.5|IJ0|pin@12||3|0|pin@76||2|0
 AThicker|net@69|||FS2700|pin@32||2|-3|pin@26||2|3
 Ecl[T,F],clS[T,F],rd[T,F],mc||D5G2;|pin@44||I
+Edo[M]||D5G2;|pin@77||U
 Efire[1]||D5G2;|pin@0||O
 Ein[1:36]||D5G2;|pin@2||I
 Emc||D5G2;|pin@4||O
@@ -1945,7 +1947,7 @@ Evdd_9||D5G2;|ins20Bx1@2|vdd_5|P
 X
 
 # Cell m1stageD;2{sch}
-Cm1stageD;2{sch}||schematic|1224182442214|1226940003568|
+Cm1stageD;2{sch}||schematic|1224182442214|1227057609202|
 IgaspL:aStageM1;1{ic}|aStageM1@2||-1|1|||D5G4;
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@1||-10|1|||Y|
@@ -1958,6 +1960,7 @@ NOff-Page|conn@8||-26|-6.5|||YR|
 NOff-Page|conn@9||-36|-16|||XRR|
 NOff-Page|conn@10||-29|-25|||XRRR|
 NOff-Page|conn@11||-36|-22|||XRR|
+NOff-Page|conn@12||-10|3||||
 IregistersL:ins20Bx36;1{ic}|ins20Bx3@0||-1|-26|Y||D5G4;
 IdriversJ:latchDriver60;1{ic}|latchDri@0||8|-11.5|RRR||D5G4;
 Im1stageD;1{ic}|m1stageD@0||32|14|||D5G4;
@@ -2006,12 +2009,14 @@ Awire|net@44|||1800|conn@1|y|-8|1|aStageM1@2|pred|-4|1
 Awire|net@59|||0|aStageM1@2|pred_1|-4|-1|pin@20||-7|-1
 Awire|net@61|||1800|aStageM1@2|succ|2|1|pin@23||5|1
 Awire|net@63|||1800|aStageM1@2|succ_1|2|-1|pin@25||5|-1
+Awire|net@64|||1800|conn@12|y|-8|3|aStageM1@2|do[M]|-3|3
 Awire|s[m1]|D5G2;||2700|pin@18||9|9|pin@12||9|13
 Abus|s[m2,m1]|D5G2;|-0.5|IJ900|scanKhx2@0|din[2]|-25|-19|pin@11||-25|-23
 Awire|succ|D5G2;||2700|pin@23||5|1|pin@24||5|5
 Awire|take[1]|D5G2;||900|latchDri@0|out|8|-15.5|pin@3||8|-20
 Awire|wait[M]|D5G2;||900|pin@25||5|-1|pin@26||5|-4
 Ecl[T,F],clS[T,F],rd[T,F],mc||D4G2;|conn@8|a|I
+Edo[M]||D5G2;X-3;|conn@12|a|U
 Efire[1]||D6G2;|conn@4|y|O
 Ein[1:36]||D4G2;|conn@5|a|I
 Emc||D6G2;|conn@10|y|O
@@ -2339,7 +2344,7 @@ Esucc||D6G2;|conn@2|y|O
 X
 
 # Cell m12stageD;1{ic}
-Cm12stageD;1{ic}||artwork|1224521888102|1226953547841|E
+Cm12stageD;1{ic}||artwork|1224521888102|1227057733959|E
 Ngeneric:Facet-Center|art@0||0|0||||AV
 Nschematic:Bus_Pin|pin@0||0|7|-1|-1||
 Nschematic:Bus_Pin|pin@1||-3|-9|-1|-1||
@@ -2379,6 +2384,7 @@ Nschematic:Bus_Pin|pin@46||2|-9|-1|-1|RRR|
 Ngeneric:Invisible-Pin|pin@47||2|-8|1|1|RRR|
 Ngeneric:Invisible-Pin|pin@49||-3|-8|1|1||
 Ngeneric:Invisible-Pin|pin@51||2|0|1|1||
+Nschematic:Bus_Pin|pin@52||-2|-2|-1|-1||
 AThicker|net@0|||FS0|pin@34||3|-4|pin@14||0|-4
 AThicker|net@1|||FS1800|pin@9||-2|3|pin@35||0|3
 AThicker|net@2|||FS2700|pin@35||0|3|pin@36||0|4
@@ -2409,6 +2415,7 @@ Aschematic:bus|net@43||-0.5|IJ2700|pin@1||-3|-9|pin@49||-3|-8
 AThicker|net@56|||FS900|pin@37||2|3|pin@12||2|-3
 Aschematic:bus|net@58||-0.5|IJ1800|pin@51||2|0|pin@7||3|0
 Ecl[T,F],clS[T,F],rd[T,F],mc||D5G2;|pin@0||I
+Edo[M]||D5G2;|pin@52||U
 Efire[m1,m2]||D5G2;|pin@1||O
 Ein[1:36]||D5G2;|pin@2||I
 Eout[1:36]||D5G2;|pin@3||O
@@ -3327,7 +3334,7 @@ Evdd_18||D5G2;|inv10x6@0|vdd|P
 X
 
 # Cell m12stageD;2{sch}
-Cm12stageD;2{sch}||schematic|1224326621858|1226939794285|
+Cm12stageD;2{sch}||schematic|1224326621858|1227057688528|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||-33|-6||||
 NOff-Page|conn@1||30.5|-6||||
@@ -3339,6 +3346,7 @@ NOff-Page|conn@8||18|12.5|||YR|
 NOff-Page|conn@9||7|5|||XRR|
 NOff-Page|conn@10||61|13|||R|
 NWire_Con|conn@12||53|-6||||
+NOff-Page|conn@13||9|-2||||
 IredFour:inv;1{ic}|inv[1:6]|D5G3;Y5;|53|0|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 Im1stageD;1{ic}|m1stageD@1||18|0|||D5G4;
 Im2stageD;1{ic}|m2stageD@2||-18|0|||D5G4;
@@ -3575,10 +3583,12 @@ Abus|net@144||-0.5|IJ1800|inv[1:6]|out|55.5|0|pin@102||60|0
 Abus|net@152||-0.5|IJ0|conn@12||53|-6|pin@106||49|-6
 Abus|net@154||-0.5|IJ1800|conn@12||53|-6|pin@108||57|-6
 Abus|net@157||-0.5|IJ1800|m1stageD@1|succ|21|0|conn@4|a|27.5|0
+Awire|net@158|||1800|conn@13|y|11|-2|m1stageD@1|do[M]|16|-2
 Abus|pout[1:12]|D5G2;|-0.5|IJ900|pin@108||57|-6|pin@109||57|-10
 Abus|pout[13:18]|D5G2;|-0.5|IJ900|pin@102||60|0|pin@105||60|-5
 Awire|s[m2]|D5G2;||2700|pin@17||-6|2|pin@13||-6|7
 Ecl[T,F],clS[T,F],rd[T,F],mc||D4G2;|conn@8|a|I
+Edo[M]||D5G2;X-3;|conn@13|a|U
 Efire[m1,m2]||D6G2;|conn@6|y|O
 Ein[1:36]||D4G2;|conn@0|a|I
 Eout[1:36]||D6G2;|conn@1|y|O
@@ -8646,7 +8656,7 @@ Evdd_63||D5G2;|topFour@0|vdd_27|P
 X
 
 # Cell ringFIFO;3{sch}
-CringFIFO;3{sch}||schematic|1224161083041|1226953997833|
+CringFIFO;3{sch}||schematic|1224161083041|1227057774609|
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@2||28|-13|||R|
 NOff-Page|conn@8||29|2|||Y|
@@ -8839,6 +8849,7 @@ NWire_Pin|pin@471||-38|-58||||
 NWire_Pin|pin@472||-38|-61||||
 NWire_Pin|pin@473||-50|-58||||
 NWire_Pin|pin@474||-50|-61||||
+NWire_Pin|pin@475||-6|-2||||
 IringFIFO;1{ic}|ringFIFO@0||48|38|||D5G4;
 Isplit10;1{ic}|split10@0||-36|0|||D5G4;
 IorangeTSMC090nm:wire90;1{ic}|wire90@39||16.5|18|||D0G4;|ATTR_L(D5G1;PUD)D3124.7000000000007|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)I3
@@ -8917,6 +8928,7 @@ IorangeTSMC090nm:wire90;1{ic}|wire90@182||-8|-58|||D0G4;|ATTR_L(D5G1;PUD)D605.39
 IorangeTSMC090nm:wire90;1{ic}|wire90@183||-20|-58|||D0G4;|ATTR_L(D5G1;PUD)D605.3999999999999|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)S4
 IorangeTSMC090nm:wire90;1{ic}|wire90@184||-32|-58|||D0G4;|ATTR_L(D5G1;PUD)D605.3999999999999|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)S4
 IorangeTSMC090nm:wire90;1{ic}|wire90@185||-44|-58|||D0G4;|ATTR_L(D5G1;PUD)D605.3999999999999|ATTR_LEWIRE(P)I1|ATTR_layer(D5G1;NPY-1;)I1|ATTR_width(D5G1;NPY-2;)S4
+Awire|do[M]|D5G2;X-5;||0|m12stage@0|do[M]|-2|-2|pin@475||-6|-2
 Abus|do[OD],wait[M]|D5G2;|-0.5|IJ900|pin@403||11|0|pin@404||11|-4
 Awire|fire[ODE]|D5G2;||900|odRQstag@0|fire[OD]|33|-9|pin@399||33|-14
 Abus|fire[m1,m2]|D5G2;|-0.5|IJ2700|pin@173||-3|-12|m12stage@0|fire[m1,m2]|-3|-9
diff --git a/electric/gaspL.jelib b/electric/gaspL.jelib
index 7fe28d8..86a1391 100755
--- a/electric/gaspL.jelib
+++ b/electric/gaspL.jelib
@@ -1,5 +1,5 @@
 # header information:
-HgaspL|8.08j
+HgaspL|8.08k
 
 # Views:
 Vicon|ic
@@ -467,7 +467,7 @@ Esucc||D6G2;|conn@34|y|O
 X
 
 # Cell aStageM1;1{ic}
-CaStageM1;1{ic}||artwork|1212797961666|1226927368466|EI
+CaStageM1;1{ic}||artwork|1212797961666|1227057576710|EI
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NThick-Circle|art@1||-2.5|-2|1|1||
 Nschematic:Bus_Pin|pin@1||0|-4|-1|-1||
@@ -498,6 +498,7 @@ Nschematic:Bus_Pin|pin@75||-3|-2|-1|-1||
 Nschematic:Bus_Pin|pin@76||3|-2|-1|-1||
 NPin|pin@77||2|-2|1|1||
 NPin|pin@78||3|-2|1|1||
+Nschematic:Bus_Pin|pin@79||-2|2|-1|-1||
 AThicker|net@24|||FS1800|pin@34||-1|3|pin@41||1|3
 AThicker|net@25|||FS1800|pin@12||-2|3|pin@34||-1|3
 AThicker|net@26|||FS2700|pin@34||-1|3|pin@35||-1|4
@@ -517,6 +518,7 @@ AThicker|net@66|||FS900|pin@62||2|0|pin@77||2|-2
 AThicker|net@67|||FS2700|pin@62||2|0|pin@13||2|3
 AThicker|net@68|||FS900|pin@77||2|-2|pin@26||2|-3
 AThicker|net@69|||FS1800|pin@77||2|-2|pin@78||3|-2
+Edo[M]||D5G2;|pin@79||U
 Efire||D5G2;|pin@1||O
 Emc||D5G2;|pin@4||I
 Epred||D5G2;|pin@3||I
@@ -645,7 +647,7 @@ Ewait[M]||D5G2;|pin@24||O
 X
 
 # Cell aStageM1;2{sch}
-CaStageM1;2{sch}||schematic|1211837167040|1226954376071|
+CaStageM1;2{sch}||schematic|1211837167040|1227057520143|
 IaStageM1;1{ic}|aStageM1@0||10.5|50.5|||D5G4;
 Ngeneric:Facet-Center|art@0||0|0||||AV
 NOff-Page|conn@0||-12|-4|||XR|
@@ -655,7 +657,8 @@ NOff-Page|conn@32||-8|32|||YRRR|
 NOff-Page|conn@34||23|27|||Y|
 NOff-Page|conn@38||3.5|42|||Y|
 NOff-Page|conn@39||36|41|||Y|
-IcentersJ:ctrAND3in40;1{ic}|ctrAND3i@0||9|14.5|XR||D5G4;
+NOff-Page|conn@40||36|6|||RR|
+IcentersJ:ctrAND4in40;1{ic}|ctrAND4i@0||9|14.5|XR||D5G4;
 IredFour:inv;1{ic}|inv@4||-23|0|XRRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S10|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFour:inv;1{ic}|inv@5||-23|15|XRRR||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S5|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
 IredFour:inv;1{ic}|inv@6||-3|21|X||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5G1.5;NPX1.5;Y2;)S100|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
@@ -674,12 +677,13 @@ NWire_Pin|pin@499||-8|27||||
 NWire_Pin|pin@500||1|27||||
 NWire_Pin|pin@502||30|3||||
 NWire_Pin|pin@504||30|41||||
-NWire_Pin|pin@505||11|3||||
+NWire_Pin|pin@505||10|3||||
 NWire_Pin|pin@506||19|37||||
 NWire_Pin|pin@508||19|40||||
 NWire_Pin|pin@509||1|37||||
 NWire_Pin|pin@510||6|4||||
 NWire_Pin|pin@511||8|6||||
+NWire_Pin|pin@512||12|6||||
 IdriversL:predDri20wMC;1{ic}|predDri2@1||-18|25|X||D5G4;
 IdriversL:sucDri20;1{ic}|sucDri20@1||12|27|||D5G4;
 IdriversL:sucDri20cond;1{ic}|sucDri20@2||22.5|41|Y||D5G4;
@@ -698,7 +702,7 @@ Awire|net@990|||2700|inv@4|in|-23|2.5|pin@478||-23|6
 Awire|net@992|||0|pin@479||18|27|sucDri20@1|succ|16|27
 Awire|net@993|||0|conn@34|a|21|27|pin@479||18|27
 Awire|net@994|||900|pin@479||18|27|pin@480||18|4
-Awire|net@1034|||2700|ctrAND3i@0|out|9|16.5|pin@497||9|21
+Awire|net@1034|||2700|ctrAND4i@0|out|9|16.5|pin@497||9|21
 Awire|net@1035|||0|pin@497||9|21|wire90@1|b|7.5|21
 Awire|net@1036|||0|wire90@1|a|2.5|21|inv@6|in|-0.5|21
 Awire|net@1037|||0|inv@6|out|-5.5|21|pin@498||-8|21
@@ -712,17 +716,20 @@ Awire|net@1055|||1800|conn@38|y|5.5|42|sucDri20@2|in_1|20.5|42
 Awire|net@1057|||0|pin@504||30|41|sucDri20@2|succ|24.5|41
 Awire|net@1060|||0|conn@39|a|34|41|pin@504||30|41
 Awire|net@1062|||2700|pin@502||30|3|pin@504||30|41
-Awire|net@1067|||2700|pin@505||11|3|ctrAND3i@0|inC|11|8.5
-Awire|net@1069|||1800|pin@505||11|3|pin@502||30|3
+Awire|net@1069|||1800|pin@505||10|3|pin@502||30|3
 Awire|net@1070|||1800|inv@7|out|8.5|37|wire90@2|a|10.5|37
 Awire|net@1071|||1800|wire90@2|b|15.5|37|pin@506||19|37
 Awire|net@1073|||1800|pin@508||19|40|sucDri20@2|in|20.5|40
 Awire|net@1076|||0|inv@7|in|3.5|37|pin@509||1|37
 Awire|net@1077|||2700|pin@506||19|37|pin@508||19|40
-Awire|net@1079|||2700|pin@510||6|4|ctrAND3i@0|inA|6|8.5
-Awire|net@1081|||2700|pin@511||8|6|ctrAND3i@0|inB|8|8.5
+Awire|net@1079|||2700|pin@510||6|4|ctrAND4i@0|inA|6|8.5
+Awire|net@1081|||2700|pin@511||8|6|ctrAND4i@0|inB|8|8.5
 Awire|net@1082|||1800|wire90@0|b|-4.5|6|pin@511||8|6
 Awire|net@1083|||0|pin@480||18|4|pin@510||6|4
+Awire|net@1087|||2700|pin@505||10|3|ctrAND4i@0|inC|10|8.5
+Awire|net@1088|||900|ctrAND4i@0|inD|12|8.5|pin@512||12|6
+Awire|net@1090|||1800|pin@512||12|6|conn@40|y|34|6
+Edo[M]||D5G2;X-3;|conn@40|a|U
 Efire||D6G2;|conn@32|y|O
 Emc||D4G2;|conn@0|a|I
 Epred||D4G2;|conn@25|a|I
diff --git a/testCode/marina.spi b/testCode/marina.spi
index ccf8146..1aec23d 100644
--- a/testCode/marina.spi
+++ b/testCode/marina.spi
@@ -1,7 +1,7 @@
 *** SPICE deck for cell marina{sch} from library marinaL
 *** Created on Mon Nov 17, 2008 08:47:24
 *** Last revised on Tue Nov 18, 2008 12:17:39
-*** Written on Tue Nov 18, 2008 16:34:24 by Electric VLSI Design System, 
+*** Written on Tue Nov 18, 2008 17:28:19 by Electric VLSI Design System, 
 *version 8.08k
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
@@ -2064,14 +2064,14 @@ Rres@3 net@8 net@11 5.891
 Xwire@0 a b wire-C_0_011f-509_8-R_34_667m
 .ENDS wire90-509_8-layer_1-width_3
 
-*** CELL: centersJ:ctrAND3in40{sch}
-.SUBCKT ctrAND3in40 inA inB inC out
-Xinv@0 inC net@88 inv-X_10
+*** CELL: centersJ:ctrAND4in40{sch}
+.SUBCKT ctrAND4in40 inA inB inC inD out
 Xnand2_sy@0 net@58 net@43 out nand2_sy-X_40
 Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_10
-Xwire90@0 net@88 net@43 wire90-521_7-layer_1-width_3
+Xnor2n_sy@0 inD inC net@64 nor2n_sy-X_10
+Xwire90@0 net@64 net@43 wire90-521_7-layer_1-width_3
 Xwire90@2 net@61 net@58 wire90-509_8-layer_1-width_3
-.ENDS ctrAND3in40
+.ENDS ctrAND4in40
 
 *** CELL: orangeTSMC090nm:PMOSx{sch}
 .SUBCKT PMOSx-X_6 d g s
@@ -2154,8 +2154,8 @@ Xwire@0 a b wire-C_0_011f-247_2-R_34_667m
 .ENDS wire90-247_2-layer_1-width_3
 
 *** CELL: gaspL:aStageM1{sch}
-.SUBCKT aStageM1 fire mc pred s[1] selLO[Dm] succ wait[M]
-XctrAND3i@0 succ net@1081 wait[M] net@1034 ctrAND3in40
+.SUBCKT aStageM1 do[M] fire mc pred s[1] selLO[Dm] succ wait[M]
+XctrAND4i@0 succ net@1081 wait[M] do[M] net@1034 ctrAND4in40
 Xinv@4 net@987 s[1] inv-X_10
 Xinv@5 pred net@987 inv-X_5
 Xinv@6 net@1036 fire inv-X_100
@@ -2227,7 +2227,7 @@ Xwire@0 a b wire-C_0_011f-447_1-R_34_667m
 .ENDS wire90-447_1-layer_1-width_3
 
 *** CELL: fifoL:m1stageD{sch}
-.SUBCKT m1stageD clS[F] clS[T] cl[F] cl[T] fire[1] in[10] in[11] in[12] 
+.SUBCKT m1stageD clS[F] clS[T] cl[F] cl[T] do[M] fire[1] in[10] in[11] in[12] 
 +in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] 
 +in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] 
 +in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc 
@@ -2236,7 +2236,7 @@ Xwire@0 a b wire-C_0_011f-447_1-R_34_667m
 +out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
 +out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred rd[F] 
 +rd[T] s[m2] sin sout succ wait[M]
-XaStageM1@2 fire[1] mc pred net@39 in[25] succ wait[M] aStageM1
+XaStageM1@2 do[M] fire[1] mc pred net@39 in[25] succ wait[M] aStageM1
 Xins20Bx3@0 net@6 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
 +in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] 
 +in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] 
@@ -2593,31 +2593,31 @@ Xwire@0 a b wire-C_0_011f-618-R_26m
 .ENDS wire90-618-layer_1-width_4
 
 *** CELL: fifoL:m12stageD{sch}
-.SUBCKT m12stageD clS[F] clS[T] cl[F] cl[T] fire[m1] fire[m2] in[10] in[11] 
-+in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] 
-+in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] 
-+in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] 
-+mc out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] 
-+out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] 
-+out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
-+out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pout[13] 
-+pout[14] pout[15] pout[16] pout[17] pout[18] pred rd[F] rd[T] sin sout succ 
-+wait[M]
+.SUBCKT m12stageD clS[F] clS[T] cl[F] cl[T] do[M] fire[m1] fire[m2] in[10] 
++in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] 
++in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] 
++in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] 
++in[9] mc out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] 
++out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] 
++out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] 
++out[34] out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] 
++pout[13] pout[14] pout[15] pout[16] pout[17] pout[18] pred rd[F] rd[T] sin 
++sout succ wait[M]
 Xinv[1] in[31] pout[13] inv-X_10
 Xinv[2] in[32] pout[14] inv-X_10
 Xinv[3] in[33] pout[15] inv-X_10
 Xinv[4] in[34] pout[16] inv-X_10
 Xinv[5] in[35] pout[17] inv-X_10
 Xinv[6] in[36] pout[18] inv-X_10
-Xm1stageD@1 clS[F] clS[T] cl[F] cl[T] fire[m1] m2[10] m2[11] m2[12] m2[13] 
-+m2[14] m2[15] m2[16] m2[17] m2[18] m2[19] m2[1] m2[20] m2[21] m2[22] m2[23] 
-+m2[24] m2[25] m2[26] m2[27] m2[28] m2[29] m2[2] m2[30] m2[31] m2[32] m2[33] 
-+m2[34] m2[35] m2[36] m2[3] m2[4] m2[5] m2[6] m2[7] m2[8] m2[9] mc out[10] 
-+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] 
-+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] 
-+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] 
-+out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] net@53 rd[F] rd[T] 
-+net@36 sin sout succ wait[M] m1stageD
+Xm1stageD@1 clS[F] clS[T] cl[F] cl[T] do[M] fire[m1] m2[10] m2[11] m2[12] 
++m2[13] m2[14] m2[15] m2[16] m2[17] m2[18] m2[19] m2[1] m2[20] m2[21] m2[22] 
++m2[23] m2[24] m2[25] m2[26] m2[27] m2[28] m2[29] m2[2] m2[30] m2[31] m2[32] 
++m2[33] m2[34] m2[35] m2[36] m2[3] m2[4] m2[5] m2[6] m2[7] m2[8] m2[9] mc 
++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] 
++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] 
++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] 
++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] net@53 rd[F] 
++rd[T] net@36 sin sout succ wait[M] m1stageD
 Xm2stageD@2 fire[m2] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] 
 +in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] 
 +in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] 
@@ -2666,15 +2666,6 @@ Xwire90@36 m2[35] wire90@36_b wire90-602_4-layer_1-width_4
 Xwire90@37 m2[36] wire90@37_b wire90-618-layer_1-width_4
 .ENDS m12stageD
 
-*** CELL: centersJ:ctrAND4in40{sch}
-.SUBCKT ctrAND4in40 inA inB inC inD out
-Xnand2_sy@0 net@58 net@43 out nand2_sy-X_40
-Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_10
-Xnor2n_sy@0 inD inC net@64 nor2n_sy-X_10
-Xwire90@0 net@64 net@43 wire90-521_7-layer_1-width_3
-Xwire90@2 net@61 net@58 wire90-509_8-layer_1-width_3
-.ENDS ctrAND4in40
-
 *** CELL: orangeTSMC090nm:wire{sch}
 .SUBCKT wire-C_0_011f-413_4-R_34_667m a b
 Ccap@0 gnd net@14 1.516f
@@ -7302,15 +7293,16 @@ Xwire@0 a b wire-C_0_011f-630-R_26m
 +od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] pout[10] pout[11] pout[12] 
 +pout[13] pout[14] pout[15] pout[16] pout[17] pout[18] pout[1] pout[2] pout[3] 
 +pout[4] pout[5] pout[6] pout[7] pout[8] pout[9] rd[F] rd[T] sin sout
-Xm12stage@0 clS[F] clS[T] cl[F] cl[T] fire[m1] fire[m2] pout[10] pout[11] 
-+pout[12] m3[13] m3[14] m3[15] m3[16] m3[17] m3[18] m3[19] pout[1] m3[20] 
-+m3[21] m3[22] m3[23] m3[24] m3[25] m3[26] m3[27] m3[28] m3[29] pout[2] m3[30] 
-+m3[31] m3[32] m3[33] m3[34] m3[35] m3[36] pout[3] pout[4] pout[5] pout[6] 
-+pout[7] pout[8] pout[9] mc m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] 
-+m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] 
-+m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] 
-+m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] pout[13] pout[14] pout[15] pout[16] 
-+pout[17] pout[18] net@233 rd[F] rd[T] net@291 sout do[OD] wait[M] m12stageD
+Xm12stage@0 clS[F] clS[T] cl[F] cl[T] do[M] fire[m1] fire[m2] pout[10] 
++pout[11] pout[12] m3[13] m3[14] m3[15] m3[16] m3[17] m3[18] m3[19] pout[1] 
++m3[20] m3[21] m3[22] m3[23] m3[24] m3[25] m3[26] m3[27] m3[28] m3[29] pout[2] 
++m3[30] m3[31] m3[32] m3[33] m3[34] m3[35] m3[36] pout[3] pout[4] pout[5] 
++pout[6] pout[7] pout[8] pout[9] mc m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] 
++m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] 
++m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] 
++m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] pout[13] pout[14] pout[15] 
++pout[16] pout[17] pout[18] net@233 rd[F] rd[T] net@291 sout do[OD] wait[M] 
++m12stageD
 XodRQstag@0 clS[F] clS[T] cl[F] cl[T] do[L] do[M] do[epi] net@236 fire[ODE] 
 +inE[10] inE[11] inE[12] inE[13] inE[14] inE[15] inE[16] inE[17] inE[18] 
 +inE[19] inE[1] inE[20] inE[21] inE[22] inE[23] inE[24] inE[25] inE[26]