From: adam <adam@megacz.com>
Date: Sun, 7 Sep 2008 03:10:19 +0000 (+0100)
Subject: add CarrySaveAdder ship
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=9946e39da7406e1cc32aa0f911189887874a4a32;p=fleet.git

add CarrySaveAdder ship
---

diff --git a/ships/CarrySaveAdder.ship b/ships/CarrySaveAdder.ship
new file mode 100644
index 0000000..d8b1a11
--- /dev/null
+++ b/ships/CarrySaveAdder.ship
@@ -0,0 +1,123 @@
+ship: CarrySaveAdder
+
+== Ports ===========================================================
+in:   in
+
+out:  out
+
+  
+== TeX ==============================================================
+
+The Carry-Save Adder computes the carry-save sum of three input
+values, provided sequentially at {\tt in}, and produces.
+
+
+== Fleeterpreter ====================================================
+
+public void service() {
+  if (box_in.dataReadyForShip() && box_out.readyForDataFromShip()) {
+  }
+}
+
+
+== FPGA ==============================================================
+
+  reg [(`DATAWIDTH-1):0] temp;
+  reg [(`DATAWIDTH):0]   out_d;
+  reg [1:0] state;
+  initial state = 0;
+  assign out_d_ = out_d;
+
+  wire [(`DATAWIDTH-1):0] majority;
+  wire [(`DATAWIDTH-1):0] xors;
+  genvar i;
+  generate
+    for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
+      assign majority[i] = (temp[i] & out_d[i]) | (in_d[i] & out_d[i]) | (temp[i] & in_d[i]);
+      assign xors[i]     = temp[i] ^ out_d[i] ^ in_d[i];
+    end
+  endgenerate
+
+  always @(posedge clk) begin
+    if (!rst) begin
+      `reset
+      state <= 0;
+    end else begin
+      if (!in_r        && in_a)       in_a        <= 0;
+      if (out_r        && out_a)      out_r       <= 0;
+      if (!out_r && !out_a && state==3) begin
+        out_d <= { 1'b0, temp };
+        out_r <= 1;
+        state <= state + 1;
+      end else if (in_r && !in_a && !out_r && !out_a) begin
+        if (state == 0) begin
+          out_d <= { 1'b0, in_d };
+        end else if (state == 1) begin
+          temp <= in_d;
+        end else if (state == 2) begin
+          out_d <= { majority[`DATAWIDTH-1:0], 1'b0 };
+          temp  <= xors;
+          out_r <= 1;
+        end
+        state <= state + 1;
+        in_a  <= 1;
+      end
+    end
+  end
+
+== Test ==============================================================
+
+// expected output
+#expect 0x3c4bc6
+#expect 0x1796d2
+#expect 0x24b4f4
+#expect 0x3c4bc6
+
+// ships required in order to run this code
+#ship debug        : Debug
+#ship csa          : CarrySaveAdder
+#ship alu          : Alu2
+#ship fifo         : Fifo
+
+fifo.in:
+   set word=1018217;  deliver;
+   set word=771820;   deliver;
+   set word=2161521;  deliver;
+fifo.out:
+   collect, send to csa.in; send to alu.in1;
+   collect, send to csa.in; send to alu.in2;
+   collect, send to csa.in; send to alu.in2;
+
+alu.in1: set ilc=4; recv, deliver;
+alu.in2: set ilc=4; recv, deliver;
+alu.inOp:
+   set word=Alu2.inOp[ADD];
+   set ilc=4; deliver;   
+alu.out:
+   collect, send to alu.in1;
+   collect; send to debug.in;
+   recv token;
+   collect; send to debug.in;
+
+csa.in:
+   set ilc=*;
+   recv, deliver;
+
+csa.out:
+   recv token;
+   collect, send to debug.in;
+   send to alu.in1;
+   collect, send to debug.in;
+   send to alu.in2;
+
+debug.in:
+   recv, deliver;
+   send token to csa.out;
+   set ilc=2;
+   recv, deliver;
+   send token to alu.out;
+   recv, deliver;
+
+
+== Contributors =========================================================
+Adam Megacz <megacz@cs.berkeley.edu>