From: megacz <adam@megacz.com>
Date: Sun, 1 Mar 2009 16:18:43 +0000 (-0800)
Subject: more predictable instance naming in Verilog.java
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=ba501e57029a321255a75f8ae0dcb0d0a487b4b6;p=fleet.git

more predictable instance naming in Verilog.java
---

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index 3ac807f..04985ff 100644
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -628,7 +628,17 @@ public class Verilog {
             public InstantiatedModule(Module thisModule, Module module) {
                 this.thisModule = thisModule;
                 this.module = module;
-                this.id = thisModule.id++;
+                // CRUDE
+                int id = 0;
+                OUTER: while(true) {
+                    for (InstantiatedModule im : thisModule.instantiatedModules)
+                        if (im.getName().equals(module.getName()+"_"+id)) {
+                            id++;
+                            continue OUTER;
+                        }
+                    break;
+                }
+                this.id = id;
                 thisModule.instantiatedModules.add(this);
                 for(String s : module.portorder)
                     getPort(s);