From: Adam Megacz Date: Tue, 10 Mar 2009 18:54:25 +0000 (+0000) Subject: update marina.spi X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=ce8ffd6293594cd3a94fedd0a90632e68a157c88;p=fleet.git update marina.spi --- diff --git a/testCode/marina.spi b/testCode/marina.spi index d1da205..f69bc43 100644 --- a/testCode/marina.spi +++ b/testCode/marina.spi @@ -1,19 +1,35 @@ -*** SPICE deck for cell marina{sch} from library marinaL +*** SPICE deck for cell marina{sch} from library aMarinaM *** Created on Mon Nov 17, 2008 08:47:24 -*** Last revised on Mon Dec 08, 2008 14:05:37 -*** Written on Mon Dec 15, 2008 15:03:31 by Electric VLSI Design System, -*version 8.08n +*** Last revised on Thu Mar 05, 2009 14:50:36 +*** Written on Sat Mar 07, 2009 08:26:02 by Electric VLSI Design System, +*version 8.08k *** Layout tech: cmos90, foundry TSMC *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF .OPTIONS NOMOD NOPAGE * Model cards are described in this file: .include '../testCode/header.hsp' +*** CELL: wiresL:bitAssignments{sch} +.SUBCKT bitAssignments +.ENDS bitAssignments + *** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_10 d g s -MNMOSf@0 d g s gnd nch W='30*(1+ABN/sqrt(30*2))' L='2' -+DELVTO='AVT0N/sqrt(30*2)' -.ENDS NMOSx-X_10 +.SUBCKT NMOSx-X_30 d g s +MNMOSf@0 d g s gnd nch W='90*(1+ABN/sqrt(90*2))' L='2' ++DELVTO='AVT0N/sqrt(90*2)' +.ENDS NMOSx-X_30 + +*** CELL: orangeTSMC090nm:PMOSx{sch} +.SUBCKT PMOSx-X_30 d g s +MPMOSf@0 d g s vdd pch W='180*(1+ABP/sqrt(180*2))' L='2' ++DELVTO='AVT0P/sqrt(180*2)' +.ENDS PMOSx-X_30 + +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_30 in out +XNMOS@0 out in gnd NMOSx-X_30 +XPMOS@0 out in vdd PMOSx-X_30 +.ENDS inv-X_30 *** CELL: orangeTSMC090nm:PMOSx{sch} .SUBCKT PMOSx-X_10 d g s @@ -21,146 +37,115 @@ MPMOSf@0 d g s vdd pch W='60*(1+ABP/sqrt(60*2))' L='2' +DELVTO='AVT0P/sqrt(60*2)' .ENDS PMOSx-X_10 -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_10 in out -XNMOS@0 out in gnd NMOSx-X_10 -XPMOS@0 out in vdd PMOSx-X_10 -.ENDS inv-X_10 +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_10 d g s +MNMOSf@0 d g s gnd nch W='30*(1+ABN/sqrt(30*2))' L='2' ++DELVTO='AVT0N/sqrt(30*2)' +.ENDS NMOSx-X_10 -*** CELL: redFour:nms2{sch} +*** CELL: redFive:nms2{sch} .SUBCKT nms2-X_5 d g g2 XNMOS@0 d g2 net@0 NMOSx-X_10 XNMOS@1 net@0 g gnd NMOSx-X_10 .ENDS nms2-X_5 -*** CELL: redFour:pms2{sch} -.SUBCKT pms2-X_5 d g g2 -XPMOS@0 net@2 g vdd PMOSx-X_10 -XPMOS@1 d g2 net@2 PMOSx-X_10 -.ENDS pms2-X_5 - -*** CELL: redFour:triInv{sch} -.SUBCKT triInv-X_5 en enB in out -Xnms2@0 out in en nms2-X_5 -Xpms2@0 out in enB pms2-X_5 -.ENDS triInv-X_5 - -*** CELL: gatesK:mux5{sch} -.SUBCKT mux5 inA[1] inB[1] out[1] s[F] s[T] -XtriInv@0 s[T] s[F] inA[1] out[1] triInv-X_5 -XtriInv@1 s[F] s[T] inB[1] out[1] triInv-X_5 -.ENDS mux5 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-277_3-R_34_667m a b -Ccap@0 gnd net@14 1.017f -Ccap@1 gnd net@8 1.017f -Ccap@2 gnd net@11 1.017f -Rres@0 net@14 a 1.602 -Rres@1 net@11 net@14 3.204 -Rres@2 b net@8 1.602 -Rres@3 net@8 net@11 3.204 -.ENDS wire-C_0_011f-277_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-277_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-277_3-R_34_667m -.ENDS wire90-277_3-layer_1-width_3 +*** CELL: redFive:nms2_sy{sch} +.SUBCKT nms2_sy-X_10 d g g2 +Xnms2@0 d g g2 nms2-X_5 +Xnms2@1 d g2 g nms2-X_5 +.ENDS nms2_sy-X_10 -*** CELL: registersL:dataMux4{sch} -.SUBCKT dataMux4 lit[16] lit[17] lit[18] lit[19] out[16] out[17] out[18] -+out[19] s[F] s[T] sign -Xi[1] lit[16] x[1] inv-X_10 -Xi[2] lit[17] x[2] inv-X_10 -Xi[3] lit[18] x[3] inv-X_10 -Xi[4] lit[19] x[4] inv-X_10 -Xm[1] x[1] sign out[16] s[F] s[T] mux5 -Xm[2] x[2] sign out[17] s[F] s[T] mux5 -Xm[3] x[3] sign out[18] s[F] s[T] mux5 -Xm[4] x[4] sign out[19] s[F] s[T] mux5 -Xwire90@0 x[1] wire90@0_b wire90-277_3-layer_1-width_3 -Xwire90@1 x[2] wire90@1_b wire90-277_3-layer_1-width_3 -Xwire90@2 x[3] wire90@2_b wire90-277_3-layer_1-width_3 -Xwire90@3 x[4] wire90@3_b wire90-277_3-layer_1-width_3 -.ENDS dataMux4 +*** CELL: redFive:nand2_sy{sch} +.SUBCKT nand2_sy-X_10 ina inb out +XPMOS@0 out inb vdd PMOSx-X_10 +XPMOS@1 out ina vdd PMOSx-X_10 +Xnms2_sy@0 out ina inb nms2_sy-X_10 +.ENDS nand2_sy-X_10 *** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_80 d g s -MNMOSf@0 d g s gnd nch W='240*(1+ABN/sqrt(240*2))' L='2' -+DELVTO='AVT0N/sqrt(240*2)' -.ENDS NMOSx-X_80 +.SUBCKT NMOSx-X_2_5 d g s +MNMOSf@0 d g s gnd nch W='7.5*(1+ABN/sqrt(7.5*2))' L='2' ++DELVTO='AVT0N/sqrt(7.5*2)' +.ENDS NMOSx-X_2_5 *** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_80 d g s -MPMOSf@0 d g s vdd pch W='480*(1+ABP/sqrt(480*2))' L='2' -+DELVTO='AVT0P/sqrt(480*2)' -.ENDS PMOSx-X_80 - -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_80 in out -XNMOS@0 out in gnd NMOSx-X_80 -XPMOS@0 out in vdd PMOSx-X_80 -.ENDS inv-X_80 +.SUBCKT PMOSx-X_5 d g s +MPMOSf@0 d g s vdd pch W='30*(1+ABP/sqrt(30*2))' L='2' ++DELVTO='AVT0P/sqrt(30*2)' +.ENDS PMOSx-X_5 -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_30 d g s -MNMOSf@0 d g s gnd nch W='90*(1+ABN/sqrt(90*2))' L='2' -+DELVTO='AVT0N/sqrt(90*2)' -.ENDS NMOSx-X_30 +*** CELL: redFive:pms2{sch} +.SUBCKT pms2-X_2_5 d g g2 +XPMOS@0 net@2 g vdd PMOSx-X_5 +XPMOS@1 d g2 net@2 PMOSx-X_5 +.ENDS pms2-X_2_5 -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_30 d g s -MPMOSf@0 d g s vdd pch W='180*(1+ABP/sqrt(180*2))' L='2' -+DELVTO='AVT0P/sqrt(180*2)' -.ENDS PMOSx-X_30 +*** CELL: redFive:pms2_sy{sch} +.SUBCKT pms2_sy-X_5 d g g2 +Xpms2@0 d g g2 pms2-X_2_5 +Xpms2@1 d g2 g pms2-X_2_5 +.ENDS pms2_sy-X_5 -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_30 in out -XNMOS@0 out in gnd NMOSx-X_30 -XPMOS@0 out in vdd PMOSx-X_30 -.ENDS inv-X_30 +*** CELL: redFive:nor2HT_sy{sch} +.SUBCKT nor2HT_sy-X_5 ina inb out +XNMOS@0 out inb gnd NMOSx-X_2_5 +XNMOS@1 out ina gnd NMOSx-X_2_5 +Xpms2_sy@0 out ina inb pms2_sy-X_5 +.ENDS nor2HT_sy-X_5 -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_100 d g s -MNMOSf@0 d g s gnd nch W='300*(1+ABN/sqrt(300*2))' L='2' -+DELVTO='AVT0N/sqrt(300*2)' -.ENDS NMOSx-X_100 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-414-R_34_667m a b +Ccap@0 gnd net@14 1.518f +Ccap@1 gnd net@8 1.518f +Ccap@2 gnd net@11 1.518f +Rres@0 net@14 a 2.392 +Rres@1 net@11 net@14 4.784 +Rres@2 b net@8 2.392 +Rres@3 net@8 net@11 4.784 +.ENDS wire-C_0_011f-414-R_34_667m -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_100 d g s -MPMOSf@0 d g s vdd pch W='600*(1+ABP/sqrt(600*2))' L='2' -+DELVTO='AVT0P/sqrt(600*2)' -.ENDS PMOSx-X_100 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-414-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-414-R_34_667m +.ENDS wire90-414-layer_1-width_3 -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_100 in out -XNMOS@0 out in gnd NMOSx-X_100 -XPMOS@0 out in vdd PMOSx-X_100 -.ENDS inv-X_100 +*** CELL: centersJ:ctrAND3in30A{sch} +.SUBCKT ctrAND3in30A inA inB inC out outM +Xinv@1 outM out inv-X_30 +Xnand2_sy@0 net@15 inC outM nand2_sy-X_10 +Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5 +Xwire90@0 net@6 net@15 wire90-414-layer_1-width_3 +.ENDS ctrAND3in30A *** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_40 d g s -MNMOSf@0 d g s gnd nch W='120*(1+ABN/sqrt(120*2))' L='2' -+DELVTO='AVT0N/sqrt(120*2)' -.ENDS NMOSx-X_40 +.SUBCKT NMOSx-X_5 d g s +MNMOSf@0 d g s gnd nch W='15*(1+ABN/sqrt(15*2))' L='2' ++DELVTO='AVT0N/sqrt(15*2)' +.ENDS NMOSx-X_5 -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_40 d g s -MPMOSf@0 d g s vdd pch W='240*(1+ABP/sqrt(240*2))' L='2' -+DELVTO='AVT0P/sqrt(240*2)' -.ENDS PMOSx-X_40 +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_5 in out +XNMOS@0 out in gnd NMOSx-X_5 +XPMOS@0 out in vdd PMOSx-X_5 +.ENDS inv-X_5 -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_40 in out -XNMOS@0 out in gnd NMOSx-X_40 -XPMOS@0 out in vdd PMOSx-X_40 -.ENDS inv-X_40 +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_10 in out +XNMOS@0 out in gnd NMOSx-X_10 +XPMOS@0 out in vdd PMOSx-X_10 +.ENDS inv-X_10 -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_20 d g s -MPMOSf@0 d g s vdd pch W='120*(1+ABP/sqrt(120*2))' L='2' -+DELVTO='AVT0P/sqrt(120*2)' -.ENDS PMOSx-X_20 +*** CELL: redFive:nor2_sy{sch} +.SUBCKT nor2_sy-X_5 ina inb out +XNMOS@0 out inb gnd NMOSx-X_5 +XNMOS@1 out ina gnd NMOSx-X_5 +Xpms2_sy@0 out ina inb pms2_sy-X_5 +.ENDS nor2_sy-X_5 + +*** CELL: redFive:nor2n_sy{sch} +.SUBCKT nor2n_sy-X_5 ina inb out +Xnor2@0 ina inb out nor2_sy-X_5 +.ENDS nor2n_sy-X_5 *** CELL: orangeTSMC090nm:NMOSx{sch} .SUBCKT NMOSx-X_20 d g s @@ -168,113 +153,11 @@ MNMOSf@0 d g s gnd nch W='60*(1+ABN/sqrt(60*2))' L='2' +DELVTO='AVT0N/sqrt(60*2)' .ENDS NMOSx-X_20 -*** CELL: redFour:nms2{sch} -.SUBCKT nms2-X_10 d g g2 -XNMOS@0 d g2 net@0 NMOSx-X_20 -XNMOS@1 net@0 g gnd NMOSx-X_20 -.ENDS nms2-X_10 - -*** CELL: redFour:nms2_sy{sch} -.SUBCKT nms2_sy-X_20 d g g2 -Xnms2@0 d g g2 nms2-X_10 -Xnms2@1 d g2 g nms2-X_10 -.ENDS nms2_sy-X_20 - -*** CELL: redFour:nand2_sy{sch} -.SUBCKT nand2_sy-X_20 ina inb out -XPMOS@0 out inb vdd PMOSx-X_20 -XPMOS@1 out ina vdd PMOSx-X_20 -Xnms2_sy@0 out ina inb nms2_sy-X_20 -.ENDS nand2_sy-X_20 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-0_954-R_34_667m a b -Ccap@0 gnd net@14 0.0035f -Ccap@1 gnd net@8 0.0035f -Ccap@2 gnd net@11 0.0035f -Rres@0 net@14 a 5.512m -Rres@1 net@11 net@14 11.024m -Rres@2 b net@8 5.512m -Rres@3 net@8 net@11 11.024m -.ENDS wire-C_0_011f-0_954-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-_954-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-0_954-R_34_667m -.ENDS wire90-_954-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-668_2-R_34_667m a b -Ccap@0 gnd net@14 2.45f -Ccap@1 gnd net@8 2.45f -Ccap@2 gnd net@11 2.45f -Rres@0 net@14 a 3.861 -Rres@1 net@11 net@14 7.721 -Rres@2 b net@8 3.861 -Rres@3 net@8 net@11 7.721 -.ENDS wire-C_0_011f-668_2-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-668_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-668_2-R_34_667m -.ENDS wire90-668_2-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-0_419-R_34_667m a b -Ccap@0 gnd net@14 0.00154f -Ccap@1 gnd net@8 0.00154f -Ccap@2 gnd net@11 0.00154f -Rres@0 net@14 a 2.42m -Rres@1 net@11 net@14 4.841m -Rres@2 b net@8 2.42m -Rres@3 net@8 net@11 4.841m -.ENDS wire-C_0_011f-0_419-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-_4189-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-0_419-R_34_667m -.ENDS wire90-_4189-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-0_694-R_34_667m a b -Ccap@0 gnd net@14 0.00255f -Ccap@1 gnd net@8 0.00255f -Ccap@2 gnd net@11 0.00255f -Rres@0 net@14 a 4.01m -Rres@1 net@11 net@14 8.021m -Rres@2 b net@8 4.01m -Rres@3 net@8 net@11 8.021m -.ENDS wire-C_0_011f-0_694-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-_6941-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-0_694-R_34_667m -.ENDS wire90-_6941-layer_1-width_3 - -*** CELL: registersL:dataMuxAll{sch} -.SUBCKT dataMuxAll lit[15] lit[16] lit[17] lit[18] lit[19] lit[20] out[15] -+out[16] out[17] out[18] out[19] s[F] s[T] sign -XdataMux4@0 lit[16] lit[17] lit[18] lit[19] out[16] out[17] out[18] out[19] -+s[F] s[T] sign dataMux4 -Xinv@0 net@122 sign inv-X_80 -Xinv@2 lit[15] net@120 inv-X_10 -Xinv@5 lit[20] net@61 inv-X_30 -Xinv@6 net@115 net@111 inv-X_100 -Xinv@7 s[T] net@113 inv-X_80 -Xinv@8 net@120 out[15] inv-X_10 -Xinv@9 net@123 net@122 inv-X_40 -Xnand2_sy@0 net@115 lit[15] net@75 nand2_sy-X_20 -Xwire90@8 net@61 net@115 wire90-_954-layer_1-width_3 -Xwire90@9 net@75 net@123 wire90-668_2-layer_1-width_3 -Xwire90@10 net@113 s[F] wire90-_4189-layer_1-width_3 -Xwire90@11 net@111 s[T] wire90-_6941-layer_1-width_3 -.ENDS dataMuxAll - *** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_1_733 d g s -MNMOSf@0 d g s gnd nch W='5.199*(1+ABN/sqrt(5.199*2))' L='2' -+DELVTO='AVT0N/sqrt(5.199*2)' -.ENDS NMOSx-X_1_733 +.SUBCKT NMOSx-X_4 d g s +MNMOSf@0 d g s gnd nch W='12*(1+ABN/sqrt(12*2))' L='2' ++DELVTO='AVT0N/sqrt(12*2)' +.ENDS NMOSx-X_4 *** CELL: orangeTSMC090nm:PMOSx{sch} .SUBCKT PMOSx-X_4 d g s @@ -282,784 +165,89 @@ MPMOSf@0 d g s vdd pch W='24*(1+ABP/sqrt(24*2))' L='2' +DELVTO='AVT0P/sqrt(24*2)' .ENDS PMOSx-X_4 +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_4 in out +XNMOS@0 out in gnd NMOSx-X_4 +XPMOS@0 out in vdd PMOSx-X_4 +.ENDS inv-X_4 + *** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_1 d g s -MPMOSf@0 d g s vdd pch W='6*(1+ABP/sqrt(6*2))' L='2' -+DELVTO='AVT0P/sqrt(6*2)' -.ENDS PMOSx-X_1 +.SUBCKT PMOSx-X_3_999 d g s +MPMOSf@0 d g s vdd pch W='23.994*(1+ABP/sqrt(23.994*2))' L='2' ++DELVTO='AVT0P/sqrt(23.994*2)' +.ENDS PMOSx-X_3_999 -*** CELL: latchPartsK:latchKeep{sch} -.SUBCKT latchKeep out[B] out[s] -XNMOSx@0 out[B] out[s] gnd NMOSx-X_1_733 -XNMOSx@1 out[s] out[B] gnd NMOSx-X_1_733 -XPMOSx@0 out[B] out[s] vdd PMOSx-X_4 -XPMOSx@1 out[s] out[B] vdd PMOSx-X_1 -.ENDS latchKeep +*** CELL: redFive:pms3{sch} +.SUBCKT pms3-X_1_333 d g g2 g3 +XPMOS@0 d g3 net@2 PMOSx-X_3_999 +XPMOS@1 net@2 g2 net@5 PMOSx-X_3_999 +XPMOS@2 net@5 g vdd PMOSx-X_3_999 +.ENDS pms3-X_1_333 -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_3 d g s -MNMOSf@0 d g s gnd nch W='9*(1+ABN/sqrt(9*2))' L='2' DELVTO='AVT0N/sqrt(9*2)' -.ENDS NMOSx-X_3 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-106_7-R_34_667m a b +Ccap@0 gnd net@14 0.391f +Ccap@1 gnd net@8 0.391f +Ccap@2 gnd net@11 0.391f +Rres@0 net@14 a 0.616 +Rres@1 net@11 net@14 1.233 +Rres@2 b net@8 0.616 +Rres@3 net@8 net@11 1.233 +.ENDS wire-C_0_011f-106_7-R_34_667m -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_6 d g s -MNMOSf@0 d g s gnd nch W='18*(1+ABN/sqrt(18*2))' L='2' -+DELVTO='AVT0N/sqrt(18*2)' -.ENDS NMOSx-X_6 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-106_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-106_7-R_34_667m +.ENDS wire90-106_7-layer_1-width_3 + +*** CELL: driversL:predDri20wMC{sch} +.SUBCKT predDri20wMC in mc pred +XNMOSx@0 pred in gnd NMOSx-X_20 +XNMOSx@1 pred mc gnd NMOSx-X_4 +Xinv@0 pred net@145 inv-X_4 +Xpms3@0 pred net@177 in mc pms3-X_1_333 +Xwire90@0 net@177 net@145 wire90-106_7-layer_1-width_3 +.ENDS predDri20wMC *** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_5 d g s -MPMOSf@0 d g s vdd pch W='30*(1+ABP/sqrt(30*2))' L='2' -+DELVTO='AVT0P/sqrt(30*2)' -.ENDS PMOSx-X_5 - -*** CELL: redFour:invLT{sch} -.SUBCKT invLT-X_5 in out -XNMOS@0 out in gnd NMOSx-X_10 -XPMOS@0 out in vdd PMOSx-X_5 -.ENDS invLT-X_5 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-124_4-R_34_667m a b -Ccap@0 gnd net@14 0.456f -Ccap@1 gnd net@8 0.456f -Ccap@2 gnd net@11 0.456f -Rres@0 net@14 a 0.719 -Rres@1 net@11 net@14 1.438 -Rres@2 b net@8 0.719 -Rres@3 net@8 net@11 1.438 -.ENDS wire-C_0_011f-124_4-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-124_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-124_4-R_34_667m -.ENDS wire90-124_4-layer_1-width_3 - -*** CELL: latchPartsK:latchPointF{sch} -.SUBCKT latchPointF hcl in[1] x[F] x[T] -XPMOSx@0 in[1] hcl x[T] NMOSx-X_3 -XPMOSx@1 net@8 hcl x[F] NMOSx-X_6 -Xinv@0 in[1] net@105 invLT-X_5 -Xwire90@0 net@105 net@8 wire90-124_4-layer_1-width_3 -.ENDS latchPointF - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-145_9-R_34_667m a b -Ccap@0 gnd net@14 0.535f -Ccap@1 gnd net@8 0.535f -Ccap@2 gnd net@11 0.535f -Rres@0 net@14 a 0.843 -Rres@1 net@11 net@14 1.686 -Rres@2 b net@8 0.843 -Rres@3 net@8 net@11 1.686 -.ENDS wire-C_0_011f-145_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-145_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-145_9-R_34_667m -.ENDS wire90-145_9-layer_1-width_3 - -*** CELL: latchesK:raw2inLatchF{sch} -.SUBCKT raw2inLatchF hcl[A] hcl[B] inA[1] inB[1] out[F] -XlatchKee@0 out[F] net@63 latchKeep -XlatchPoi@0 hcl[A] inA[1] out[F] net@45 latchPointF -XlatchPoi@1 hcl[B] inB[1] out[F] net@45 latchPointF -Xwire90@0 net@45 net@63 wire90-145_9-layer_1-width_3 -.ENDS raw2inLatchF - -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_20 in out -XNMOS@0 out in gnd NMOSx-X_20 -XPMOS@0 out in vdd PMOSx-X_20 -.ENDS inv-X_20 - -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_60 d g s -MNMOSf@0 d g s gnd nch W='180*(1+ABN/sqrt(180*2))' L='2' -+DELVTO='AVT0N/sqrt(180*2)' -.ENDS NMOSx-X_60 - -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_60 d g s -MPMOSf@0 d g s vdd pch W='360*(1+ABP/sqrt(360*2))' L='2' -+DELVTO='AVT0P/sqrt(360*2)' -.ENDS PMOSx-X_60 - -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_60 in out -XNMOS@0 out in gnd NMOSx-X_60 -XPMOS@0 out in vdd PMOSx-X_60 -.ENDS inv-X_60 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-295_8-R_34_667m a b -Ccap@0 gnd net@14 1.085f -Ccap@1 gnd net@8 1.085f -Ccap@2 gnd net@11 1.085f -Rres@0 net@14 a 1.709 -Rres@1 net@11 net@14 3.418 -Rres@2 b net@8 1.709 -Rres@3 net@8 net@11 3.418 -.ENDS wire-C_0_011f-295_8-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-295_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-295_8-R_34_667m -.ENDS wire90-295_8-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-242_1-R_34_667m a b -Ccap@0 gnd net@14 0.888f -Ccap@1 gnd net@8 0.888f -Ccap@2 gnd net@11 0.888f -Rres@0 net@14 a 1.399 -Rres@1 net@11 net@14 2.798 -Rres@2 b net@8 1.399 -Rres@3 net@8 net@11 2.798 -.ENDS wire-C_0_011f-242_1-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-242_1-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-242_1-R_34_667m -.ENDS wire90-242_1-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-555_8-R_34_667m a b -Ccap@0 gnd net@14 2.038f -Ccap@1 gnd net@8 2.038f -Ccap@2 gnd net@11 2.038f -Rres@0 net@14 a 3.211 -Rres@1 net@11 net@14 6.423 -Rres@2 b net@8 3.211 -Rres@3 net@8 net@11 6.423 -.ENDS wire-C_0_011f-555_8-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-555_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-555_8-R_34_667m -.ENDS wire90-555_8-layer_1-width_3 - -*** CELL: latchesK:latch2in60C{sch} -.SUBCKT latch2in60C hcl[A] hcl[B] inA[1] inB[1] outS[1] -Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@14 raw2inLatchF -XinvLT@0 net@15 net@18 invLT-X_5 -XinvLT@1 net@16 net@19 inv-X_20 -XinvLT@2 net@17 outS[1] inv-X_60 -Xwire90@0 net@14 net@15 wire90-295_8-layer_1-width_3 -Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3 -Xwire90@2 net@19 net@17 wire90-555_8-layer_1-width_3 -.ENDS latch2in60C - -*** CELL: redFour:nms2{sch} -.SUBCKT nms2-X_20 d g g2 -XNMOS@0 d g2 net@0 NMOSx-X_40 -XNMOS@1 net@0 g gnd NMOSx-X_40 -.ENDS nms2-X_20 - -*** CELL: redFour:nand2{sch} -.SUBCKT nand2-X_20 ina inb out -XPMOS@0 out ina vdd PMOSx-X_20 -XPMOS@1 out inb vdd PMOSx-X_20 -Xnms2@0 out ina inb nms2-X_20 -.ENDS nand2-X_20 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-544_2-R_34_667m a b -Ccap@0 gnd net@14 1.995f -Ccap@1 gnd net@8 1.995f -Ccap@2 gnd net@11 1.995f -Rres@0 net@14 a 3.144 -Rres@1 net@11 net@14 6.289 -Rres@2 b net@8 3.144 -Rres@3 net@8 net@11 6.289 -.ENDS wire-C_0_011f-544_2-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-544_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-544_2-R_34_667m -.ENDS wire90-544_2-layer_1-width_3 - -*** CELL: driversJ:latchAndDriver60{sch} -.SUBCKT latchAndDriver60 inA inB out -Xinv@0 net@8 out inv-X_60 -Xnand2@0 inA inB net@26 nand2-X_20 -Xwire90@0 net@26 net@8 wire90-544_2-layer_1-width_3 -.ENDS latchAndDriver60 - -*** CELL: driversJ:latchDriver60{sch} -.SUBCKT latchDriver60 in out -Xinv@0 net@8 out inv-X_60 -Xinv@1 in net@16 inv-X_20 -Xwire90@0 net@16 net@8 wire90-544_2-layer_1-width_3 -.ENDS latchDriver60 - -*** CELL: registersL:dRegDrive{sch} -.SUBCKT dRegDrive dataCap dcl[L] dcl[M] fire[L] fire[M] inL[19] inM[19] -+inM[To] outS[19] outS[T] -Xhi2inLat@0 fire[M] dcl[L] net@104 outS[T] outS[T] latch2in60C -Xinv@0 inM[To] net@104 inv-X_10 -Xlatch2in@0 dcl[M] dcl[L] inM[19] inL[19] outS[19] latch2in60C -XlatchAnd@1 dataCap fire[M] dcl[M] latchAndDriver60 -XlatchDri@2 fire[L] dcl[L] latchDriver60 -.ENDS dRegDrive - -*** CELL: latchesK:latch2in20A{sch} -.SUBCKT latch2in20A hcl[A] hcl[B] inA[1] inB[1] out[1] -Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@36 raw2inLatchF -XinvLT@1 net@16 out[1] inv-X_20 -Xwire90@1 net@36 net@16 wire90-242_1-layer_1-width_3 -.ENDS latch2in20A - -*** CELL: redFour:pms2{sch} -.SUBCKT pms2-X_10 d g g2 -XPMOS@0 net@2 g vdd PMOSx-X_20 -XPMOS@1 d g2 net@2 PMOSx-X_20 -.ENDS pms2-X_10 - -*** CELL: redFour:nor2{sch} -.SUBCKT nor2-X_10 ina inb out -XNMOS@0 out ina gnd NMOSx-X_10 -XNMOS@1 out inb gnd NMOSx-X_10 -Xpms2@0 out ina inb pms2-X_10 -.ENDS nor2-X_10 - -*** CELL: redFour:nor2n{sch} -.SUBCKT nor2n-X_10 ina inb out -Xnor2@0 ina inb out nor2-X_10 -.ENDS nor2n-X_10 - -*** CELL: registersL:dRegSignal{sch} -.SUBCKT dRegSignal dataCap dcl[M] fire[M] flag[C] sigA sigS -Xinv@0 fire[M] net@132 inv-X_10 -Xlatch2in@2 dcl[M] net@116 sigS sigA flag[C] latch2in20A -Xnor2n@0 dataCap net@131 net@128 nor2n-X_10 -Xwire90@0 net@128 net@116 wire90-295_8-layer_1-width_3 -Xwire90@1 net@132 net@131 wire90-295_8-layer_1-width_3 -.ENDS dRegSignal - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-146_1-R_34_667m a b -Ccap@0 gnd net@14 0.536f -Ccap@1 gnd net@8 0.536f -Ccap@2 gnd net@11 0.536f -Rres@0 net@14 a 0.844 -Rres@1 net@11 net@14 1.688 -Rres@2 b net@8 0.844 -Rres@3 net@8 net@11 1.688 -.ENDS wire-C_0_011f-146_1-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-146_1-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-146_1-R_34_667m -.ENDS wire90-146_1-layer_1-width_3 - -*** CELL: latchesK:raw1inLatchF{sch} -.SUBCKT raw1inLatchF hcl in[1] out[F] -XlatchFlo@0 out[F] net@58 latchKeep -XlatchPoi@0 hcl in[1] out[F] net@45 latchPointF -Xwire90@0 net@45 net@58 wire90-146_1-layer_1-width_3 -.ENDS raw1inLatchF - -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_9_6 d g s -MNMOSf@0 d g s gnd nch W='28.8*(1+ABN/sqrt(28.8*2))' L='2' -+DELVTO='AVT0N/sqrt(28.8*2)' -.ENDS NMOSx-X_9_6 - -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_9_6 d g s -MPMOSf@0 d g s vdd pch W='57.6*(1+ABP/sqrt(57.6*2))' L='2' -+DELVTO='AVT0P/sqrt(57.6*2)' -.ENDS PMOSx-X_9_6 - -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_9_6 in out -XNMOS@0 out in gnd NMOSx-X_9_6 -XPMOS@0 out in vdd PMOSx-X_9_6 -.ENDS inv-X_9_6 - -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_4 d g s -MNMOSf@0 d g s gnd nch W='12*(1+ABN/sqrt(12*2))' L='2' -+DELVTO='AVT0N/sqrt(12*2)' -.ENDS NMOSx-X_4 - -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_4 in out -XNMOS@0 out in gnd NMOSx-X_4 -XPMOS@0 out in vdd PMOSx-X_4 -.ENDS inv-X_4 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-114_7-R_34_667m a b -Ccap@0 gnd net@14 0.421f -Ccap@1 gnd net@8 0.421f -Ccap@2 gnd net@11 0.421f -Rres@0 net@14 a 0.663 -Rres@1 net@11 net@14 1.325 -Rres@2 b net@8 0.663 -Rres@3 net@8 net@11 1.325 -.ENDS wire-C_0_011f-114_7-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-114_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-114_7-R_34_667m -.ENDS wire90-114_7-layer_1-width_3 - -*** CELL: latchesK:latch1in09.6Bi{sch} -.SUBCKT latch1in09_6Bi hcl in[1] out[1] -Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF -Xinv@0 net@23 out[1] inv-X_9_6 -XinvLT@0 net@18 net@25 inv-X_4 -Xwire90@0 net@19 net@18 wire90-277_3-layer_1-width_3 -Xwire90@1 net@25 net@23 wire90-114_7-layer_1-width_3 -.ENDS latch1in09_6Bi - -*** CELL: latchGroupsK:dataMux{sch} -.SUBCKT dataMux hcl inB[1] in[1] out[1] s[F] s[T] -Xlatch1in@1 hcl in[1] net@5 latch1in09_6Bi -Xmux5@0 net@6 inB[1] out[1] s[F] s[T] mux5 -Xwire90@0 net@5 net@6 wire90-277_3-layer_1-width_3 -.ENDS dataMux - -*** CELL: registersL:dataMux18{sch} -.SUBCKT dataMux18 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] -+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3] -+out[4] out[5] out[6] out[7] out[8] out[9] s[F] s[T] sign take -Xdm[1] net@42 sign in[1] out[1] s[F] s[T] dataMux -Xdm[2] net@42 sign in[2] out[2] s[F] s[T] dataMux -Xdm[3] net@42 sign in[3] out[3] s[F] s[T] dataMux -Xdm[4] net@42 sign in[4] out[4] s[F] s[T] dataMux -Xdm[5] net@42 sign in[5] out[5] s[F] s[T] dataMux -Xdm[6] net@42 sign in[6] out[6] s[F] s[T] dataMux -Xdm[7] net@42 sign in[7] out[7] s[F] s[T] dataMux -Xdm[8] net@42 sign in[8] out[8] s[F] s[T] dataMux -Xdm[9] net@42 sign in[9] out[9] s[F] s[T] dataMux -Xdm[10] net@42 sign in[10] out[10] s[F] s[T] dataMux -Xdm[11] net@42 sign in[11] out[11] s[F] s[T] dataMux -Xdm[12] net@42 sign in[12] out[12] s[F] s[T] dataMux -Xdm[13] net@42 sign in[13] out[13] s[F] s[T] dataMux -Xdm[14] net@42 sign in[14] out[14] s[F] s[T] dataMux -Xdm[15] net@42 sign in[15] out[15] s[F] s[T] dataMux -Xdm[16] net@42 sign in[16] out[16] s[F] s[T] dataMux -Xdm[17] net@42 sign in[17] out[17] s[F] s[T] dataMux -Xdm[18] net@42 sign in[18] out[18] s[F] s[T] dataMux -Xinv@0 take net@39 inv-X_30 -Xwire90@0 net@39 net@42 wire90-277_3-layer_1-width_3 -.ENDS dataMux18 - -*** CELL: registersL:theDregister{sch} -.SUBCKT theDregister fire[L] fire[M] flag[C] inA[10] inA[11] inA[12] inA[13] -+inA[14] inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] -+inA[22] inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] -+inA[30] inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] -+inA[5] inA[6] inA[7] inA[8] inA[9] inA[T] lit[10] lit[11] lit[12] lit[13] -+lit[14] lit[15] lit[16] lit[17] lit[18] lit[19] lit[1] lit[2] lit[3] lit[4] -+lit[5] lit[6] lit[7] lit[8] lit[9] od[17] outS[10] outS[11] outS[12] outS[13] -+outS[14] outS[15] outS[16] outS[17] outS[18] outS[19] outS[1] outS[20] -+outS[21] outS[22] outS[23] outS[24] outS[25] outS[26] outS[27] outS[28] -+outS[29] outS[2] outS[30] outS[31] outS[32] outS[33] outS[34] outS[35] -+outS[36] outS[37] outS[3] outS[4] outS[5] outS[6] outS[7] outS[8] outS[9] -+outS[T] s[F] s[T] sigA sigS sign -XdRegDriv@1 od[17] dcl[L] dcl[M] fire[L] fire[M] lit[19] inA[19] inA[T] -+outS[19] outS[T] dRegDrive -XdRegSign@0 od[17] net@6 fire[M] flag[C] sigA sigS dRegSignal -XdataMux1@0 outS[10] outS[11] outS[12] outS[13] outS[14] outS[15] outS[16] -+outS[17] outS[18] outS[1] outS[2] outS[3] outS[4] outS[5] outS[6] outS[7] -+outS[8] outS[9] inB[29] inB[30] inB[31] inB[32] inB[33] inB[34] inB[35] -+inB[36] inB[37] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25] inB[26] -+inB[27] inB[28] s[F] s[T] sign dcl[L] dataMux18 -Xlat[1] net@6 net@3 inA[1] lit[1] outS[1] latch2in60C -Xlat[2] net@6 net@3 inA[2] lit[2] outS[2] latch2in60C -Xlat[3] net@6 net@3 inA[3] lit[3] outS[3] latch2in60C -Xlat[4] net@6 net@3 inA[4] lit[4] outS[4] latch2in60C -Xlat[5] net@6 net@3 inA[5] lit[5] outS[5] latch2in60C -Xlat[6] net@6 net@3 inA[6] lit[6] outS[6] latch2in60C -Xlat[7] net@6 net@3 inA[7] lit[7] outS[7] latch2in60C -Xlat[8] net@6 net@3 inA[8] lit[8] outS[8] latch2in60C -Xlat[9] net@6 net@3 inA[9] lit[9] outS[9] latch2in60C -Xlat[10] net@6 net@3 inA[10] lit[10] outS[10] latch2in60C -Xlat[11] net@6 net@3 inA[11] lit[11] outS[11] latch2in60C -Xlat[12] net@6 net@3 inA[12] lit[12] outS[12] latch2in60C -Xlat[13] net@6 net@3 inA[13] lit[13] outS[13] latch2in60C -Xlat[14] net@6 net@3 inA[14] lit[14] outS[14] latch2in60C -Xlat[15] net@6 net@3 inA[15] lit[15] outS[15] latch2in60C -Xlat[16] net@6 net@3 inA[16] lit[16] outS[16] latch2in60C -Xlat[17] net@6 net@3 inA[17] lit[17] outS[17] latch2in60C -Xlat[18] net@6 net@3 inA[18] lit[18] outS[18] latch2in60C -Xlat[20] net@6 net@3 inA[20] inB[20] outS[20] latch2in60C -Xlat[21] net@6 net@3 inA[21] inB[21] outS[21] latch2in60C -Xlat[22] net@6 net@3 inA[22] inB[22] outS[22] latch2in60C -Xlat[23] net@6 net@3 inA[23] inB[23] outS[23] latch2in60C -Xlat[24] net@6 net@3 inA[24] inB[24] outS[24] latch2in60C -Xlat[25] net@6 net@3 inA[25] inB[25] outS[25] latch2in60C -Xlat[26] net@6 net@3 inA[26] inB[26] outS[26] latch2in60C -Xlat[27] net@6 net@3 inA[27] inB[27] outS[27] latch2in60C -Xlat[28] net@6 net@3 inA[28] inB[28] outS[28] latch2in60C -Xlat[29] net@6 net@3 inA[29] inB[29] outS[29] latch2in60C -Xlat[30] net@6 net@3 inA[30] inB[30] outS[30] latch2in60C -Xlat[31] net@6 net@3 inA[31] inB[31] outS[31] latch2in60C -Xlat[32] net@6 net@3 inA[32] inB[32] outS[32] latch2in60C -Xlat[33] net@6 net@3 inA[33] inB[33] outS[33] latch2in60C -Xlat[34] net@6 net@3 inA[34] inB[34] outS[34] latch2in60C -Xlat[35] net@6 net@3 inA[35] inB[35] outS[35] latch2in60C -Xlat[36] net@6 net@3 inA[36] inB[36] outS[36] latch2in60C -Xlat[37] net@6 net@3 inA[37] inB[37] outS[37] latch2in60C -Xwire90@1 dcl[M] net@6 wire90-668_2-layer_1-width_3 -Xwire90@2 dcl[L] net@3 wire90-668_2-layer_1-width_3 -.ENDS theDregister - -*** CELL: registersL:addr2in14{sch} -.SUBCKT addr2in14 ainA[10] ainA[11] ainA[12] ainA[13] ainA[14] ainA[1] -+ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7] ainA[8] ainA[9] ainB[10] -+ainB[11] ainB[12] ainB[13] ainB[14] ainB[1] ainB[2] ainB[3] ainB[4] ainB[5] -+ainB[6] ainB[7] ainB[8] ainB[9] aout[10] aout[11] aout[12] aout[13] aout[14] -+aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] -+dcl[A] dcl[B] -XhiL[1] dcl[A] dcl[B] ainA[1] ainB[1] aout[1] latch2in60C -XhiL[2] dcl[A] dcl[B] ainA[2] ainB[2] aout[2] latch2in60C -XhiL[3] dcl[A] dcl[B] ainA[3] ainB[3] aout[3] latch2in60C -XhiL[4] dcl[A] dcl[B] ainA[4] ainB[4] aout[4] latch2in60C -XhiL[5] dcl[A] dcl[B] ainA[5] ainB[5] aout[5] latch2in60C -XhiL[6] dcl[A] dcl[B] ainA[6] ainB[6] aout[6] latch2in60C -XhiL[7] dcl[A] dcl[B] ainA[7] ainB[7] aout[7] latch2in60C -XhiL[8] dcl[A] dcl[B] ainA[8] ainB[8] aout[8] latch2in60C -XhiL[9] dcl[A] dcl[B] ainA[9] ainB[9] aout[9] latch2in60C -XhiL[10] dcl[A] dcl[B] ainA[10] ainB[10] aout[10] latch2in60C -XhiL[11] dcl[A] dcl[B] ainA[11] ainB[11] aout[11] latch2in60C -XhiL[12] dcl[A] dcl[B] ainA[12] ainB[12] aout[12] latch2in60C -XhiL[13] dcl[A] dcl[B] ainA[13] ainB[13] aout[13] latch2in60C -XhiL[14] dcl[A] dcl[B] ainA[14] ainB[14] aout[14] latch2in60C -.ENDS addr2in14 - -*** CELL: redFour:nand2{sch} -.SUBCKT nand2-X_10 ina inb out -XPMOS@0 out ina vdd PMOSx-X_10 -XPMOS@1 out inb vdd PMOSx-X_10 -Xnms2@0 out ina inb nms2-X_10 -.ENDS nand2-X_10 - -*** CELL: driversJ:latchAndDriver30{sch} -.SUBCKT latchAndDriver30 inA inB out -Xinv@0 net@8 out inv-X_30 -Xnand2@0 inA inB net@26 nand2-X_10 -Xwire90@0 net@26 net@8 wire90-544_2-layer_1-width_3 -.ENDS latchAndDriver30 - -*** CELL: redFour:pms2_sy{sch} -.SUBCKT pms2_sy-X_10 d g g2 -Xpms2@0 d g g2 pms2-X_5 -Xpms2@1 d g2 g pms2-X_5 -.ENDS pms2_sy-X_10 - -*** CELL: redFour:nor2_sy{sch} -.SUBCKT nor2_sy-X_10 ina inb out -XNMOS@0 out inb gnd NMOSx-X_10 -XNMOS@1 out ina gnd NMOSx-X_10 -Xpms2_sy@0 out ina inb pms2_sy-X_10 -.ENDS nor2_sy-X_10 - -*** CELL: redFour:nor2n_sy{sch} -.SUBCKT nor2n_sy-X_10 ina inb out -Xnor2@0 ina inb out nor2_sy-X_10 -.ENDS nor2n_sy-X_10 - -*** CELL: registersL:thePathRegister{sch} -.SUBCKT thePathRegister aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] -+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] dataPred[10] -+dataPred[11] dataPred[1] dataPred[2] dataPred[3] dataPred[4] dataPred[5] -+dataPred[6] dataPred[7] dataPred[8] dataPred[9] fire[M] path[10] path[11] -+path[12] path[13] path[14] path[1] path[2] path[3] path[4] path[5] path[6] -+path[7] path[8] path[9] -Xaddr2in1@2 dataPred[10] dataPred[11] dataPred[11] dataPred[11] dataPred[11] -+dataPred[1] dataPred[2] dataPred[3] dataPred[4] dataPred[5] dataPred[6] -+dataPred[7] dataPred[8] dataPred[9] path[10] path[11] path[12] path[13] -+path[14] path[1] path[2] path[3] path[4] path[5] path[6] path[7] path[8] -+path[9] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] -+aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] take[A] take[B] addr2in14 -XlatchAnd@0 path[14] fire[M] net@17 latchAndDriver30 -XlatchAnd@1 net@12 fire[M] net@18 latchAndDriver30 -Xnor2n_sy@0 path[13] path[14] net@13 nor2n_sy-X_10 -Xwire90@0 net@13 net@12 wire90-544_2-layer_1-width_3 -Xwire90@1 net@17 take[B] wire90-544_2-layer_1-width_3 -Xwire90@2 net@18 take[A] wire90-544_2-layer_1-width_3 -.ENDS thePathRegister - -*** CELL: dockPartOD:dataAddrRegAll{sch} -.SUBCKT dataAddrRegAll ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] -+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] aout[10] aout[11] aout[12] -+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] -+aout[8] aout[9] fire[L] fire[M] flag[C] inA[10] inA[11] inA[12] inA[13] -+inA[14] inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] -+inA[22] inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] -+inA[30] inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] -+inA[5] inA[6] inA[7] inA[8] inA[9] inA[T] lit[19] lit[20] od[10] od[11] -+od[12] od[13] od[14] od[15] od[16] od[17] od[18] od[1] od[2] od[3] od[4] -+od[5] od[6] od[7] od[8] od[9] outS[10] outS[11] outS[12] outS[13] outS[14] -+outS[15] outS[16] outS[17] outS[18] outS[19] outS[1] outS[20] outS[21] -+outS[22] outS[23] outS[24] outS[25] outS[26] outS[27] outS[28] outS[29] -+outS[2] outS[30] outS[31] outS[32] outS[33] outS[34] outS[35] outS[36] -+outS[37] outS[3] outS[4] outS[5] outS[6] outS[7] outS[8] outS[9] outS[T] sigA -+sigS -XdataMuxA@0 od[15] od[16] od[17] od[18] lit[19] lit[20] bk[15] bk[16] bk[17] -+bk[18] bk[19] s[F] s[T] sign dataMuxAll -XtheDregi@0 fire[L] fire[M] flag[C] inA[10] inA[11] inA[12] inA[13] inA[14] -+inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] -+inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] -+inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] inA[5] -+inA[6] inA[7] inA[8] inA[9] inA[T] od[10] od[11] od[12] od[13] od[14] bk[15] -+bk[16] bk[17] bk[18] bk[19] od[1] od[2] od[3] od[4] od[5] od[6] od[7] od[8] -+od[9] od[17] outS[10] outS[11] outS[12] outS[13] outS[14] outS[15] outS[16] -+outS[17] outS[18] outS[19] outS[1] outS[20] outS[21] outS[22] outS[23] -+outS[24] outS[25] outS[26] outS[27] outS[28] outS[29] outS[2] outS[30] -+outS[31] outS[32] outS[33] outS[34] outS[35] outS[36] outS[37] outS[3] -+outS[4] outS[5] outS[6] outS[7] outS[8] outS[9] outS[T] s[F] s[T] sigA sigS -+sign theDregister -XthePathR@0 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] -+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] inA[36] inA[37] -+inA[27] inA[28] inA[29] inA[30] inA[31] inA[32] inA[33] inA[34] inA[35] -+fire[M] od[10] od[11] od[12] od[13] od[14] od[1] od[2] od[3] od[4] od[5] -+od[6] od[7] od[8] od[9] thePathRegister -.ENDS dataAddrRegAll - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-70-R_34_667m a b -Ccap@0 gnd net@14 0.257f -Ccap@1 gnd net@8 0.257f -Ccap@2 gnd net@11 0.257f -Rres@0 net@14 a 0.404 -Rres@1 net@11 net@14 0.809 -Rres@2 b net@8 0.404 -Rres@3 net@8 net@11 0.809 -.ENDS wire-C_0_011f-70-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-70-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-70-R_34_667m -.ENDS wire90-70-layer_1-width_3 - -*** CELL: scanJ:scanAmp{sch} -.SUBCKT scanAmp in[1] out[1] -Xinv@0 in[1] net@1 inv-X_10 -Xinv@1 net@2 out[1] inv-X_20 -Xwire90@0 net@1 net@2 wire90-70-layer_1-width_3 -.ENDS scanAmp - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-297_6-R_34_667m a b -Ccap@0 gnd net@14 1.091f -Ccap@1 gnd net@8 1.091f -Ccap@2 gnd net@11 1.091f -Rres@0 net@14 a 1.719 -Rres@1 net@11 net@14 3.439 -Rres@2 b net@8 1.719 -Rres@3 net@8 net@11 3.439 -.ENDS wire-C_0_011f-297_6-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-297_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-297_6-R_34_667m -.ENDS wire90-297_6-layer_1-width_3 - -*** CELL: scanK:scanFromDock{sch} -.SUBCKT scanFromDock clS[F] clS[T] cl[F] cl[T] mc rd[F] rd[T] si[1] si[2] -+si[3] si[4] si[5] si[6] si[7] si[8] si[9] sin so[1] so[2] so[3] so[5] so[9] -Xinv@0 cl[T] net@40 inv-X_10 -Xinv@9 clS[T] net@47 inv-X_10 -Xinv@10 rd[T] net@55 inv-X_10 -Xinv@13 net@65 so[9] inv-X_20 -Xinv@14 mc net@64 inv-X_10 -Xnor2n_sy@0 cl[F] net@39 so[2] nor2n_sy-X_10 -Xnor2n_sy@1 clS[F] net@46 so[3] nor2n_sy-X_10 -Xnor2n_sy@2 rd[F] net@54 so[5] nor2n_sy-X_10 -XscanAmp@0 sin so[1] scanAmp -Xwire90@3 net@40 net@39 wire90-297_6-layer_1-width_3 -Xwire90@4 net@47 net@46 wire90-297_6-layer_1-width_3 -Xwire90@5 net@55 net@54 wire90-297_6-layer_1-width_3 -Xwire90@7 net@64 net@65 wire90-70-layer_1-width_3 -.ENDS scanFromDock - -*** CELL: scanK:scanToDock{sch} -.SUBCKT scanToDock clS[F] clS[T] cl[F] cl[T] mc rd[F] rd[T] si[1] si[2] si[3] -+si[4] si[5] si[6] si[7] si[8] si[9] so[1] so[2] so[3] so[5] so[9] sout -Xinv@0 si[2] net@1 inv-X_10 -Xinv@1 net@2 cl[T] inv-X_20 -Xinv@2 cl[T] cl[F] inv-X_20 -Xinv@3 si[3] net@14 inv-X_10 -Xinv@4 net@16 clS[T] inv-X_20 -Xinv@5 clS[T] clS[F] inv-X_20 -Xinv@6 si[5] net@25 inv-X_10 -Xinv@7 net@27 rd[T] inv-X_20 -Xinv@8 rd[T] rd[F] inv-X_20 -Xinv@9 si[9] net@33 inv-X_10 -Xinv@10 net@34 mc inv-X_20 -XscanAmp@0 si[1] sout scanAmp -Xwire90@0 net@1 net@2 wire90-70-layer_1-width_3 -Xwire90@1 net@14 net@16 wire90-70-layer_1-width_3 -Xwire90@2 net@25 net@27 wire90-70-layer_1-width_3 -Xwire90@3 net@33 net@34 wire90-70-layer_1-width_3 -.ENDS scanToDock - -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_2_5 d g s -MNMOSf@0 d g s gnd nch W='7.5*(1+ABN/sqrt(7.5*2))' L='2' -+DELVTO='AVT0N/sqrt(7.5*2)' -.ENDS NMOSx-X_2_5 - -*** CELL: redFour:pms2{sch} -.SUBCKT pms2-X_2_5 d g g2 -XPMOS@0 net@2 g vdd PMOSx-X_5 -XPMOS@1 d g2 net@2 PMOSx-X_5 -.ENDS pms2-X_2_5 - -*** CELL: redFour:pms2_sy{sch} -.SUBCKT pms2_sy-X_5 d g g2 -Xpms2@0 d g g2 pms2-X_2_5 -Xpms2@1 d g2 g pms2-X_2_5 -.ENDS pms2_sy-X_5 - -*** CELL: redFour:nor2HT_sy{sch} -.SUBCKT nor2HT_sy-X_5 ina inb out -XNMOS@0 out inb gnd NMOSx-X_2_5 -XNMOS@1 out ina gnd NMOSx-X_2_5 -Xpms2_sy@0 out ina inb pms2_sy-X_5 -.ENDS nor2HT_sy-X_5 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-252_6-R_34_667m a b -Ccap@0 gnd net@14 0.926f -Ccap@1 gnd net@8 0.926f -Ccap@2 gnd net@11 0.926f -Rres@0 net@14 a 1.459 -Rres@1 net@11 net@14 2.919 -Rres@2 b net@8 1.459 -Rres@3 net@8 net@11 2.919 -.ENDS wire-C_0_011f-252_6-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-252_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-252_6-R_34_667m -.ENDS wire90-252_6-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-366_8-R_34_667m a b -Ccap@0 gnd net@14 1.345f -Ccap@1 gnd net@8 1.345f -Ccap@2 gnd net@11 1.345f -Rres@0 net@14 a 2.119 -Rres@1 net@11 net@14 4.239 -Rres@2 b net@8 2.119 -Rres@3 net@8 net@11 4.239 -.ENDS wire-C_0_011f-366_8-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-366_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-366_8-R_34_667m -.ENDS wire90-366_8-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-176_4-R_34_667m a b -Ccap@0 gnd net@14 0.647f -Ccap@1 gnd net@8 0.647f -Ccap@2 gnd net@11 0.647f -Rres@0 net@14 a 1.019 -Rres@1 net@11 net@14 2.038 -Rres@2 b net@8 1.019 -Rres@3 net@8 net@11 2.038 -.ENDS wire-C_0_011f-176_4-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-176_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-176_4-R_34_667m -.ENDS wire90-176_4-layer_1-width_3 - -*** CELL: centersJ:ctrAND3in30{sch} -.SUBCKT ctrAND3in30 inA inB inC out -Xinv@4 inC net@30 inv-X_4 -Xinv@5 net@9 out inv-X_30 -Xnand2@0 net@19 net@15 net@27 nand2-X_10 -Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5 -Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3 -Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3 -Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3 -.ENDS ctrAND3in30 - -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_5 d g s -MNMOSf@0 d g s gnd nch W='15*(1+ABN/sqrt(15*2))' L='2' -+DELVTO='AVT0N/sqrt(15*2)' -.ENDS NMOSx-X_5 - -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_5 in out -XNMOS@0 out in gnd NMOSx-X_5 -XPMOS@0 out in vdd PMOSx-X_5 -.ENDS inv-X_5 +.SUBCKT PMOSx-X_20 d g s +MPMOSf@0 d g s vdd pch W='120*(1+ABP/sqrt(120*2))' L='2' ++DELVTO='AVT0P/sqrt(120*2)' +.ENDS PMOSx-X_20 *** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_3_999 d g s -MPMOSf@0 d g s vdd pch W='23.994*(1+ABP/sqrt(23.994*2))' L='2' -+DELVTO='AVT0P/sqrt(23.994*2)' -.ENDS PMOSx-X_3_999 - -*** CELL: redFour:pms3{sch} -.SUBCKT pms3-X_1_333 d g g2 g3 -XPMOS@0 d g3 net@2 PMOSx-X_3_999 -XPMOS@1 net@2 g2 net@5 PMOSx-X_3_999 -XPMOS@2 net@5 g vdd PMOSx-X_3_999 -.ENDS pms3-X_1_333 +.SUBCKT PMOSx-X_6_667 d g s +MPMOSf@0 d g s vdd pch W='40.002*(1+ABP/sqrt(40.002*2))' L='2' ++DELVTO='AVT0P/sqrt(40.002*2)' +.ENDS PMOSx-X_6_667 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-243_6-R_34_667m a b -Ccap@0 gnd net@14 0.893f -Ccap@1 gnd net@8 0.893f -Ccap@2 gnd net@11 0.893f -Rres@0 net@14 a 1.407 -Rres@1 net@11 net@14 2.815 -Rres@2 b net@8 1.407 -Rres@3 net@8 net@11 2.815 -.ENDS wire-C_0_011f-243_6-R_34_667m +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_20_001 d g s +MNMOSf@0 d g s gnd nch W='60.003*(1+ABN/sqrt(60.003*2))' L='2' ++DELVTO='AVT0N/sqrt(60.003*2)' +.ENDS NMOSx-X_20_001 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-243_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-243_6-R_34_667m -.ENDS wire90-243_6-layer_1-width_3 +*** CELL: redFive:nms3{sch} +.SUBCKT nms3-X_6_667 d g g2 g3 +XNMOS@0 d g3 net@6 NMOSx-X_20_001 +XNMOS@1 net@7 g gnd NMOSx-X_20_001 +XNMOS@2 net@6 g2 net@7 NMOSx-X_20_001 +.ENDS nms3-X_6_667 -*** CELL: driversL:predDri20wMC{sch} -.SUBCKT predDri20wMC in mc pred -XNMOSx@0 pred in gnd NMOSx-X_20 -XNMOSx@1 pred mc gnd NMOSx-X_4 -Xinv@0 pred net@145 inv-X_4 -Xpms3@0 pred net@177 in mc pms3-X_1_333 -Xwire90@0 net@177 net@145 wire90-243_6-layer_1-width_3 -.ENDS predDri20wMC +*** CELL: redFive:nand3{sch} +.SUBCKT nand3-X_6_667 ina inb inc out +XPMOS@0 out inc vdd PMOSx-X_6_667 +XPMOS@1 out inb vdd PMOSx-X_6_667 +XPMOS@2 out ina vdd PMOSx-X_6_667 +Xnms3@0 out ina inb inc nms3-X_6_667 +.ENDS nand3-X_6_667 -*** CELL: redFour:nms2{sch} +*** CELL: redFive:nms2{sch} .SUBCKT nms2-X_2 d g g2 XNMOS@0 d g2 net@0 NMOSx-X_4 XNMOS@1 net@0 g gnd NMOSx-X_4 .ENDS nms2-X_2 -*** CELL: redFour:nms2{sch} -.SUBCKT nms2-X_2_5 d g g2 -XNMOS@0 d g2 net@0 NMOSx-X_5 -XNMOS@1 net@0 g gnd NMOSx-X_5 -.ENDS nms2-X_2_5 - -*** CELL: redFour:nms2_sy{sch} -.SUBCKT nms2_sy-X_5 d g g2 -Xnms2@0 d g g2 nms2-X_2_5 -Xnms2@1 d g2 g nms2-X_2_5 -.ENDS nms2_sy-X_5 - -*** CELL: redFour:nand2_sy{sch} -.SUBCKT nand2_sy-X_5 ina inb out -XPMOS@0 out inb vdd PMOSx-X_5 -XPMOS@1 out ina vdd PMOSx-X_5 -Xnms2_sy@0 out ina inb nms2_sy-X_5 -.ENDS nand2_sy-X_5 - *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-309-R_34_667m a b Ccap@0 gnd net@14 1.133f @@ -1092,125 +280,104 @@ Rres@3 net@8 net@11 1.328 Xwire@0 a b wire-C_0_011f-114_9-R_34_667m .ENDS wire90-114_9-layer_1-width_3 +*** CELL: driversL:suc3ANDdri20{sch} +.SUBCKT suc3ANDdri20 inA inB inC succ +XPMOSx@0 succ net@51 vdd PMOSx-X_20 +Xinv@0 succ net@71 inv-X_4 +Xnand3@0 inA inB inC net@67 nand3-X_6_667 +Xnms2@0 succ net@75 net@51 nms2-X_2 +Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3 +Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3 +.ENDS suc3ANDdri20 + +*** CELL: redFive:nand2{sch} +.SUBCKT nand2-X_5 ina inb out +XPMOS@0 out ina vdd PMOSx-X_5 +XPMOS@1 out inb vdd PMOSx-X_5 +Xnms2@0 out ina inb nms2-X_5 +.ENDS nand2-X_5 + *** CELL: driversL:sucANDdri20{sch} .SUBCKT sucANDdri20 inA inB succ XPMOSx@0 succ net@51 vdd PMOSx-X_20 Xinv@0 succ net@71 inv-X_4 +Xnand2@0 inA inB net@67 nand2-X_5 Xnms2@0 succ net@75 net@51 nms2-X_2 -Xnor2_sy@0 inA inB net@67 nand2_sy-X_5 Xwire90@0 net@67 net@51 wire90-309-layer_1-width_3 Xwire90@1 net@75 net@71 wire90-114_9-layer_1-width_3 .ENDS sucANDdri20 *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-372_8-R_34_667m a b -Ccap@0 gnd net@14 1.367f -Ccap@1 gnd net@8 1.367f -Ccap@2 gnd net@11 1.367f -Rres@0 net@14 a 2.154 -Rres@1 net@11 net@14 4.308 -Rres@2 b net@8 2.154 -Rres@3 net@8 net@11 4.308 -.ENDS wire-C_0_011f-372_8-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-372_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-372_8-R_34_667m -.ENDS wire90-372_8-layer_1-width_3 - -*** CELL: gaspL:anEpiStart{sch} -.SUBCKT anEpiStart fire mc pred s[1] succ tokenLO torp -XctrAND3i@0 net@986 succ torp fire ctrAND3in30 -Xinv@4 net@987 s[1] inv-X_10 -Xinv@5 pred net@987 inv-X_5 -Xinv@7 tokenLO net@1060 inv-X_10 -XpredDri2@0 fire mc pred predDri20wMC -XsucANDdr@0 tokenLO fire succ sucANDdri20 -XsucANDdr@1 net@1048 fire torp sucANDdri20 -Xwire90@0 net@987 net@986 wire90-372_8-layer_1-width_3 -Xwire90@2 net@1060 net@1048 wire90-372_8-layer_1-width_3 -.ENDS anEpiStart - -*** CELL: redFour:invLT{sch} -.SUBCKT invLT-X_10 in out -XNMOS@0 out in gnd NMOSx-X_20 -XPMOS@0 out in vdd PMOSx-X_10 -.ENDS invLT-X_10 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-282-R_34_667m a b -Ccap@0 gnd net@14 1.034f -Ccap@1 gnd net@8 1.034f -Ccap@2 gnd net@11 1.034f -Rres@0 net@14 a 1.629 -Rres@1 net@11 net@14 3.259 -Rres@2 b net@8 1.629 -Rres@3 net@8 net@11 3.259 -.ENDS wire-C_0_011f-282-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-282-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-282-R_34_667m -.ENDS wire90-282-layer_1-width_3 - -*** CELL: latchesK:latch1in10A{sch} -.SUBCKT latch1in10A hcl in[1] out[1] -Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF -XinvLT@0 net@18 out[1] invLT-X_10 -Xwire90@0 net@19 net@18 wire90-282-layer_1-width_3 -.ENDS latch1in10A - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-311_7-R_34_667m a b -Ccap@0 gnd net@14 1.143f -Ccap@1 gnd net@8 1.143f -Ccap@2 gnd net@11 1.143f -Rres@0 net@14 a 1.801 -Rres@1 net@11 net@14 3.602 -Rres@2 b net@8 1.801 -Rres@3 net@8 net@11 3.602 -.ENDS wire-C_0_011f-311_7-R_34_667m +Ccap@0 gnd net@14 1.367f +Ccap@1 gnd net@8 1.367f +Ccap@2 gnd net@11 1.367f +Rres@0 net@14 a 2.154 +Rres@1 net@11 net@14 4.308 +Rres@2 b net@8 2.154 +Rres@3 net@8 net@11 4.308 +.ENDS wire-C_0_011f-372_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-311_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-311_7-R_34_667m -.ENDS wire90-311_7-layer_1-width_3 +.SUBCKT wire90-372_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-372_8-R_34_667m +.ENDS wire90-372_8-layer_1-width_3 -*** CELL: latchesK:latch2in10Alo{sch} -.SUBCKT latch2in10Alo hcl[A] hcl[B] inA[1] inB[1] out[1] -Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] dataBar raw2inLatchF -XinvLT@0 net@15 out[1] invLT-X_10 -Xwire90@0 dataBar net@15 wire90-311_7-layer_1-width_3 -.ENDS latch2in10Alo +*** CELL: gaspM:gaspEpi{sch} +.SUBCKT gaspEpi epi[OTHER] epi[TAIL] epi[TORP] fire mc pred s[1] tailBit ++tokenLO +XctrAND3i@3 net@1068 epi[TORP] net@1082 fire net@1119 ctrAND3in30A +Xinv@5 pred net@987 inv-X_5 +XinvI@0 net@987 s[1] inv-X_10 +XinvI@1 tokenLO net@1146 inv-X_5 +XinvI@3 tailBit net@1147 inv-X_5 +Xnor2n_sy@0 epi[TAIL] epi[OTHER] net@1079 nor2n_sy-X_5 +XpredDri2@0 fire mc pred predDri20wMC +Xsuc3ANDd@0 tokenLO net@1148 fire epi[OTHER] suc3ANDdri20 +Xsuc3ANDd@1 tokenLO tailBit fire epi[TAIL] suc3ANDdri20 +XsucANDdr@1 net@1139 fire epi[TORP] sucANDdri20 +Xwire90@0 net@987 net@1068 wire90-372_8-layer_1-width_3 +Xwire90@3 net@1079 net@1082 wire90-372_8-layer_1-width_3 +Xwire90@4 net@1139 net@1146 wire90-372_8-layer_1-width_3 +Xwire90@6 net@1148 net@1147 wire90-372_8-layer_1-width_3 +.ENDS gaspEpi -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-218_4-R_34_667m a b -Ccap@0 gnd net@14 0.801f -Ccap@1 gnd net@8 0.801f -Ccap@2 gnd net@11 0.801f -Rres@0 net@14 a 1.262 -Rres@1 net@11 net@14 2.524 -Rres@2 b net@8 1.262 -Rres@3 net@8 net@11 2.524 -.ENDS wire-C_0_011f-218_4-R_34_667m +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_1_733 d g s +MNMOSf@0 d g s gnd nch W='5.199*(1+ABN/sqrt(5.199*2))' L='2' ++DELVTO='AVT0N/sqrt(5.199*2)' +.ENDS NMOSx-X_1_733 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-218_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-218_4-R_34_667m -.ENDS wire90-218_4-layer_1-width_3 +*** CELL: orangeTSMC090nm:PMOSx{sch} +.SUBCKT PMOSx-X_1 d g s +MPMOSf@0 d g s vdd pch W='6*(1+ABP/sqrt(6*2))' L='2' ++DELVTO='AVT0P/sqrt(6*2)' +.ENDS PMOSx-X_1 -*** CELL: scanJ:scanCellE{sch} -.SUBCKT scanCellE dIn[1] p1p p2p rd sin sout -Xlatch1in@0 p2p sin net@2 latch1in10A -Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo -Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3 -.ENDS scanCellE +*** CELL: latchPartsK:latchKeep{sch} +.SUBCKT latchKeep out[B] out[s] +XNMOSx@0 out[B] out[s] gnd NMOSx-X_1_733 +XNMOSx@1 out[s] out[B] gnd NMOSx-X_1_733 +XPMOSx@0 out[B] out[s] vdd PMOSx-X_4 +XPMOSx@1 out[s] out[B] vdd PMOSx-X_1 +.ENDS latchKeep -*** CELL: scanJ:scanEx1vertA{sch} -.SUBCKT scanEx1vertA dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sor[1] -XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanCellE -.ENDS scanEx1vertA +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_6 d g s +MNMOSf@0 d g s gnd nch W='18*(1+ABN/sqrt(18*2))' L='2' ++DELVTO='AVT0N/sqrt(18*2)' +.ENDS NMOSx-X_6 + +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_3 d g s +MNMOSf@0 d g s gnd nch W='9*(1+ABN/sqrt(9*2))' L='2' DELVTO='AVT0N/sqrt(9*2)' +.ENDS NMOSx-X_3 + +*** CELL: redFive:invLT{sch} +.SUBCKT invLT-X_5 in out +XNMOS@0 out in gnd NMOSx-X_10 +XPMOS@0 out in vdd PMOSx-X_5 +.ENDS invLT-X_5 *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-123_7-R_34_667m a b @@ -1259,6 +426,12 @@ XlatchPoi@0 hcl[A] inA[1] net@7 out[T] latchPointT Xwire90@0 net@7 net@29 wire90-180_9-layer_1-width_3 .ENDS raw1inLatchT +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_20 in out +XNMOS@0 out in gnd NMOSx-X_20 +XPMOS@0 out in vdd PMOSx-X_20 +.ENDS inv-X_20 + *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-250_9-R_34_667m a b Ccap@0 gnd net@14 0.92f @@ -1270,1118 +443,1492 @@ Rres@2 b net@8 1.45 Rres@3 net@8 net@11 2.899 .ENDS wire-C_0_011f-250_9-R_34_667m -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-250_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-250_9-R_34_667m -.ENDS wire90-250_9-layer_1-width_3 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-250_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-250_9-R_34_667m +.ENDS wire90-250_9-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-214_6-R_34_667m a b +Ccap@0 gnd net@14 0.787f +Ccap@1 gnd net@8 0.787f +Ccap@2 gnd net@11 0.787f +Rres@0 net@14 a 1.24 +Rres@1 net@11 net@14 2.48 +Rres@2 b net@8 1.24 +Rres@3 net@8 net@11 2.48 +.ENDS wire-C_0_011f-214_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-214_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-214_6-R_34_667m +.ENDS wire90-214_6-layer_1-width_3 + +*** CELL: latchesK:latch1in20B{sch} +.SUBCKT latch1in20B hcl in[1] out[1] +Xhi2inLat@0 hcl in[1] net@19 raw1inLatchT +Xinv@0 net@23 out[1] inv-X_20 +XinvLT@0 net@18 net@25 inv-X_5 +Xwire90@0 net@19 net@18 wire90-250_9-layer_1-width_3 +Xwire90@1 net@25 net@23 wire90-214_6-layer_1-width_3 +.ENDS latch1in20B + +*** CELL: registersM:ins1in20Bx18{sch} +.SUBCKT ins1in20Bx18 hcl in[10] in[11] in[12] in[13] in[14] in[15] in[16] ++in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] ++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] ++out[3] out[4] out[5] out[6] out[7] out[8] out[9] +Xlx[1] hcl in[1] out[1] latch1in20B +Xlx[2] hcl in[2] out[2] latch1in20B +Xlx[3] hcl in[3] out[3] latch1in20B +Xlx[4] hcl in[4] out[4] latch1in20B +Xlx[5] hcl in[5] out[5] latch1in20B +Xlx[6] hcl in[6] out[6] latch1in20B +Xlx[7] hcl in[7] out[7] latch1in20B +Xlx[8] hcl in[8] out[8] latch1in20B +Xlx[9] hcl in[9] out[9] latch1in20B +Xlx[10] hcl in[10] out[10] latch1in20B +Xlx[11] hcl in[11] out[11] latch1in20B +Xlx[12] hcl in[12] out[12] latch1in20B +Xlx[13] hcl in[13] out[13] latch1in20B +Xlx[14] hcl in[14] out[14] latch1in20B +Xlx[15] hcl in[15] out[15] latch1in20B +Xlx[16] hcl in[16] out[16] latch1in20B +Xlx[17] hcl in[17] out[17] latch1in20B +Xlx[18] hcl in[18] out[18] latch1in20B +.ENDS ins1in20Bx18 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-2550-R_34_667m a b +Ccap@0 gnd net@14 9.35f +Ccap@1 gnd net@8 9.35f +Ccap@2 gnd net@11 9.35f +Rres@0 net@14 a 14.733 +Rres@1 net@11 net@14 29.467 +Rres@2 b net@8 14.733 +Rres@3 net@8 net@11 29.467 +.ENDS wire-C_0_011f-2550-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-2550-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-2550-R_34_667m +.ENDS wire90-2550-layer_1-width_3 + +*** CELL: registersM:ins1in20Bx36{sch} +.SUBCKT ins1in20Bx36 hcl[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] ++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] ++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] ++in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] ++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] ++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] ++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] ++out[6] out[7] out[8] out[9] +Xins1in20@0 net@13 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] ++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3] ++out[4] out[5] out[6] out[7] out[8] out[9] ins1in20Bx18 +Xins1in20@1 net@11 in[28] in[29] in[30] in[31] in[32] in[33] in[34] in[35] ++in[36] in[19] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] out[28] ++out[29] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[19] ++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] ins1in20Bx18 +Xwire90@0 hcl[1] net@13 wire90-2550-layer_1-width_3 +Xwire90@1 hcl[1] net@11 wire90-2550-layer_1-width_3 +.ENDS ins1in20Bx36 + +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_60 d g s +MNMOSf@0 d g s gnd nch W='180*(1+ABN/sqrt(180*2))' L='2' ++DELVTO='AVT0N/sqrt(180*2)' +.ENDS NMOSx-X_60 + +*** CELL: orangeTSMC090nm:PMOSx{sch} +.SUBCKT PMOSx-X_60 d g s +MPMOSf@0 d g s vdd pch W='360*(1+ABP/sqrt(360*2))' L='2' ++DELVTO='AVT0P/sqrt(360*2)' +.ENDS PMOSx-X_60 + +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_60 in out +XNMOS@0 out in gnd NMOSx-X_60 +XPMOS@0 out in vdd PMOSx-X_60 +.ENDS inv-X_60 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-544_2-R_34_667m a b +Ccap@0 gnd net@14 1.995f +Ccap@1 gnd net@8 1.995f +Ccap@2 gnd net@11 1.995f +Rres@0 net@14 a 3.144 +Rres@1 net@11 net@14 6.289 +Rres@2 b net@8 3.144 +Rres@3 net@8 net@11 6.289 +.ENDS wire-C_0_011f-544_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-544_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-544_2-R_34_667m +.ENDS wire90-544_2-layer_1-width_3 + +*** CELL: driversJ:latchDriver60{sch} +.SUBCKT latchDriver60 in out +Xinv@1 in net@16 inv-X_20 +XinvI@0 net@8 out inv-X_60 +Xwire90@0 net@16 net@8 wire90-544_2-layer_1-width_3 +.ENDS latchDriver60 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-124_4-R_34_667m a b +Ccap@0 gnd net@14 0.456f +Ccap@1 gnd net@8 0.456f +Ccap@2 gnd net@11 0.456f +Rres@0 net@14 a 0.719 +Rres@1 net@11 net@14 1.438 +Rres@2 b net@8 0.719 +Rres@3 net@8 net@11 1.438 +.ENDS wire-C_0_011f-124_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-124_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-124_4-R_34_667m +.ENDS wire90-124_4-layer_1-width_3 + +*** CELL: latchPartsK:latchPointF{sch} +.SUBCKT latchPointF hcl in[1] x[F] x[T] +XPMOSx@0 in[1] hcl x[T] NMOSx-X_3 +XPMOSx@1 net@8 hcl x[F] NMOSx-X_6 +Xinv@0 in[1] net@105 invLT-X_5 +Xwire90@0 net@105 net@8 wire90-124_4-layer_1-width_3 +.ENDS latchPointF + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-146_1-R_34_667m a b +Ccap@0 gnd net@14 0.536f +Ccap@1 gnd net@8 0.536f +Ccap@2 gnd net@11 0.536f +Rres@0 net@14 a 0.844 +Rres@1 net@11 net@14 1.688 +Rres@2 b net@8 0.844 +Rres@3 net@8 net@11 1.688 +.ENDS wire-C_0_011f-146_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-146_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-146_1-R_34_667m +.ENDS wire90-146_1-layer_1-width_3 + +*** CELL: latchesK:raw1inLatchF{sch} +.SUBCKT raw1inLatchF hcl in[1] out[F] +XlatchFlo@0 out[F] net@58 latchKeep +XlatchPoi@0 hcl in[1] out[F] net@45 latchPointF +Xwire90@0 net@45 net@58 wire90-146_1-layer_1-width_3 +.ENDS raw1inLatchF + +*** CELL: redFive:invLT{sch} +.SUBCKT invLT-X_10 in out +XNMOS@0 out in gnd NMOSx-X_20 +XPMOS@0 out in vdd PMOSx-X_10 +.ENDS invLT-X_10 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-282-R_34_667m a b +Ccap@0 gnd net@14 1.034f +Ccap@1 gnd net@8 1.034f +Ccap@2 gnd net@11 1.034f +Rres@0 net@14 a 1.629 +Rres@1 net@11 net@14 3.259 +Rres@2 b net@8 1.629 +Rres@3 net@8 net@11 3.259 +.ENDS wire-C_0_011f-282-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-282-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-282-R_34_667m +.ENDS wire90-282-layer_1-width_3 + +*** CELL: latchesK:latch1in10A{sch} +.SUBCKT latch1in10A hcl in[1] out[1] +Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF +XinvLT@0 net@18 out[1] invLT-X_10 +Xwire90@0 net@19 net@18 wire90-282-layer_1-width_3 +.ENDS latch1in10A + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-145_9-R_34_667m a b +Ccap@0 gnd net@14 0.535f +Ccap@1 gnd net@8 0.535f +Ccap@2 gnd net@11 0.535f +Rres@0 net@14 a 0.843 +Rres@1 net@11 net@14 1.686 +Rres@2 b net@8 0.843 +Rres@3 net@8 net@11 1.686 +.ENDS wire-C_0_011f-145_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-145_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-145_9-R_34_667m +.ENDS wire90-145_9-layer_1-width_3 + +*** CELL: latchesK:raw2inLatchF{sch} +.SUBCKT raw2inLatchF hcl[A] hcl[B] inA[1] inB[1] out[F] +XlatchKee@0 out[F] net@63 latchKeep +XlatchPoi@0 hcl[A] inA[1] out[F] net@45 latchPointF +XlatchPoi@1 hcl[B] inB[1] out[F] net@45 latchPointF +Xwire90@0 net@45 net@63 wire90-145_9-layer_1-width_3 +.ENDS raw2inLatchF *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-214_6-R_34_667m a b -Ccap@0 gnd net@14 0.787f -Ccap@1 gnd net@8 0.787f -Ccap@2 gnd net@11 0.787f -Rres@0 net@14 a 1.24 -Rres@1 net@11 net@14 2.48 -Rres@2 b net@8 1.24 -Rres@3 net@8 net@11 2.48 -.ENDS wire-C_0_011f-214_6-R_34_667m +.SUBCKT wire-C_0_011f-311_7-R_34_667m a b +Ccap@0 gnd net@14 1.143f +Ccap@1 gnd net@8 1.143f +Ccap@2 gnd net@11 1.143f +Rres@0 net@14 a 1.801 +Rres@1 net@11 net@14 3.602 +Rres@2 b net@8 1.801 +Rres@3 net@8 net@11 3.602 +.ENDS wire-C_0_011f-311_7-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-214_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-214_6-R_34_667m -.ENDS wire90-214_6-layer_1-width_3 - -*** CELL: latchesK:latch1in20B{sch} -.SUBCKT latch1in20B hcl in[1] out[1] -Xhi2inLat@0 hcl in[1] net@19 raw1inLatchT -Xinv@0 net@23 out[1] inv-X_20 -XinvLT@0 net@18 net@25 inv-X_5 -Xwire90@0 net@19 net@18 wire90-250_9-layer_1-width_3 -Xwire90@1 net@25 net@23 wire90-214_6-layer_1-width_3 -.ENDS latch1in20B +.SUBCKT wire90-311_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-311_7-R_34_667m +.ENDS wire90-311_7-layer_1-width_3 -*** CELL: registersL:short20Bx18{sch} -.SUBCKT short20Bx18 hcl[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] -+in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] -+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] -+out[3] out[4] out[5] out[6] out[7] out[8] out[9] -Xlx[1] hcl[1] in[1] out[1] latch1in20B -Xlx[2] hcl[1] in[2] out[2] latch1in20B -Xlx[3] hcl[1] in[3] out[3] latch1in20B -Xlx[4] hcl[1] in[4] out[4] latch1in20B -Xlx[5] hcl[1] in[5] out[5] latch1in20B -Xlx[6] hcl[1] in[6] out[6] latch1in20B -Xlx[7] hcl[1] in[7] out[7] latch1in20B -Xlx[8] hcl[1] in[8] out[8] latch1in20B -Xlx[9] hcl[1] in[9] out[9] latch1in20B -Xlx[10] hcl[1] in[10] out[10] latch1in20B -Xlx[11] hcl[1] in[11] out[11] latch1in20B -Xlx[12] hcl[1] in[12] out[12] latch1in20B -Xlx[13] hcl[1] in[13] out[13] latch1in20B -Xlx[14] hcl[1] in[14] out[14] latch1in20B -Xlx[15] hcl[1] in[15] out[15] latch1in20B -Xlx[16] hcl[1] in[16] out[16] latch1in20B -Xlx[17] hcl[1] in[17] out[17] latch1in20B -Xlx[18] hcl[1] in[18] out[18] latch1in20B -.ENDS short20Bx18 - -*** CELL: registersL:short20Bx36{sch} -.SUBCKT short20Bx36 hcl[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] -+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] -+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] -+in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] -+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] -+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] -+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] -+out[6] out[7] out[8] out[9] -Xshort20B@0 hcl[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] -+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3] -+out[4] out[5] out[6] out[7] out[8] out[9] short20Bx18 -Xshort20B@1 hcl[1] in[28] in[29] in[30] in[31] in[32] in[33] in[34] in[35] -+in[36] in[19] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] out[28] -+out[29] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[19] -+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] short20Bx18 -.ENDS short20Bx36 +*** CELL: latchesK:latch2in10Alo{sch} +.SUBCKT latch2in10Alo hcl[A] hcl[B] inA[1] inB[1] out[1] +Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] dataBar raw2inLatchF +XinvLT@0 net@15 out[1] invLT-X_10 +Xwire90@0 dataBar net@15 wire90-311_7-layer_1-width_3 +.ENDS latch2in10Alo *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-3704_051-R_34_667m a b -Ccap@0 gnd net@14 13.582f -Ccap@1 gnd net@8 13.582f -Ccap@2 gnd net@11 13.582f -Rres@0 net@14 a 21.401 -Rres@1 net@11 net@14 42.802 -Rres@2 b net@8 21.401 -Rres@3 net@8 net@11 42.802 -.ENDS wire-C_0_011f-3704_051-R_34_667m +.SUBCKT wire-C_0_011f-218_4-R_34_667m a b +Ccap@0 gnd net@14 0.801f +Ccap@1 gnd net@8 0.801f +Ccap@2 gnd net@11 0.801f +Rres@0 net@14 a 1.262 +Rres@1 net@11 net@14 2.524 +Rres@2 b net@8 1.262 +Rres@3 net@8 net@11 2.524 +.ENDS wire-C_0_011f-218_4-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-3704_051-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-3704_051-R_34_667m -.ENDS wire90-3704_051-layer_1-width_3 +.SUBCKT wire90-218_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-218_4-R_34_667m +.ENDS wire90-218_4-layer_1-width_3 + +*** CELL: scanJ:scanCellE{sch} +.SUBCKT scanJ__scanCellE dIn[1] p1p p2p rd sin sout +Xlatch1in@0 p2p sin net@2 latch1in10A +Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo +Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3 +.ENDS scanJ__scanCellE + +*** CELL: scanJ:scanEx1vertA{sch} +.SUBCKT scanEx1vertA dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sor[1] +XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanJ__scanCellE +.ENDS scanEx1vertA -*** CELL: stepsM:epiStep{sch} -.SUBCKT epiStep in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +*** CELL: stagesM:epiDockStage{sch} +.SUBCKT epiDockStage do[epi] epi[10] epi[11] epi[12] epi[13] epi[14] epi[15] ++epi[16] epi[17] epi[18] epi[19] epi[1] epi[20] epi[21] epi[22] epi[23] ++epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30] epi[31] ++epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6] epi[7] ++epi[8] epi[9] epi[OTHER] epi[TAIL] epi[TORP] in[10] in[11] in[12] in[13] ++in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] ++in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] ++in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] sir[1] ++sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] take[epi] +XanEpiSta@1 epi[OTHER] epi[TAIL] epi[TORP] net@5 sir[9] do[epi] net@47 in[28] ++in[T] gaspEpi +Xins1in20@0 take[epi] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] +in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] in[T] mc out[10] out[11] out[12] out[13] -+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] -+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] -+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] -+out[6] out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sir[9] sor[1] succ torp -XanEpiSta@0 net@5 mc pred net@27 succ in[T] torp anEpiStart -XlatchDri@0 net@0 net@13 latchDriver60 -XscanEx1v@0 net@27 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++in[4] in[5] in[6] in[7] in[8] in[9] epi[10] epi[11] epi[12] epi[13] epi[14] ++epi[15] epi[16] epi[17] epi[18] epi[19] epi[1] epi[20] epi[21] epi[22] ++epi[23] epi[24] epi[25] epi[26] epi[27] epi[28] epi[29] epi[2] epi[30] ++epi[31] epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6] ++epi[7] epi[8] epi[9] ins1in20Bx36 +XlatchDri@0 net@0 take[epi] latchDriver60 +XscanEx1v@1 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] +sir[8] sor[1] scanEx1vertA -Xshort20B@0 net@15 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] -+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] -+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] -+out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] -+out[7] out[8] out[9] short20Bx36 Xwire90@0 net@0 net@5 wire90-372_8-layer_1-width_3 -Xwire90@1 net@13 net@15 wire90-3704_051-layer_1-width_3 -.ENDS epiStep - -*** CELL: redFour:nms2_sy{sch} -.SUBCKT nms2_sy-X_40 d g g2 -Xnms2@0 d g g2 nms2-X_20 -Xnms2@1 d g2 g nms2-X_20 -.ENDS nms2_sy-X_40 - -*** CELL: redFour:nand2_sy{sch} -.SUBCKT nand2_sy-X_40 ina inb out -XPMOS@0 out inb vdd PMOSx-X_40 -XPMOS@1 out ina vdd PMOSx-X_40 -Xnms2_sy@0 out ina inb nms2_sy-X_40 -.ENDS nand2_sy-X_40 - -*** CELL: redFour:nor2HT_sy{sch} -.SUBCKT nor2HT_sy-X_10 ina inb out -XNMOS@0 out inb gnd NMOSx-X_5 -XNMOS@1 out ina gnd NMOSx-X_5 -Xpms2_sy@0 out ina inb pms2_sy-X_10 -.ENDS nor2HT_sy-X_10 +.ENDS epiDockStage -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-521_7-R_34_667m a b -Ccap@0 gnd net@14 1.913f -Ccap@1 gnd net@8 1.913f -Ccap@2 gnd net@11 1.913f -Rres@0 net@14 a 3.014 -Rres@1 net@11 net@14 6.029 -Rres@2 b net@8 3.014 -Rres@3 net@8 net@11 6.029 -.ENDS wire-C_0_011f-521_7-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-521_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-521_7-R_34_667m -.ENDS wire90-521_7-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-509_8-R_34_667m a b -Ccap@0 gnd net@14 1.869f -Ccap@1 gnd net@8 1.869f -Ccap@2 gnd net@11 1.869f -Rres@0 net@14 a 2.946 -Rres@1 net@11 net@14 5.891 -Rres@2 b net@8 2.946 -Rres@3 net@8 net@11 5.891 -.ENDS wire-C_0_011f-509_8-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-509_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-509_8-R_34_667m -.ENDS wire90-509_8-layer_1-width_3 +*** CELL: redFive:nand2LT_sy{sch} +.SUBCKT nand2LT_sy-X_10 ina inb out +XPMOS@0 out ina vdd PMOSx-X_5 +XPMOS@1 out inb vdd PMOSx-X_5 +Xnms2_sy@0 out ina inb nms2_sy-X_10 +.ENDS nand2LT_sy-X_10 -*** CELL: centersJ:ctrAND4in40{sch} -.SUBCKT ctrAND4in40 inA inB inC inD out -Xnand2_sy@0 net@58 net@43 out nand2_sy-X_40 -Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_10 -Xnor2n_sy@0 inD inC net@64 nor2n_sy-X_10 -Xwire90@0 net@64 net@43 wire90-521_7-layer_1-width_3 -Xwire90@2 net@61 net@58 wire90-509_8-layer_1-width_3 -.ENDS ctrAND4in40 +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_12 d g s +MNMOSf@0 d g s gnd nch W='36*(1+ABN/sqrt(36*2))' L='2' ++DELVTO='AVT0N/sqrt(36*2)' +.ENDS NMOSx-X_12 *** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_6 d g s -MPMOSf@0 d g s vdd pch W='36*(1+ABP/sqrt(36*2))' L='2' -+DELVTO='AVT0P/sqrt(36*2)' -.ENDS PMOSx-X_6 - -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_6 in out -XNMOS@0 out in gnd NMOSx-X_6 -XPMOS@0 out in vdd PMOSx-X_6 -.ENDS inv-X_6 +.SUBCKT PMOSx-X_9_999 d g s +MPMOSf@0 d g s vdd pch W='59.994*(1+ABP/sqrt(59.994*2))' L='2' ++DELVTO='AVT0P/sqrt(59.994*2)' +.ENDS PMOSx-X_9_999 + +*** CELL: redFive:pms3{sch} +.SUBCKT pms3-X_3_333 d g g2 g3 +XPMOS@0 d g3 net@2 PMOSx-X_9_999 +XPMOS@1 net@2 g2 net@5 PMOSx-X_9_999 +XPMOS@2 net@5 g vdd PMOSx-X_9_999 +.ENDS pms3-X_3_333 + +*** CELL: gates3inM:nor3in6.6sym{sch} +.SUBCKT nor3in6_6sym inA inB inC out +XNMOSx@0 out inC gnd NMOSx-X_12 +XNMOSx@7 out inB gnd NMOSx-X_12 +XNMOSx@8 out inA gnd NMOSx-X_12 +Xpms3@0 out inA inB inC pms3-X_3_333 +Xpms3@1 out inC inB inA pms3-X_3_333 +.ENDS nor3in6_6sym + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-956_7-R_34_667m a b +Ccap@0 gnd net@14 3.508f +Ccap@1 gnd net@8 3.508f +Ccap@2 gnd net@11 3.508f +Rres@0 net@14 a 5.528 +Rres@1 net@11 net@14 11.055 +Rres@2 b net@8 5.528 +Rres@3 net@8 net@11 11.055 +.ENDS wire-C_0_011f-956_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-956_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-956_7-R_34_667m +.ENDS wire90-956_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-294_8-R_34_667m a b +Ccap@0 gnd net@14 1.081f +Ccap@1 gnd net@8 1.081f +Ccap@2 gnd net@11 1.081f +Rres@0 net@14 a 1.703 +Rres@1 net@11 net@14 3.407 +Rres@2 b net@8 1.703 +Rres@3 net@8 net@11 3.407 +.ENDS wire-C_0_011f-294_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-294_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-294_8-R_34_667m +.ENDS wire90-294_8-layer_1-width_3 + +*** CELL: oneHotM:onDeck{sch} +.SUBCKT onDeck bits[ABORT] bits[HEAD] fire[od] flag[A][clr] flag[A][set] ++flag[D][clr] flag[D][set] mc od[ABORT] od[HEAD] od[OTHER] pred s[1] s[2] +Xinv@8 pred net@358 inv-X_5 +Xinv@9 bits[HEAD] net@441 inv-X_5 +Xinv@10 bits[ABORT] net@463 inv-X_5 +XinvI@1 net@368 fire[od] inv-X_30 +XinvI@2 net@317 s[2] inv-X_10 +XinvI@3 net@314 s[1] inv-X_10 +Xnand2LT_@0 net@371 net@374 net@367 nand2LT_sy-X_10 +Xnor2_sy@4 flag[A][set] flag[A][clr] net@305 nor2_sy-X_5 +Xnor2_sy@5 flag[D][set] flag[D][clr] net@297 nor2_sy-X_5 +Xnor3in3_@2 net@317 net@436 net@314 net@322 nor3in6_6sym +Xnor3in3_@5 od[ABORT] od[OTHER] od[HEAD] net@476 nor3in6_6sym +XpredDri2@2 fire[od] mc pred predDri20wMC +Xsuc3ANDd@1 net@438 net@485 fire[od] od[OTHER] suc3ANDdri20 +XsucANDdr@0 bits[HEAD] net@444 od[HEAD] sucANDdri20 +XsucANDdr@4 bits[ABORT] fire[od] od[ABORT] sucANDdri20 +Xwire90@10 fire[od] net@444 wire90-956_7-layer_1-width_3 +Xwire90@11 net@322 net@374 wire90-294_8-layer_1-width_3 +Xwire90@13 net@297 net@317 wire90-294_8-layer_1-width_3 +Xwire90@15 net@305 net@436 wire90-294_8-layer_1-width_3 +Xwire90@16 net@358 net@314 wire90-294_8-layer_1-width_3 +Xwire90@18 net@371 net@476 wire90-294_8-layer_1-width_3 +Xwire90@19 net@368 net@367 wire90-294_8-layer_1-width_3 +Xwire90@20 net@441 net@438 wire90-294_8-layer_1-width_3 +Xwire90@21 net@463 net@485 wire90-294_8-layer_1-width_3 +.ENDS onDeck + +*** CELL: scanM:scanCellE{sch} +.SUBCKT scanM__scanCellE dIn[1] p1p p2p rd sin sout +Xlatch1in@0 p2p sin net@2 latch1in10A +Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo +Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3 +.ENDS scanM__scanCellE *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-124_7-R_34_667m a b -Ccap@0 gnd net@14 0.457f -Ccap@1 gnd net@8 0.457f -Ccap@2 gnd net@11 0.457f -Rres@0 net@14 a 0.72 -Rres@1 net@11 net@14 1.441 -Rres@2 b net@8 0.72 -Rres@3 net@8 net@11 1.441 -.ENDS wire-C_0_011f-124_7-R_34_667m +.SUBCKT wire-C_0_011f-297_6-R_34_667m a b +Ccap@0 gnd net@14 1.091f +Ccap@1 gnd net@8 1.091f +Ccap@2 gnd net@11 1.091f +Rres@0 net@14 a 1.719 +Rres@1 net@11 net@14 3.439 +Rres@2 b net@8 1.719 +Rres@3 net@8 net@11 3.439 +.ENDS wire-C_0_011f-297_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-124_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-124_7-R_34_667m -.ENDS wire90-124_7-layer_1-width_3 +.SUBCKT wire90-297_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-297_6-R_34_667m +.ENDS wire90-297_6-layer_1-width_3 + +*** CELL: scanM:scanEx2{sch} +.SUBCKT scanEx2 dIn[1] dIn[2] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sor[1] +XscanCell@3 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanM__scanCellE +XscanCell@4 dIn[2] sir[3] sir[2] sir[5] net@27 sor[1] scanM__scanCellE +Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3 +.ENDS scanEx2 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-503_4-R_34_667m a b -Ccap@0 gnd net@14 1.846f -Ccap@1 gnd net@8 1.846f -Ccap@2 gnd net@11 1.846f -Rres@0 net@14 a 2.909 -Rres@1 net@11 net@14 5.817 -Rres@2 b net@8 2.909 -Rres@3 net@8 net@11 5.817 -.ENDS wire-C_0_011f-503_4-R_34_667m +.SUBCKT wire-C_0_011f-791_7-R_34_667m a b +Ccap@0 gnd net@14 2.903f +Ccap@1 gnd net@8 2.903f +Ccap@2 gnd net@11 2.903f +Rres@0 net@14 a 4.574 +Rres@1 net@11 net@14 9.149 +Rres@2 b net@8 4.574 +Rres@3 net@8 net@11 9.149 +.ENDS wire-C_0_011f-791_7-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-503_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-503_4-R_34_667m -.ENDS wire90-503_4-layer_1-width_3 - -*** CELL: driversL:sucDri20{sch} -.SUBCKT sucDri20 in succ -XPMOSx@0 succ net@46 vdd PMOSx-X_20 -Xinv@1 succ net@94 inv-X_4 -Xinv@2 in net@110 inv-X_6 -Xnms2@0 succ net@117 net@46 nms2-X_2 -Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3 -Xwire90@1 net@110 net@46 wire90-503_4-layer_1-width_3 -.ENDS sucDri20 - -*** CELL: redFour:pms2{sch} -.SUBCKT pms2-X_20 d g g2 -XPMOS@0 net@2 g vdd PMOSx-X_40 -XPMOS@1 d g2 net@2 PMOSx-X_40 -.ENDS pms2-X_20 +.SUBCKT wire90-791_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-791_7-R_34_667m +.ENDS wire90-791_7-layer_1-width_3 -*** CELL: driversL:sucDri20cond{sch} -.SUBCKT sucDri20cond cond in succ -XNMOSx@0 succ in net@160 NMOSx-X_5 -XNMOSx@1 succ cond net@160 NMOSx-X_5 -XNMOSx@2 net@160 net@158 gnd NMOSx-X_10 -Xinv@1 succ net@94 inv-X_5 -Xpms2@0 succ cond in pms2-X_20 -Xwire90@0 net@158 net@94 wire90-124_7-layer_1-width_3 -.ENDS sucDri20cond +*** CELL: stagesM:onDeckDockStage{sch} +.SUBCKT onDeckDockStage do[od] flag[A][clr] flag[A][set] flag[D][clr] ++flag[D][set] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] ++m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] ++m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] ++m1[5] m1[6] m1[7] m1[8] m1[9] od[10] od[11] od[12] od[13] od[14] od[15] ++od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25] ++od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35] ++od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] od[ABORT] od[HEAD] od[OTHER] ++sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] ++take[od] +Xins1in20@0 take[od] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] ++m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] ++m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] ++m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] od[10] od[11] od[12] od[13] od[14] od[15] ++od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25] ++od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35] ++od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] ins1in20Bx36 +XlatchDri@0 fire[1] take[od] latchDriver60 +XonDeck@0 m1[29] m1[30] net@11 flag[A][clr] flag[A][set] flag[D][clr] ++flag[D][set] sir[9] od[ABORT] od[HEAD] od[OTHER] do[od] net@62[1] net@62[0] ++onDeck +XscanEx2v@2 net@62[1] net@62[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sor[1] scanEx2 +Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3 +.ENDS onDeckDockStage *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-247_2-R_34_667m a b -Ccap@0 gnd net@14 0.906f -Ccap@1 gnd net@8 0.906f -Ccap@2 gnd net@11 0.906f -Rres@0 net@14 a 1.428 -Rres@1 net@11 net@14 2.857 -Rres@2 b net@8 1.428 -Rres@3 net@8 net@11 2.857 -.ENDS wire-C_0_011f-247_2-R_34_667m +.SUBCKT wire-C_0_011f-242_1-R_34_667m a b +Ccap@0 gnd net@14 0.888f +Ccap@1 gnd net@8 0.888f +Ccap@2 gnd net@11 0.888f +Rres@0 net@14 a 1.399 +Rres@1 net@11 net@14 2.798 +Rres@2 b net@8 1.399 +Rres@3 net@8 net@11 2.798 +.ENDS wire-C_0_011f-242_1-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-247_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-247_2-R_34_667m -.ENDS wire90-247_2-layer_1-width_3 - -*** CELL: gaspL:aStageM1{sch} -.SUBCKT aStageM1 do[M] fire mc pred s[1] selLO[Dm] succ wait[M] -XctrAND4i@0 succ net@1081 do[M] wait[M] net@1034 ctrAND4in40 -Xinv@4 net@987 s[1] inv-X_10 -Xinv@5 pred net@987 inv-X_5 -Xinv@6 net@1036 fire inv-X_100 -Xinv@7 fire net@1070 inv-X_10 -XpredDri2@1 fire mc pred predDri20wMC -XsucDri20@1 fire succ sucDri20 -XsucDri20@2 selLO[Dm] net@1071 wait[M] sucDri20cond -Xwire90@0 net@987 net@1081 wire90-247_2-layer_1-width_3 -Xwire90@1 net@1036 net@1034 wire90-247_2-layer_1-width_3 -Xwire90@2 net@1070 net@1071 wire90-247_2-layer_1-width_3 -.ENDS aStageM1 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-3715_9-R_34_667m a b -Ccap@0 gnd net@14 13.625f -Ccap@1 gnd net@8 13.625f -Ccap@2 gnd net@11 13.625f -Rres@0 net@14 a 21.47 -Rres@1 net@11 net@14 42.939 -Rres@2 b net@8 21.47 -Rres@3 net@8 net@11 42.939 -.ENDS wire-C_0_011f-3715_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-3715_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-3715_9-R_34_667m -.ENDS wire90-3715_9-layer_1-width_3 - -*** CELL: stepsM:m1step{sch} -.SUBCKT m1step do[M] fire[m1] in[10] in[11] in[12] in[13] in[14] in[15] -+in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] -+in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] -+in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] m1[10] m1[11] m1[12] m1[13] -+m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] -+m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] -+m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc pred s[1] -+succ wait[M] -XaStageM1@0 do[M] fire[m1] mc pred s[1] in[25] succ wait[M] aStageM1 -XlatchDri@0 fire[m1] take[1] latchDriver60 -Xshort20B@0 net@12 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] -+m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] -+m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] -+m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] short20Bx36 -Xwire90@0 net@12 take[1] wire90-3715_9-layer_1-width_3 -.ENDS m1step - -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_15 d g s -MPMOSf@0 d g s vdd pch W='90*(1+ABP/sqrt(90*2))' L='2' -+DELVTO='AVT0P/sqrt(90*2)' -.ENDS PMOSx-X_15 +.SUBCKT wire90-242_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-242_1-R_34_667m +.ENDS wire90-242_1-layer_1-width_3 -*** CELL: redFour:nms2{sch} -.SUBCKT nms2-X_15 d g g2 -XNMOS@0 d g2 net@0 NMOSx-X_30 -XNMOS@1 net@0 g gnd NMOSx-X_30 -.ENDS nms2-X_15 +*** CELL: latchesK:latch2in20A{sch} +.SUBCKT latch2in20A hcl[A] hcl[B] inA[1] inB[1] out[1] +Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@36 raw2inLatchF +XinvLT@1 net@16 out[1] inv-X_20 +Xwire90@1 net@36 net@16 wire90-242_1-layer_1-width_3 +.ENDS latch2in20A -*** CELL: redFour:nms2_sy{sch} -.SUBCKT nms2_sy-X_30 d g g2 -Xnms2@0 d g g2 nms2-X_15 -Xnms2@1 d g2 g nms2-X_15 -.ENDS nms2_sy-X_30 +*** CELL: registersM:ins2in20Ax18{sch} +.SUBCKT ins2in20Ax18 hcl[A] hcl[B] inA[10] inA[11] inA[12] inA[13] inA[14] ++inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] ++inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] ++inB[17] inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] ++inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] ++out[18] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] +Xlx[1] hcl[A] hcl[B] inA[1] inB[1] out[1] latch2in20A +Xlx[2] hcl[A] hcl[B] inA[2] inB[2] out[2] latch2in20A +Xlx[3] hcl[A] hcl[B] inA[3] inB[3] out[3] latch2in20A +Xlx[4] hcl[A] hcl[B] inA[4] inB[4] out[4] latch2in20A +Xlx[5] hcl[A] hcl[B] inA[5] inB[5] out[5] latch2in20A +Xlx[6] hcl[A] hcl[B] inA[6] inB[6] out[6] latch2in20A +Xlx[7] hcl[A] hcl[B] inA[7] inB[7] out[7] latch2in20A +Xlx[8] hcl[A] hcl[B] inA[8] inB[8] out[8] latch2in20A +Xlx[9] hcl[A] hcl[B] inA[9] inB[9] out[9] latch2in20A +Xlx[10] hcl[A] hcl[B] inA[10] inB[10] out[10] latch2in20A +Xlx[11] hcl[A] hcl[B] inA[11] inB[11] out[11] latch2in20A +Xlx[12] hcl[A] hcl[B] inA[12] inB[12] out[12] latch2in20A +Xlx[13] hcl[A] hcl[B] inA[13] inB[13] out[13] latch2in20A +Xlx[14] hcl[A] hcl[B] inA[14] inB[14] out[14] latch2in20A +Xlx[15] hcl[A] hcl[B] inA[15] inB[15] out[15] latch2in20A +Xlx[16] hcl[A] hcl[B] inA[16] inB[16] out[16] latch2in20A +Xlx[17] hcl[A] hcl[B] inA[17] inB[17] out[17] latch2in20A +Xlx[18] hcl[A] hcl[B] inA[18] inB[18] out[18] latch2in20A +.ENDS ins2in20Ax18 + +*** CELL: registersM:ins2in20Ax36{sch} +.SUBCKT ins2in20Ax36 hcl[A] hcl[B] inA[10] inA[11] inA[12] inA[13] inA[14] ++inA[15] inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] ++inA[23] inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] ++inA[31] inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] ++inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] ++inB[17] inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] ++inB[25] inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] ++inB[33] inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] ++inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] ++out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] ++out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] ++out[34] out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] +Xins2in20@2 net@178 net@162 inA[28] inA[29] inA[30] inA[31] inA[32] inA[33] ++inA[34] inA[35] inA[36] inA[19] inA[20] inA[21] inA[22] inA[23] inA[24] ++inA[25] inA[26] inA[27] inB[28] inB[29] inB[30] inB[31] inB[32] inB[33] ++inB[34] inB[35] inB[36] inB[19] inB[20] inB[21] inB[22] inB[23] inB[24] ++inB[25] inB[26] inB[27] out[28] out[29] out[30] out[31] out[32] out[33] ++out[34] out[35] out[36] out[19] out[20] out[21] out[22] out[23] out[24] ++out[25] out[26] out[27] ins2in20Ax18 +Xins2in20@3 net@157 net@177 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] ++inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inA[7] ++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17] ++inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9] ++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] ++out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax18 +Xwire90@0 net@178 hcl[A] wire90-2550-layer_1-width_3 +Xwire90@1 hcl[A] net@157 wire90-2550-layer_1-width_3 +Xwire90@2 net@162 hcl[B] wire90-2550-layer_1-width_3 +Xwire90@3 hcl[B] net@177 wire90-2550-layer_1-width_3 +.ENDS ins2in20Ax36 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-927-R_34_667m a b +Ccap@0 gnd net@14 3.399f +Ccap@1 gnd net@8 3.399f +Ccap@2 gnd net@11 3.399f +Rres@0 net@14 a 5.356 +Rres@1 net@11 net@14 10.712 +Rres@2 b net@8 5.356 +Rres@3 net@8 net@11 10.712 +.ENDS wire-C_0_011f-927-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-927-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-927-R_34_667m +.ENDS wire90-927-layer_1-width_3 + +*** CELL: centersJ:ctrAND1in30{sch} +.SUBCKT ctrAND1in30 in out +Xinv@11 net@125 net@120 inv-X_10 +XinvI@1 net@82 out inv-X_30 +XinvI@2 in net@101 inv-X_5 +Xwire90@1 net@101 net@125 wire90-414-layer_1-width_3 +Xwire90@2 net@120 net@82 wire90-927-layer_1-width_3 +.ENDS ctrAND1in30 -*** CELL: redFour:nand2LT_sy{sch} -.SUBCKT nand2LT_sy-X_30 ina inb out -XPMOS@0 out ina vdd PMOSx-X_15 -XPMOS@1 out inb vdd PMOSx-X_15 -Xnms2_sy@0 out ina inb nms2_sy-X_30 -.ENDS nand2LT_sy-X_30 +*** CELL: orangeTSMC090nm:PMOSx{sch} +.SUBCKT PMOSx-X_6 d g s +MPMOSf@0 d g s vdd pch W='36*(1+ABP/sqrt(36*2))' L='2' ++DELVTO='AVT0P/sqrt(36*2)' +.ENDS PMOSx-X_6 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-399_2-R_34_667m a b -Ccap@0 gnd net@14 1.464f -Ccap@1 gnd net@8 1.464f -Ccap@2 gnd net@11 1.464f -Rres@0 net@14 a 2.306 -Rres@1 net@11 net@14 4.613 -Rres@2 b net@8 2.306 -Rres@3 net@8 net@11 4.613 -.ENDS wire-C_0_011f-399_2-R_34_667m +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_6 in out +XNMOS@0 out in gnd NMOSx-X_6 +XPMOS@0 out in vdd PMOSx-X_6 +.ENDS inv-X_6 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-399_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-399_2-R_34_667m -.ENDS wire90-399_2-layer_1-width_3 +*** CELL: redFive:pms1{sch} +.SUBCKT pms1-X_20 d g +XPMOS@0 d g vdd PMOSx-X_20 +.ENDS pms1-X_20 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1013_8-R_34_667m a b -Ccap@0 gnd net@14 3.717f -Ccap@1 gnd net@8 3.717f -Ccap@2 gnd net@11 3.717f -Rres@0 net@14 a 5.858 -Rres@1 net@11 net@14 11.715 -Rres@2 b net@8 5.858 -Rres@3 net@8 net@11 11.715 -.ENDS wire-C_0_011f-1013_8-R_34_667m +.SUBCKT wire-C_0_011f-124_7-R_34_667m a b +Ccap@0 gnd net@14 0.457f +Ccap@1 gnd net@8 0.457f +Ccap@2 gnd net@11 0.457f +Rres@0 net@14 a 0.72 +Rres@1 net@11 net@14 1.441 +Rres@2 b net@8 0.72 +Rres@3 net@8 net@11 1.441 +.ENDS wire-C_0_011f-124_7-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1013_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1013_8-R_34_667m -.ENDS wire90-1013_8-layer_1-width_3 +.SUBCKT wire90-124_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-124_7-R_34_667m +.ENDS wire90-124_7-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-468_3-R_34_667m a b -Ccap@0 gnd net@14 1.717f -Ccap@1 gnd net@8 1.717f -Ccap@2 gnd net@11 1.717f -Rres@0 net@14 a 2.706 -Rres@1 net@11 net@14 5.411 -Rres@2 b net@8 2.706 -Rres@3 net@8 net@11 5.411 -.ENDS wire-C_0_011f-468_3-R_34_667m +.SUBCKT wire-C_0_011f-503_4-R_34_667m a b +Ccap@0 gnd net@14 1.846f +Ccap@1 gnd net@8 1.846f +Ccap@2 gnd net@11 1.846f +Rres@0 net@14 a 2.909 +Rres@1 net@11 net@14 5.817 +Rres@2 b net@8 2.909 +Rres@3 net@8 net@11 5.817 +.ENDS wire-C_0_011f-503_4-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-468_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-468_3-R_34_667m -.ENDS wire90-468_3-layer_1-width_3 - -*** CELL: centersJ:ctrAND2in100LT{sch} -.SUBCKT ctrAND2in100LT inA inB out -Xinv@8 inB net@135 inv-X_10 -Xinv@9 inA net@139 inv-X_10 -Xinv@10 net@146 out inv-X_100 -Xnand2LT_@0 net@140 net@136 net@144 nand2LT_sy-X_30 -Xwire90@4 net@135 net@136 wire90-399_2-layer_1-width_3 -Xwire90@5 net@144 net@146 wire90-1013_8-layer_1-width_3 -Xwire90@6 net@139 net@140 wire90-468_3-layer_1-width_3 -.ENDS ctrAND2in100LT - -*** CELL: gaspL:aStageB{sch} -.SUBCKT aStageB fire mc pred s[1] succ -XctrAND2i@7 succ net@986 fire ctrAND2in100LT -Xinv@4 net@987 s[1] inv-X_10 -Xinv@5 pred net@987 inv-X_5 -XpredDri2@1 fire mc pred predDri20wMC -XsucDri20@1 fire succ sucDri20 -Xwire90@0 net@987 net@986 wire90-247_2-layer_1-width_3 -.ENDS aStageB - -*** CELL: stepsM:m2step{sch} -.SUBCKT m2step fire[m2] in[10] in[11] in[12] in[13] in[14] in[15] in[16] -+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] -+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] -+in[3] in[4] in[5] in[6] in[7] in[8] in[9] m2[10] m2[11] m2[12] m2[13] m2[14] -+m2[15] m2[16] m2[17] m2[18] m2[19] m2[1] m2[20] m2[21] m2[22] m2[23] m2[24] -+m2[25] m2[26] m2[27] m2[28] m2[29] m2[2] m2[30] m2[31] m2[32] m2[33] m2[34] -+m2[35] m2[36] m2[3] m2[4] m2[5] m2[6] m2[7] m2[8] m2[9] mc pred s[1] succ -XaStageB@0 fire[m2] mc pred s[1] succ aStageB -XlatchDri@0 fire[m2] take[1] latchDriver60 -Xshort20B@0 net@10 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] m2[10] m2[11] m2[12] m2[13] m2[14] m2[15] -+m2[16] m2[17] m2[18] m2[19] m2[1] m2[20] m2[21] m2[22] m2[23] m2[24] m2[25] -+m2[26] m2[27] m2[28] m2[29] m2[2] m2[30] m2[31] m2[32] m2[33] m2[34] m2[35] -+m2[36] m2[3] m2[4] m2[5] m2[6] m2[7] m2[8] m2[9] short20Bx36 -Xwire90@0 net@10 take[1] wire90-3715_9-layer_1-width_3 -.ENDS m2step - -*** CELL: scanJ:scanEx2vert{sch} -.SUBCKT scanEx2vert dIn[1] dIn[2] mc sir[1] sir[2] sir[3] sir[4] sir[5] -+sir[6] sir[7] sir[8] sor[1] -XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanCellE -XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 sor[1] scanCellE -Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3 -.ENDS scanEx2vert +.SUBCKT wire90-503_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-503_4-R_34_667m +.ENDS wire90-503_4-layer_1-width_3 -*** CELL: stepsM:m2m1step{sch} -.SUBCKT m2m1step do[M] fire[m1] fire[m2] in[10] in[11] in[12] in[13] in[14] -+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] -+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] -+in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] m1[10] m1[11] m1[12] -+m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] -+m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] -+m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc pred -+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ -+wait[M] -Xm1step@0 do[M] fire[m1] net@57[26] net@57[25] net@57[24] net@57[23] -+net@57[22] net@57[21] net@57[20] net@57[19] net@57[18] net@57[17] net@57[35] -+net@57[16] net@57[15] net@57[14] net@57[13] net@57[12] net@57[11] net@57[10] -+net@57[9] net@57[8] net@57[7] net@57[34] net@57[6] net@57[5] net@57[4] -+net@57[3] net@57[2] net@57[1] net@57[0] net@57[33] net@57[32] net@57[31] -+net@57[30] net@57[29] net@57[28] net@57[27] m1[10] m1[11] m1[12] m1[13] -+m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] -+m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] -+m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc net@3 s[2] -+succ wait[M] m1step -Xm2step@0 fire[m2] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] net@57[26] net@57[25] net@57[24] -+net@57[23] net@57[22] net@57[21] net@57[20] net@57[19] net@57[18] net@57[17] -+net@57[35] net@57[16] net@57[15] net@57[14] net@57[13] net@57[12] net@57[11] -+net@57[10] net@57[9] net@57[8] net@57[7] net@57[34] net@57[6] net@57[5] -+net@57[4] net@57[3] net@57[2] net@57[1] net@57[0] net@57[33] net@57[32] -+net@57[31] net@57[30] net@57[29] net@57[28] net@57[27] mc pred s[1] net@0 -+m2step -XscanEx2v@0 s[1] s[2] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx2vert -Xwire90@0 net@0 net@3 wire90-3715_9-layer_1-width_3 -.ENDS m2m1step - -*** CELL: gatesK:andOrInv5{sch} -.SUBCKT andOrInv5 inA inB inC inD out -XPMOSx@0 out inA net@42 PMOSx-X_5 -XPMOSx@1 out inB net@42 PMOSx-X_5 -XPMOSx@2 out inC net@39 PMOSx-X_5 -XPMOSx@3 out inD net@39 PMOSx-X_5 -XPMOSx@4 net@39 inA vdd PMOSx-X_5 -XPMOSx@5 net@39 inB vdd PMOSx-X_5 -XPMOSx@6 net@42 inC vdd PMOSx-X_5 -XPMOSx@7 net@42 inD vdd PMOSx-X_5 -Xnms2@0 out inA inB nms2-X_5 -Xnms2@2 out inD inC nms2-X_5 -.ENDS andOrInv5 +*** CELL: driversL:sucDri20{sch} +.SUBCKT sucDri20 in succ +Xinv@1 succ net@94 inv-X_4 +Xinv@2 in net@110 inv-X_6 +Xnms2@0 succ net@117 net@109 nms2-X_2 +Xpms1@0 succ net@109 pms1-X_20 +Xwire90@0 net@117 net@94 wire90-124_7-layer_1-width_3 +Xwire90@1 net@110 net@109 wire90-503_4-layer_1-width_3 +.ENDS sucDri20 -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_2 d g s -MNMOSf@0 d g s gnd nch W='6*(1+ABN/sqrt(6*2))' L='2' DELVTO='AVT0N/sqrt(6*2)' -.ENDS NMOSx-X_2 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-301_8-R_34_667m a b +Ccap@0 gnd net@14 1.107f +Ccap@1 gnd net@8 1.107f +Ccap@2 gnd net@11 1.107f +Rres@0 net@14 a 1.744 +Rres@1 net@11 net@14 3.487 +Rres@2 b net@8 1.744 +Rres@3 net@8 net@11 3.487 +.ENDS wire-C_0_011f-301_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-301_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-301_8-R_34_667m +.ENDS wire90-301_8-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-732_5-R_34_667m a b +Ccap@0 gnd net@14 2.686f +Ccap@1 gnd net@8 2.686f +Ccap@2 gnd net@11 2.686f +Rres@0 net@14 a 4.232 +Rres@1 net@11 net@14 8.464 +Rres@2 b net@8 4.232 +Rres@3 net@8 net@11 8.464 +.ENDS wire-C_0_011f-732_5-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-732_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-732_5-R_34_667m +.ENDS wire90-732_5-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-142_6-R_34_667m a b +Ccap@0 gnd net@14 0.523f +Ccap@1 gnd net@8 0.523f +Ccap@2 gnd net@11 0.523f +Rres@0 net@14 a 0.824 +Rres@1 net@11 net@14 1.648 +Rres@2 b net@8 0.824 +Rres@3 net@8 net@11 1.648 +.ENDS wire-C_0_011f-142_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-142_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-142_6-R_34_667m +.ENDS wire90-142_6-layer_1-width_3 + +*** CELL: oneHotM:reQueueB{sch} +.SUBCKT reQueueB circulate epi[TAIL] mc od[HEAD] s[1] s[2] +XctrAND1i@0 net@1 net@7 ctrAND1in30 +Xinv@2 od[HEAD] net@127 inv-X_5 +Xinv@3 epi[TAIL] net@125 inv-X_5 +XinvI@3 net@128 s[1] inv-X_10 +XinvI@4 net@126 s[2] inv-X_10 +Xnand2@0 od[HEAD] epi[TAIL] net@0 nand2-X_5 +XpredDri2@1 net@7 mc epi[TAIL] predDri20wMC +XpredDri2@2 net@7 mc od[HEAD] predDri20wMC +XsucDri20@0 net@9 circulate sucDri20 +Xwire90@0 net@0 net@1 wire90-301_8-layer_1-width_3 +Xwire90@1 net@7 net@9 wire90-732_5-layer_1-width_3 +Xwire90@2 net@126 net@125 wire90-142_6-layer_1-width_3 +Xwire90@3 net@128 net@127 wire90-142_6-layer_1-width_3 +.ENDS reQueueB + +*** CELL: redFive:nms2{sch} +.SUBCKT nms2-X_10 d g g2 +XNMOS@0 d g2 net@0 NMOSx-X_20 +XNMOS@1 net@0 g gnd NMOSx-X_20 +.ENDS nms2-X_10 -*** CELL: redFour:pms2{sch} -.SUBCKT pms2-X_2 d g g2 -XPMOS@0 net@2 g vdd PMOSx-X_4 -XPMOS@1 d g2 net@2 PMOSx-X_4 -.ENDS pms2-X_2 +*** CELL: redFive:nand2{sch} +.SUBCKT nand2-X_10 ina inb out +XPMOS@0 out ina vdd PMOSx-X_10 +XPMOS@1 out inb vdd PMOSx-X_10 +Xnms2@0 out ina inb nms2-X_10 +.ENDS nand2-X_10 -*** CELL: redFour:pms2_sy{sch} -.SUBCKT pms2_sy-X_4 d g g2 -Xpms2@0 d g g2 pms2-X_2 -Xpms2@1 d g2 g pms2-X_2 -.ENDS pms2_sy-X_4 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-252_6-R_34_667m a b +Ccap@0 gnd net@14 0.926f +Ccap@1 gnd net@8 0.926f +Ccap@2 gnd net@11 0.926f +Rres@0 net@14 a 1.459 +Rres@1 net@11 net@14 2.919 +Rres@2 b net@8 1.459 +Rres@3 net@8 net@11 2.919 +.ENDS wire-C_0_011f-252_6-R_34_667m -*** CELL: redFour:nor2HT_sy{sch} -.SUBCKT nor2HT_sy-X_4 ina inb out -XNMOS@0 out inb gnd NMOSx-X_2 -XNMOS@1 out ina gnd NMOSx-X_2 -Xpms2_sy@0 out ina inb pms2_sy-X_4 -.ENDS nor2HT_sy-X_4 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-252_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-252_6-R_34_667m +.ENDS wire90-252_6-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-249_5-R_34_667m a b -Ccap@0 gnd net@14 0.915f -Ccap@1 gnd net@8 0.915f -Ccap@2 gnd net@11 0.915f -Rres@0 net@14 a 1.442 -Rres@1 net@11 net@14 2.883 -Rres@2 b net@8 1.442 -Rres@3 net@8 net@11 2.883 -.ENDS wire-C_0_011f-249_5-R_34_667m +.SUBCKT wire-C_0_011f-366_8-R_34_667m a b +Ccap@0 gnd net@14 1.345f +Ccap@1 gnd net@8 1.345f +Ccap@2 gnd net@11 1.345f +Rres@0 net@14 a 2.119 +Rres@1 net@11 net@14 4.239 +Rres@2 b net@8 2.119 +Rres@3 net@8 net@11 4.239 +.ENDS wire-C_0_011f-366_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-249_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-249_5-R_34_667m -.ENDS wire90-249_5-layer_1-width_3 +.SUBCKT wire90-366_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-366_8-R_34_667m +.ENDS wire90-366_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-355_8-R_34_667m a b -Ccap@0 gnd net@14 1.305f -Ccap@1 gnd net@8 1.305f -Ccap@2 gnd net@11 1.305f -Rres@0 net@14 a 2.056 -Rres@1 net@11 net@14 4.111 -Rres@2 b net@8 2.056 -Rres@3 net@8 net@11 4.111 -.ENDS wire-C_0_011f-355_8-R_34_667m +.SUBCKT wire-C_0_011f-176_4-R_34_667m a b +Ccap@0 gnd net@14 0.647f +Ccap@1 gnd net@8 0.647f +Ccap@2 gnd net@11 0.647f +Rres@0 net@14 a 1.019 +Rres@1 net@11 net@14 2.038 +Rres@2 b net@8 1.019 +Rres@3 net@8 net@11 2.038 +.ENDS wire-C_0_011f-176_4-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-355_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-355_8-R_34_667m -.ENDS wire90-355_8-layer_1-width_3 +.SUBCKT wire90-176_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-176_4-R_34_667m +.ENDS wire90-176_4-layer_1-width_3 -*** CELL: centersJ:ctrAND2in30{sch} -.SUBCKT ctrAND2in30 inA inB out -Xinv@0 net@7 net@8 inv-X_10 -Xinv@1 net@9 out inv-X_30 -Xnor2HT_s@1 inA inB net@6 nor2HT_sy-X_4 -Xwire90@0 net@6 net@7 wire90-249_5-layer_1-width_3 -Xwire90@1 net@8 net@9 wire90-355_8-layer_1-width_3 -.ENDS ctrAND2in30 +*** CELL: centersJ:ctrAND3in30{sch} +.SUBCKT ctrAND3in30 inA inB inC out +Xinv@4 inC net@30 inv-X_4 +Xinv@5 net@9 out inv-X_30 +Xnand2@0 net@19 net@15 net@27 nand2-X_10 +Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_5 +Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3 +Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3 +Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3 +.ENDS ctrAND3in30 -*** CELL: redFour:nor2{sch} -.SUBCKT nor2-X_5 ina inb out -XNMOS@0 out ina gnd NMOSx-X_5 -XNMOS@1 out inb gnd NMOSx-X_5 -Xpms2@0 out ina inb pms2-X_5 -.ENDS nor2-X_5 +*** CELL: redFive:nms2{sch} +.SUBCKT nms2-X_3 d g g2 +XNMOS@0 d g2 net@0 NMOSx-X_6 +XNMOS@1 net@0 g gnd NMOSx-X_6 +.ENDS nms2-X_3 -*** CELL: redFour:nor2n{sch} -.SUBCKT nor2n-X_5 ina inb out -Xnor2@0 ina inb out nor2-X_5 -.ENDS nor2n-X_5 +*** CELL: redFive:nms2_sy{sch} +.SUBCKT nms2_sy-X_6 d g g2 +Xnms2@0 d g g2 nms2-X_3 +Xnms2@1 d g2 g nms2-X_3 +.ENDS nms2_sy-X_6 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-238_2-R_34_667m a b -Ccap@0 gnd net@14 0.873f -Ccap@1 gnd net@8 0.873f -Ccap@2 gnd net@11 0.873f -Rres@0 net@14 a 1.376 -Rres@1 net@11 net@14 2.753 -Rres@2 b net@8 1.376 -Rres@3 net@8 net@11 2.753 -.ENDS wire-C_0_011f-238_2-R_34_667m +*** CELL: redFive:nand2_sy{sch} +.SUBCKT nand2_sy-X_6 ina inb out +XPMOS@0 out inb vdd PMOSx-X_6 +XPMOS@1 out ina vdd PMOSx-X_6 +Xnms2_sy@0 out ina inb nms2_sy-X_6 +.ENDS nand2_sy-X_6 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-238_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-238_2-R_34_667m -.ENDS wire90-238_2-layer_1-width_3 +*** CELL: redFive:nand2n{sch} +.SUBCKT nand2n-X_5 ina inb out +Xnand2@0 ina inb out nand2-X_5 +.ENDS nand2n-X_5 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-520-R_34_667m a b -Ccap@0 gnd net@14 1.907f -Ccap@1 gnd net@8 1.907f -Ccap@2 gnd net@11 1.907f -Rres@0 net@14 a 3.004 -Rres@1 net@11 net@14 6.009 -Rres@2 b net@8 3.004 -Rres@3 net@8 net@11 6.009 -.ENDS wire-C_0_011f-520-R_34_667m +*** CELL: redFive:nms2_sy{sch} +.SUBCKT nms2_sy-X_20 d g g2 +Xnms2@0 d g g2 nms2-X_10 +Xnms2@1 d g2 g nms2-X_10 +.ENDS nms2_sy-X_20 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-520-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-520-R_34_667m -.ENDS wire90-520-layer_1-width_3 +*** CELL: redFive:nand2_sy{sch} +.SUBCKT nand2_sy-X_20 ina inb out +XPMOS@0 out inb vdd PMOSx-X_20 +XPMOS@1 out ina vdd PMOSx-X_20 +Xnms2_sy@0 out ina inb nms2_sy-X_20 +.ENDS nand2_sy-X_20 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-222_3-R_34_667m a b -Ccap@0 gnd net@14 0.815f -Ccap@1 gnd net@8 0.815f -Ccap@2 gnd net@11 0.815f -Rres@0 net@14 a 1.284 -Rres@1 net@11 net@14 2.569 -Rres@2 b net@8 1.284 -Rres@3 net@8 net@11 2.569 -.ENDS wire-C_0_011f-222_3-R_34_667m +*** CELL: redFive:nand2n_sy{sch} +.SUBCKT nand2n_sy-X_20 ina inb out +Xnand2_sy@0 ina inb out nand2_sy-X_20 +.ENDS nand2n_sy-X_20 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-222_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-222_3-R_34_667m -.ENDS wire90-222_3-layer_1-width_3 +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_9_999 d g s +MNMOSf@0 d g s gnd nch W='29.997*(1+ABN/sqrt(29.997*2))' L='2' ++DELVTO='AVT0N/sqrt(29.997*2)' +.ENDS NMOSx-X_9_999 -*** CELL: centersJ:ctrAND4in30{sch} -.SUBCKT ctrAND4in30 inA inB inC inD out -Xinv@1 net@3 out inv-X_30 -Xnand2@1 net@43 net@58 net@67 nand2-X_10 -Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4 -Xnor2n@0 inD inC net@64 nor2n-X_5 -Xwire90@0 net@64 net@43 wire90-238_2-layer_1-width_3 -Xwire90@1 net@67 net@3 wire90-520-layer_1-width_3 -Xwire90@2 net@61 net@58 wire90-222_3-layer_1-width_3 -.ENDS ctrAND4in30 +*** CELL: redFive:nms3{sch} +.SUBCKT nms3-X_3_333 d g g2 g3 +XNMOS@0 d g3 net@6 NMOSx-X_9_999 +XNMOS@1 net@7 g gnd NMOSx-X_9_999 +XNMOS@2 net@6 g2 net@7 NMOSx-X_9_999 +.ENDS nms3-X_3_333 -*** CELL: driversL:predORdri20wMC{sch} -.SUBCKT predORdri20wMC inA inB mc pred -XNMOSx@0 pred inA gnd NMOSx-X_20 -XNMOSx@1 pred mc gnd NMOSx-X_4 -XNMOSx@2 pred inB gnd NMOSx-X_20 -XPMOSx@1 pred net@217 net@203 PMOSx-X_4 -XPMOSx@2 net@203 inB net@204 PMOSx-X_4 -XPMOSx@3 net@204 inA net@205 PMOSx-X_4 -XPMOSx@4 net@205 mc vdd PMOSx-X_4 -Xinv@0 pred net@145 inv-X_4 -Xwire90@0 net@217 net@145 wire90-243_6-layer_1-width_3 -.ENDS predORdri20wMC +*** CELL: gates3inM:nand3in6.6sym{sch} +.SUBCKT nand3in6_6sym inA inB inC out +XPMOSx@1 out inA vdd PMOSx-X_10 +XPMOSx@3 out inC vdd PMOSx-X_10 +XPMOSx@4 out inB vdd PMOSx-X_10 +Xnms3@0 out inA inB inC nms3-X_3_333 +Xnms3@2 out inC inB inA nms3-X_3_333 +.ENDS nand3in6_6sym -*** CELL: redFour:nms2_sy{sch} -.SUBCKT nms2_sy-X_4 d g g2 -Xnms2@0 d g g2 nms2-X_2 -Xnms2@1 d g2 g nms2-X_2 -.ENDS nms2_sy-X_4 +*** CELL: redFive:pms2{sch} +.SUBCKT pms2-X_10 d g g2 +XPMOS@0 net@2 g vdd PMOSx-X_20 +XPMOS@1 d g2 net@2 PMOSx-X_20 +.ENDS pms2-X_10 -*** CELL: redFour:nand2_sy{sch} -.SUBCKT nand2_sy-X_4 ina inb out -XPMOS@0 out inb vdd PMOSx-X_4 -XPMOS@1 out ina vdd PMOSx-X_4 -Xnms2_sy@0 out ina inb nms2_sy-X_4 -.ENDS nand2_sy-X_4 +*** CELL: redFive:nor2{sch} +.SUBCKT nor2-X_10 ina inb out +XNMOS@0 out ina gnd NMOSx-X_10 +XNMOS@1 out inb gnd NMOSx-X_10 +Xpms2@0 out ina inb pms2-X_10 +.ENDS nor2-X_10 -*** CELL: redFour:nms2_sy{sch} -.SUBCKT nms2_sy-X_10 d g g2 -Xnms2@0 d g g2 nms2-X_5 -Xnms2@1 d g2 g nms2-X_5 -.ENDS nms2_sy-X_10 +*** CELL: redFive:nor2n{sch} +.SUBCKT nor2n-X_10 ina inb out +Xnor2@0 ina inb out nor2-X_10 +.ENDS nor2n-X_10 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-210_3-R_34_667m a b -Ccap@0 gnd net@14 0.771f -Ccap@1 gnd net@8 0.771f -Ccap@2 gnd net@11 0.771f -Rres@0 net@14 a 1.215 -Rres@1 net@11 net@14 2.43 -Rres@2 b net@8 1.215 -Rres@3 net@8 net@11 2.43 -.ENDS wire-C_0_011f-210_3-R_34_667m +.SUBCKT wire-C_0_011f-1001_8-R_34_667m a b +Ccap@0 gnd net@14 3.673f +Ccap@1 gnd net@8 3.673f +Ccap@2 gnd net@11 3.673f +Rres@0 net@14 a 5.788 +Rres@1 net@11 net@14 11.576 +Rres@2 b net@8 5.788 +Rres@3 net@8 net@11 11.576 +.ENDS wire-C_0_011f-1001_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-210_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-210_3-R_34_667m -.ENDS wire90-210_3-layer_1-width_3 +.SUBCKT wire90-1001_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1001_8-R_34_667m +.ENDS wire90-1001_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-353_2-R_34_667m a b -Ccap@0 gnd net@14 1.295f -Ccap@1 gnd net@8 1.295f -Ccap@2 gnd net@11 1.295f -Rres@0 net@14 a 2.041 -Rres@1 net@11 net@14 4.081 -Rres@2 b net@8 2.041 -Rres@3 net@8 net@11 4.081 -.ENDS wire-C_0_011f-353_2-R_34_667m +.SUBCKT wire-C_0_011f-209-R_34_667m a b +Ccap@0 gnd net@14 0.766f +Ccap@1 gnd net@8 0.766f +Ccap@2 gnd net@11 0.766f +Rres@0 net@14 a 1.208 +Rres@1 net@11 net@14 2.415 +Rres@2 b net@8 1.208 +Rres@3 net@8 net@11 2.415 +.ENDS wire-C_0_011f-209-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-353_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-353_2-R_34_667m -.ENDS wire90-353_2-layer_1-width_3 - -*** CELL: latchesK:rsLatchC{sch} -.SUBCKT rsLatchC mc out outBar resetA resetB setA setB -XNMOSx@1 net@188 mc gnd NMOSx-X_4 -XPMOSx@3 net@188 net@177 vdd PMOSx-X_10 -XPMOSx@4 net@274 resetA vdd PMOSx-X_5 -XPMOSx@5 net@274 resetB vdd PMOSx-X_5 -XPMOSx@6 net@226 outBar net@273 PMOSx-X_5 -XPMOSx@7 net@273 mc net@274 PMOSx-X_5 -Xinv@0 net@226 outBar inv-X_20 -Xinv@2 outBar out inv-X_20 -Xnand2_sy@0 setA setB net@267 nand2_sy-X_4 -Xnms2@1 net@188 outBar net@177 nms2-X_2 -Xnms2_sy@0 net@226 resetB resetA nms2_sy-X_10 -Xwire90@0 net@267 net@177 wire90-210_3-layer_1-width_3 -Xwire90@1 net@188 net@226 wire90-353_2-layer_1-width_3 -.ENDS rsLatchC +.SUBCKT wire90-209-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-209-R_34_667m +.ENDS wire90-209-layer_1-width_3 -*** CELL: driversL:sucDri20plain{sch} -.SUBCKT sucDri20plain in succ -XPMOSx@0 succ in vdd PMOSx-X_20 -Xinv@1 succ net@94 inv-X_4 -Xnms2@0 succ net@127 in nms2-X_2 -Xwire90@0 net@127 net@94 wire90-124_7-layer_1-width_3 -.ENDS sucDri20plain +*** CELL: driversL:sucORdri20{sch} +.SUBCKT sucORdri20 inA inB succ +XPMOSx@0 succ net@51 vdd PMOSx-X_20 +Xinv@0 succ net@71 inv-X_4 +Xnms2@0 succ net@73 net@51 nms2-X_2 +Xnor2_sy@0 inA inB net@67 nor2_sy-X_5 +Xwire90@0 net@67 net@51 wire90-1001_8-layer_1-width_3 +Xwire90@1 net@73 net@71 wire90-209-layer_1-width_3 +.ENDS sucORdri20 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-314_7-R_34_667m a b -Ccap@0 gnd net@14 1.154f -Ccap@1 gnd net@8 1.154f -Ccap@2 gnd net@11 1.154f -Rres@0 net@14 a 1.818 -Rres@1 net@11 net@14 3.637 -Rres@2 b net@8 1.818 -Rres@3 net@8 net@11 3.637 -.ENDS wire-C_0_011f-314_7-R_34_667m +.SUBCKT wire-C_0_011f-286_3-R_34_667m a b +Ccap@0 gnd net@14 1.05f +Ccap@1 gnd net@8 1.05f +Ccap@2 gnd net@11 1.05f +Rres@0 net@14 a 1.654 +Rres@1 net@11 net@14 3.308 +Rres@2 b net@8 1.654 +Rres@3 net@8 net@11 3.308 +.ENDS wire-C_0_011f-286_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-314_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-314_7-R_34_667m -.ENDS wire90-314_7-layer_1-width_3 +.SUBCKT wire90-286_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-286_3-R_34_667m +.ENDS wire90-286_3-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1526_5-R_34_667m a b -Ccap@0 gnd net@14 5.597f -Ccap@1 gnd net@8 5.597f -Ccap@2 gnd net@11 5.597f -Rres@0 net@14 a 8.82 -Rres@1 net@11 net@14 17.64 -Rres@2 b net@8 8.82 -Rres@3 net@8 net@11 17.64 -.ENDS wire-C_0_011f-1526_5-R_34_667m +.SUBCKT wire-C_0_011f-428_8-R_34_667m a b +Ccap@0 gnd net@14 1.572f +Ccap@1 gnd net@8 1.572f +Ccap@2 gnd net@11 1.572f +Rres@0 net@14 a 2.478 +Rres@1 net@11 net@14 4.955 +Rres@2 b net@8 2.478 +Rres@3 net@8 net@11 4.955 +.ENDS wire-C_0_011f-428_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1526_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1526_5-R_34_667m -.ENDS wire90-1526_5-layer_1-width_3 +.SUBCKT wire90-428_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-428_8-R_34_667m +.ENDS wire90-428_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1328_7-R_34_667m a b -Ccap@0 gnd net@14 4.872f -Ccap@1 gnd net@8 4.872f -Ccap@2 gnd net@11 4.872f -Rres@0 net@14 a 7.677 -Rres@1 net@11 net@14 15.354 -Rres@2 b net@8 7.677 -Rres@3 net@8 net@11 15.354 -.ENDS wire-C_0_011f-1328_7-R_34_667m +.SUBCKT wire-C_0_011f-356_7-R_34_667m a b +Ccap@0 gnd net@14 1.308f +Ccap@1 gnd net@8 1.308f +Ccap@2 gnd net@11 1.308f +Rres@0 net@14 a 2.061 +Rres@1 net@11 net@14 4.122 +Rres@2 b net@8 2.061 +Rres@3 net@8 net@11 4.122 +.ENDS wire-C_0_011f-356_7-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1328_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1328_7-R_34_667m -.ENDS wire90-1328_7-layer_1-width_3 +.SUBCKT wire90-356_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-356_7-R_34_667m +.ENDS wire90-356_7-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-234_9-R_34_667m a b -Ccap@0 gnd net@14 0.861f -Ccap@1 gnd net@8 0.861f -Ccap@2 gnd net@11 0.861f -Rres@0 net@14 a 1.357 -Rres@1 net@11 net@14 2.714 -Rres@2 b net@8 1.357 -Rres@3 net@8 net@11 2.714 -.ENDS wire-C_0_011f-234_9-R_34_667m +.SUBCKT wire-C_0_011f-199_1-R_34_667m a b +Ccap@0 gnd net@14 0.73f +Ccap@1 gnd net@8 0.73f +Ccap@2 gnd net@11 0.73f +Rres@0 net@14 a 1.15 +Rres@1 net@11 net@14 2.301 +Rres@2 b net@8 1.15 +Rres@3 net@8 net@11 2.301 +.ENDS wire-C_0_011f-199_1-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-234_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-234_9-R_34_667m -.ENDS wire90-234_9-layer_1-width_3 +.SUBCKT wire90-199_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-199_1-R_34_667m +.ENDS wire90-199_1-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1122_1-R_34_667m a b -Ccap@0 gnd net@14 4.114f -Ccap@1 gnd net@8 4.114f -Ccap@2 gnd net@11 4.114f -Rres@0 net@14 a 6.483 -Rres@1 net@11 net@14 12.966 -Rres@2 b net@8 6.483 -Rres@3 net@8 net@11 12.966 -.ENDS wire-C_0_011f-1122_1-R_34_667m +.SUBCKT wire-C_0_011f-702_4-R_34_667m a b +Ccap@0 gnd net@14 2.575f +Ccap@1 gnd net@8 2.575f +Ccap@2 gnd net@11 2.575f +Rres@0 net@14 a 4.058 +Rres@1 net@11 net@14 8.117 +Rres@2 b net@8 4.058 +Rres@3 net@8 net@11 8.117 +.ENDS wire-C_0_011f-702_4-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1122_1-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1122_1-R_34_667m -.ENDS wire90-1122_1-layer_1-width_3 +.SUBCKT wire90-702_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-702_4-R_34_667m +.ENDS wire90-702_4-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-820_7-R_34_667m a b -Ccap@0 gnd net@14 3.009f -Ccap@1 gnd net@8 3.009f -Ccap@2 gnd net@11 3.009f -Rres@0 net@14 a 4.742 -Rres@1 net@11 net@14 9.484 -Rres@2 b net@8 4.742 -Rres@3 net@8 net@11 9.484 -.ENDS wire-C_0_011f-820_7-R_34_667m +.SUBCKT wire-C_0_011f-251_7-R_34_667m a b +Ccap@0 gnd net@14 0.923f +Ccap@1 gnd net@8 0.923f +Ccap@2 gnd net@11 0.923f +Rres@0 net@14 a 1.454 +Rres@1 net@11 net@14 2.909 +Rres@2 b net@8 1.454 +Rres@3 net@8 net@11 2.909 +.ENDS wire-C_0_011f-251_7-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-820_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-820_7-R_34_667m -.ENDS wire90-820_7-layer_1-width_3 +.SUBCKT wire90-251_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-251_7-R_34_667m +.ENDS wire90-251_7-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-228_4-R_34_667m a b -Ccap@0 gnd net@14 0.837f -Ccap@1 gnd net@8 0.837f -Ccap@2 gnd net@11 0.837f -Rres@0 net@14 a 1.32 -Rres@1 net@11 net@14 2.639 -Rres@2 b net@8 1.32 -Rres@3 net@8 net@11 2.639 -.ENDS wire-C_0_011f-228_4-R_34_667m +.SUBCKT wire-C_0_011f-377-R_34_667m a b +Ccap@0 gnd net@14 1.382f +Ccap@1 gnd net@8 1.382f +Ccap@2 gnd net@11 1.382f +Rres@0 net@14 a 2.178 +Rres@1 net@11 net@14 4.356 +Rres@2 b net@8 2.178 +Rres@3 net@8 net@11 4.356 +.ENDS wire-C_0_011f-377-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-228_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-228_4-R_34_667m -.ENDS wire90-228_4-layer_1-width_3 +.SUBCKT wire90-377-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-377-R_34_667m +.ENDS wire90-377-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-707_6-R_34_667m a b -Ccap@0 gnd net@14 2.595f -Ccap@1 gnd net@8 2.595f -Ccap@2 gnd net@11 2.595f -Rres@0 net@14 a 4.088 -Rres@1 net@11 net@14 8.177 -Rres@2 b net@8 4.088 -Rres@3 net@8 net@11 8.177 -.ENDS wire-C_0_011f-707_6-R_34_667m +.SUBCKT wire-C_0_011f-593_4-R_34_667m a b +Ccap@0 gnd net@14 2.176f +Ccap@1 gnd net@8 2.176f +Ccap@2 gnd net@11 2.176f +Rres@0 net@14 a 3.429 +Rres@1 net@11 net@14 6.857 +Rres@2 b net@8 3.429 +Rres@3 net@8 net@11 6.857 +.ENDS wire-C_0_011f-593_4-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-707_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-707_6-R_34_667m -.ENDS wire90-707_6-layer_1-width_3 +.SUBCKT wire90-593_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-593_4-R_34_667m +.ENDS wire90-593_4-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-812_8-R_34_667m a b -Ccap@0 gnd net@14 2.98f -Ccap@1 gnd net@8 2.98f -Ccap@2 gnd net@11 2.98f -Rres@0 net@14 a 4.696 -Rres@1 net@11 net@14 9.392 -Rres@2 b net@8 4.696 -Rres@3 net@8 net@11 9.392 -.ENDS wire-C_0_011f-812_8-R_34_667m +.SUBCKT wire-C_0_011f-1158_7-R_34_667m a b +Ccap@0 gnd net@14 4.249f +Ccap@1 gnd net@8 4.249f +Ccap@2 gnd net@11 4.249f +Rres@0 net@14 a 6.695 +Rres@1 net@11 net@14 13.389 +Rres@2 b net@8 6.695 +Rres@3 net@8 net@11 13.389 +.ENDS wire-C_0_011f-1158_7-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-812_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-812_8-R_34_667m -.ENDS wire90-812_8-layer_1-width_3 +.SUBCKT wire90-1158_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1158_7-R_34_667m +.ENDS wire90-1158_7-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-428_6-R_34_667m a b -Ccap@0 gnd net@14 1.572f -Ccap@1 gnd net@8 1.572f -Ccap@2 gnd net@11 1.572f -Rres@0 net@14 a 2.476 -Rres@1 net@11 net@14 4.953 -Rres@2 b net@8 2.476 -Rres@3 net@8 net@11 4.953 -.ENDS wire-C_0_011f-428_6-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-428_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-428_6-R_34_667m -.ENDS wire90-428_6-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-672_2-R_34_667m a b -Ccap@0 gnd net@14 2.465f -Ccap@1 gnd net@8 2.465f -Ccap@2 gnd net@11 2.465f -Rres@0 net@14 a 3.884 -Rres@1 net@11 net@14 7.768 -Rres@2 b net@8 3.884 -Rres@3 net@8 net@11 7.768 -.ENDS wire-C_0_011f-672_2-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-672_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-672_2-R_34_667m -.ENDS wire90-672_2-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-495_5-R_34_667m a b -Ccap@0 gnd net@14 1.817f -Ccap@1 gnd net@8 1.817f -Ccap@2 gnd net@11 1.817f -Rres@0 net@14 a 2.863 -Rres@1 net@11 net@14 5.726 -Rres@2 b net@8 2.863 -Rres@3 net@8 net@11 5.726 -.ENDS wire-C_0_011f-495_5-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-495_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-495_5-R_34_667m -.ENDS wire90-495_5-layer_1-width_3 - -*** CELL: gaspL:rqStage{sch} -.SUBCKT rqStage do[RQ] do[epi] do[ring] in[RQ] in[Z] mc s[1] s[2] s[3] s[4] -+tail take[E] take[R] -XandOrInv@0 nzrq fire[R] fire[E] tailBAR net@239 andOrInv5 -XctrAND2i@0 net@324 net@129 fireB ctrAND2in30 -XctrAND3i@0 net@8 do[ring] net@124 fire[E] ctrAND3in30 -XctrAND4i@1 do[ring] net@205 net@193 net@197 fire[R] ctrAND4in30 -Xinv@12 do[epi] net@7 inv-X_5 -Xinv@13 net@8 s[1] inv-X_5 -Xinv@14 net@197 s[2] inv-X_5 -Xinv@15 net@193 s[4] inv-X_5 -Xinv@16 net@205 s[3] inv-X_5 -Xinv@17 do[RQ] net@324 inv-X_10 -Xinv@18 tail net@305 inv-X_10 -XlatchDri@0 fire[R] take[R] latchDriver60 -XlatchDri@1 fire[E] take[E] latchDriver60 -Xnor2_sy@1 in[Z] in[RQ] net@287 nor2_sy-X_10 -XpredDri2@0 net@121 mc do[epi] predDri20wMC -XpredORdr@0 net@142 net@139 mc do[RQ] predORdri20wMC -XrsLatchC@0 mc net@105 filling fire[R] in[Z] fire[E] tail rsLatchC -XrsLatchC@1 mc net@40 draining fire[R] in[Z] fireB nzrq rsLatchC -XsucDri20@1 net@240 do[ring] sucDri20plain -Xwire90@0 net@7 net@8 wire90-314_7-layer_1-width_3 -Xwire90@2 net@142 fire[R] wire90-1526_5-layer_1-width_3 -Xwire90@3 net@121 fire[E] wire90-1328_7-layer_1-width_3 -Xwire90@4 net@124 net@105 wire90-234_9-layer_1-width_3 -Xwire90@5 filling net@197 wire90-1122_1-layer_1-width_3 -Xwire90@6 draining net@193 wire90-820_7-layer_1-width_3 -Xwire90@7 net@129 net@40 wire90-228_4-layer_1-width_3 -Xwire90@8 net@324 net@205 wire90-707_6-layer_1-width_3 -Xwire90@9 net@139 fireB wire90-812_8-layer_1-width_3 -Xwire90@14 net@239 net@240 wire90-428_6-layer_1-width_3 -Xwire90@17 nzrq net@287 wire90-672_2-layer_1-width_3 -Xwire90@18 net@305 tailBAR wire90-495_5-layer_1-width_3 -.ENDS rqStage +.SUBCKT wire-C_0_011f-487_9-R_34_667m a b +Ccap@0 gnd net@14 1.789f +Ccap@1 gnd net@8 1.789f +Ccap@2 gnd net@11 1.789f +Rres@0 net@14 a 2.819 +Rres@1 net@11 net@14 5.638 +Rres@2 b net@8 2.819 +Rres@3 net@8 net@11 5.638 +.ENDS wire-C_0_011f-487_9-R_34_667m -*** CELL: scanJ:scanEx3hor{sch} -.SUBCKT scanEx3hor dIn[1] dIn[2] dIn[3] mc sir[1] sir[2] sir[3] sir[4] sir[5] -+sir[6] sir[7] sir[8] sor[1] -XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanCellE -XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanCellE -XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sor[1] scanCellE +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-487_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-487_9-R_34_667m +.ENDS wire90-487_9-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-214_3-R_34_667m a b +Ccap@0 gnd net@14 0.786f +Ccap@1 gnd net@8 0.786f +Ccap@2 gnd net@11 0.786f +Rres@0 net@14 a 1.238 +Rres@1 net@11 net@14 2.476 +Rres@2 b net@8 1.238 +Rres@3 net@8 net@11 2.476 +.ENDS wire-C_0_011f-214_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-214_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-214_3-R_34_667m +.ENDS wire90-214_3-layer_1-width_3 + +*** CELL: oneHotM:reQueueC{sch} +.SUBCKT reQueueC circulate epi[OTHER] fire[E] fire[R] mc od[ABORT] od[OTHER] ++ps[do] ps[skip] s[1] s[2] succ +XctrAND3i@0 succ net@361 circulate fire[E] ctrAND3in30 +Xinv@12 net@377 abortLO inv-X_10 +Xinv@13 epi[OTHER] net@440 inv-X_5 +Xinv@14 circulate net@320 inv-X_10 +XinvI@10 net@309 net@376 inv-X_5 +XinvI@11 net@394 net@396 inv-X_10 +XinvI@12 net@440 s[2] inv-X_10 +XinvI@13 net@320 s[1] inv-X_10 +Xnand2_sy@1 od[OTHER] ps[skip] net@274 nand2_sy-X_6 +Xnand2_sy@2 od[ABORT] ps[skip] net@277 nand2_sy-X_6 +Xnand2_sy@3 od[OTHER] ps[do] net@280 nand2_sy-X_6 +Xnand2_sy@4 od[ABORT] ps[do] net@283 nand2_sy-X_6 +Xnand2_sy@5 net@313 net@311 net@324 nand2_sy-X_6 +Xnand2n@0 circulate succ net@315 nand2n-X_5 +Xnand2n_s@0 net@324 abortLO fire[C] nand2n_sy-X_20 +Xnand3in6@1 net@303 net@418 net@306 net@420 nand3in6_6sym +Xnor2n@1 net@326 net@322 fire[R] nor2n-X_10 +XpredDri2@2 net@243 mc od[ABORT] predDri20wMC +XpredDri2@3 net@243 mc od[OTHER] predDri20wMC +XpredDri2@4 net@243 mc ps[do] predDri20wMC +XpredDri2@5 net@243 mc ps[skip] predDri20wMC +XpredDri2@6 fire[E] mc epi[OTHER] predDri20wMC +XpredDri2@7 net@399 mc circulate predDri20wMC +XsucORdri@0 fire[R] fire[E] succ sucORdri20 +Xwire90@12 net@274 net@303 wire90-286_3-layer_1-width_3 +Xwire90@13 net@277 net@418 wire90-428_8-layer_1-width_3 +Xwire90@14 net@280 net@306 wire90-356_7-layer_1-width_3 +Xwire90@15 net@283 net@309 wire90-199_1-layer_1-width_3 +Xwire90@16 net@420 net@311 wire90-702_4-layer_1-width_3 +Xwire90@17 net@313 net@315 wire90-251_7-layer_1-width_3 +Xwire90@18 net@322 net@320 wire90-377-layer_1-width_3 +Xwire90@19 net@324 net@326 wire90-593_4-layer_1-width_3 +Xwire90@20 net@243 fire[C] wire90-1158_7-layer_1-width_3 +Xwire90@23 net@376 net@377 wire90-142_6-layer_1-width_3 +Xwire90@24 abortLO net@394 wire90-487_9-layer_1-width_3 +Xwire90@25 net@396 net@399 wire90-214_3-layer_1-width_3 +Xwire90@27 net@361 net@440 wire90-142_6-layer_1-width_3 +.ENDS reQueueC + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1041_2-R_34_667m a b +Ccap@0 gnd net@14 3.818f +Ccap@1 gnd net@8 3.818f +Ccap@2 gnd net@11 3.818f +Rres@0 net@14 a 6.016 +Rres@1 net@11 net@14 12.032 +Rres@2 b net@8 6.016 +Rres@3 net@8 net@11 12.032 +.ENDS wire-C_0_011f-1041_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1041_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1041_2-R_34_667m +.ENDS wire90-1041_2-layer_1-width_3 + +*** CELL: oneHotM:reQueue{sch} +.SUBCKT reQueue epi[OTHER] epi[TAIL] fire[E] fire[R] mc od[ABORT] od[HEAD] ++od[OTHER] ps[do] ps[skip] s[1] s[2] s[3] s[4] succ +XreQueueB@1 circulate epi[TAIL] mc od[HEAD] s[1] s[2] reQueueB +XreQueueC@0 net@3 epi[OTHER] fire[E] fire[R] mc od[ABORT] od[OTHER] ps[do] ++ps[skip] s[3] s[4] succ reQueueC +Xwire90@0 circulate net@3 wire90-1041_2-layer_1-width_3 +.ENDS reQueue + +*** CELL: scanM:scanEx3plain{sch} +.SUBCKT scanEx3plain dIn[1] dIn[2] dIn[3] sin sir[2] sir[3] sir[5] sout +XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sin net@26 scanM__scanCellE +XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanM__scanCellE +XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sout scanM__scanCellE Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3 Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3 -.ENDS scanEx3hor +.ENDS scanEx3plain -*** CELL: registersL:short2in20Ax18{sch} -.SUBCKT short2in20Ax18 hcl[A][1] hcl[B][1] inA[10] inA[11] inA[12] inA[13] -+inA[14] inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] -+inA[6] inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] -+inB[16] inB[17] inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] -+inB[8] inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] -+out[18] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] -Xlx[1] hcl[A][1] hcl[B][1] inA[1] inB[1] out[1] latch2in20A -Xlx[2] hcl[A][1] hcl[B][1] inA[2] inB[2] out[2] latch2in20A -Xlx[3] hcl[A][1] hcl[B][1] inA[3] inB[3] out[3] latch2in20A -Xlx[4] hcl[A][1] hcl[B][1] inA[4] inB[4] out[4] latch2in20A -Xlx[5] hcl[A][1] hcl[B][1] inA[5] inB[5] out[5] latch2in20A -Xlx[6] hcl[A][1] hcl[B][1] inA[6] inB[6] out[6] latch2in20A -Xlx[7] hcl[A][1] hcl[B][1] inA[7] inB[7] out[7] latch2in20A -Xlx[8] hcl[A][1] hcl[B][1] inA[8] inB[8] out[8] latch2in20A -Xlx[9] hcl[A][1] hcl[B][1] inA[9] inB[9] out[9] latch2in20A -Xlx[10] hcl[A][1] hcl[B][1] inA[10] inB[10] out[10] latch2in20A -Xlx[11] hcl[A][1] hcl[B][1] inA[11] inB[11] out[11] latch2in20A -Xlx[12] hcl[A][1] hcl[B][1] inA[12] inB[12] out[12] latch2in20A -Xlx[13] hcl[A][1] hcl[B][1] inA[13] inB[13] out[13] latch2in20A -Xlx[14] hcl[A][1] hcl[B][1] inA[14] inB[14] out[14] latch2in20A -Xlx[15] hcl[A][1] hcl[B][1] inA[15] inB[15] out[15] latch2in20A -Xlx[16] hcl[A][1] hcl[B][1] inA[16] inB[16] out[16] latch2in20A -Xlx[17] hcl[A][1] hcl[B][1] inA[17] inB[17] out[17] latch2in20A -Xlx[18] hcl[A][1] hcl[B][1] inA[18] inB[18] out[18] latch2in20A -.ENDS short2in20Ax18 - -*** CELL: registersL:short2in20Ax36{sch} -.SUBCKT short2in20Ax36 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] -+inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] -+inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] -+inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7] -+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17] -+inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25] -+inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33] -+inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9] -+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] -+out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] -+out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] -+out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] take[A] -+take[B] -Xshort2in@0 take[A] take[B] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] -+inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inA[7] -+inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17] -+inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9] -+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] -+out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] short2in20Ax18 -Xshort2in@1 take[A] take[B] inA[28] inA[29] inA[30] inA[31] inA[32] inA[33] -+inA[34] inA[35] inA[36] inA[19] inA[20] inA[21] inA[22] inA[23] inA[24] -+inA[25] inA[26] inA[27] inB[28] inB[29] inB[30] inB[31] inB[32] inB[33] -+inB[34] inB[35] inB[36] inB[19] inB[20] inB[21] inB[22] inB[23] inB[24] -+inB[25] inB[26] inB[27] out[28] out[29] out[30] out[31] out[32] out[33] -+out[34] out[35] out[36] out[19] out[20] out[21] out[22] out[23] out[24] -+out[25] out[26] out[27] short2in20Ax18 -.ENDS short2in20Ax36 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1336_2-R_34_667m a b +Ccap@0 gnd net@14 4.899f +Ccap@1 gnd net@8 4.899f +Ccap@2 gnd net@11 4.899f +Rres@0 net@14 a 7.72 +Rres@1 net@11 net@14 15.441 +Rres@2 b net@8 7.72 +Rres@3 net@8 net@11 15.441 +.ENDS wire-C_0_011f-1336_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1336_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1336_2-R_34_667m +.ENDS wire90-1336_2-layer_1-width_3 -*** CELL: stepsM:reQstep{sch} -.SUBCKT reQstep do[RQ] do[epi] do[ring] inE[10] inE[11] inE[12] inE[13] +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1307-R_34_667m a b +Ccap@0 gnd net@14 4.792f +Ccap@1 gnd net@8 4.792f +Ccap@2 gnd net@11 4.792f +Rres@0 net@14 a 7.552 +Rres@1 net@11 net@14 15.103 +Rres@2 b net@8 7.552 +Rres@3 net@8 net@11 15.103 +.ENDS wire-C_0_011f-1307-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1307-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1307-R_34_667m +.ENDS wire90-1307-layer_1-width_3 + +*** CELL: stagesM:rqDockStage{sch} +.SUBCKT rqDockStage epi[OTHER] epi[TAIL] inE[10] inE[11] inE[12] inE[13] +inE[14] inE[15] inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] +inE[22] inE[23] inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] +inE[30] inE[31] inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] -+inE[6] inE[7] inE[8] inE[9] inR[10] inR[11] inR[12] inR[13] inR[14] inR[15] -+inR[16] inR[17] inR[18] inR[19] inR[1] inR[20] inR[21] inR[22] inR[23] -+inR[24] inR[25] inR[26] inR[27] inR[28] inR[29] inR[2] inR[30] inR[31] -+inR[32] inR[33] inR[34] inR[35] inR[36] inR[3] inR[4] inR[5] inR[6] inR[7] -+inR[8] inR[9] mc out[10] out[11] out[12] out[13] out[14] out[15] out[16] -+out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] -+out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] -+out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] -+out[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] -XrqStage@0 do[RQ] do[epi] do[ring] inR[30] inR[21] mc s[1] s[2] s[3] s[4] -+inE[21] take[E] take[R] rqStage -XscanEx1v@0 s[4] sir[9] net@47[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertA -XscanEx3h@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] net@47[8] scanEx3hor -Xshort2in@0 inR[10] inR[11] inR[12] inR[13] inR[14] inR[15] inR[16] inR[17] -+inR[18] inR[19] inR[1] inR[20] inR[21] inR[22] inR[23] inR[24] inR[25] -+inR[26] inR[27] inR[28] inR[29] inR[2] inR[30] inR[31] inR[32] inR[33] -+inR[34] inR[35] inR[36] inR[3] inR[4] inR[5] inR[6] inR[7] inR[8] inR[9] -+inE[10] inE[11] inE[12] inE[13] inE[14] inE[15] inE[16] inE[17] inE[18] -+inE[19] inE[1] inE[20] inE[21] inE[22] inE[23] inE[24] inE[25] inE[26] -+inE[27] inE[28] inE[29] inE[2] inE[30] inE[31] inE[32] inE[33] inE[34] -+inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] inE[7] inE[8] inE[9] out[10] -+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] -+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] -+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] -+out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] net@20 net@19 -+short2in20Ax36 -Xwire90@2 take[R] net@20 wire90-242_1-layer_1-width_3 -Xwire90@3 take[E] net@19 wire90-242_1-layer_1-width_3 -.ENDS reQstep ++inE[6] inE[7] inE[8] inE[9] inP[10] inP[11] inP[12] inP[13] inP[14] inP[15] ++inP[16] inP[17] inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23] ++inP[24] inP[25] inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31] ++inP[32] inP[33] inP[34] inP[35] inP[36] inP[3] inP[4] inP[5] inP[6] inP[7] ++inP[8] inP[9] od[ABORT] od[HEAD] od[OTHER] ps[do] ps[skip] rq[10] rq[11] ++rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1] rq[20] rq[21] ++rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] rq[30] rq[31] ++rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] rq[9] ++sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ ++take[E] take[P] +Xins2in20@0 take[E] take[P] inE[10] inE[11] inE[12] inE[13] inE[14] inE[15] ++inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] inE[22] inE[23] ++inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] inE[30] inE[31] ++inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] inE[7] ++inE[8] inE[9] inP[10] inP[11] inP[12] inP[13] inP[14] inP[15] inP[16] inP[17] ++inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23] inP[24] inP[25] ++inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31] inP[32] inP[33] ++inP[34] inP[35] inP[36] inP[3] inP[4] inP[5] inP[6] inP[7] inP[8] inP[9] ++rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1] ++rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] ++rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] ++rq[7] rq[8] rq[9] ins2in20Ax36 +XlatchDri@0 net@3 take[E] latchDriver60 +XlatchDri@1 net@7 take[P] latchDriver60 +XreQueue@0 epi[OTHER] epi[TAIL] fire[E] fire[R] sir[9] od[ABORT] od[HEAD] ++od[OTHER] ps[do] ps[skip] s[1] s[2] s[3] s[4] succ reQueue +XscanEx1v@0 s[1] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sin scanEx1vertA +XscanEx3p@1 s[2] s[3] s[4] sin sir[2] sir[3] sir[5] sor[1] scanEx3plain +Xwire90@0 net@7 fire[R] wire90-1336_2-layer_1-width_3 +Xwire90@1 net@3 fire[E] wire90-1307-layer_1-width_3 +.ENDS rqDockStage + +*** CELL: stageGroupsM:epiRQod{sch} +.SUBCKT epiRQod do[epi] do[od] epi[TORP] flag[A][clr] flag[A][set] ++flag[D][clr] flag[D][set] in[10] in[11] in[12] in[13] in[14] in[15] in[16] ++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] ++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] ++in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] m1[10] m1[11] m1[12] m1[13] ++m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] ++m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] ++m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ps[do] ++ps[skip] rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] ++rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] ++rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] ++rq[5] rq[6] rq[7] rq[8] rq[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sir[9] sor[1] succ +XepiDockS@0 do[epi] net@45[26] net@45[25] net@45[24] net@45[23] net@45[22] ++net@45[21] net@45[20] net@45[19] net@45[18] net@45[17] net@45[35] net@45[16] ++net@45[15] net@45[14] net@45[13] net@45[12] net@45[11] net@45[10] net@45[9] ++net@45[8] net@45[7] net@45[34] net@45[6] net@45[5] net@45[4] net@45[3] ++net@45[2] net@45[1] net@45[0] net@45[33] net@45[32] net@45[31] net@45[30] ++net@45[29] net@45[28] net@45[27] net@44[0] net@44[1] epi[TORP] in[10] in[11] ++in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] ++in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] ++in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] ++in[T] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@0[8] ++take[epi] epiDockStage +XonDeckDo@0 do[od] flag[A][clr] flag[A][set] flag[D][clr] flag[D][set] m1[10] ++m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] ++m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] ++m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] ++m1[9] net@46[26] net@46[25] net@46[24] net@46[23] net@46[22] net@46[21] ++net@46[20] net@46[19] net@46[18] net@46[17] net@46[35] net@46[16] net@46[15] ++net@46[14] net@46[13] net@46[12] net@46[11] net@46[10] net@46[9] net@46[8] ++net@46[7] net@46[34] net@46[6] net@46[5] net@46[4] net@46[3] net@46[2] ++net@46[1] net@46[0] net@46[33] net@46[32] net@46[31] net@46[30] net@46[29] ++net@46[28] net@46[27] od[ABORT] od[HEAD] od[OTHER] net@36[8] sir[2] sir[3] ++sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] take[od] onDeckDockStage +XrqDockSt@0 net@44[0] net@44[1] net@45[26] net@45[25] net@45[24] net@45[23] ++net@45[22] net@45[21] net@45[20] net@45[19] net@45[18] net@45[17] net@45[35] ++net@45[16] net@45[15] net@45[14] net@45[13] net@45[12] net@45[11] net@45[10] ++net@45[9] net@45[8] net@45[7] net@45[34] net@45[6] net@45[5] net@45[4] ++net@45[3] net@45[2] net@45[1] net@45[0] net@45[33] net@45[32] net@45[31] ++net@45[30] net@45[29] net@45[28] net@45[27] net@46[26] net@46[25] net@46[24] ++net@46[23] net@46[22] net@46[21] net@46[20] net@46[19] net@46[18] net@46[17] ++net@46[35] net@46[16] net@46[15] net@46[14] net@46[13] net@46[12] net@46[11] ++net@46[10] net@46[9] net@46[8] net@46[7] net@46[34] net@46[6] net@46[5] ++net@46[4] net@46[3] net@46[2] net@46[1] net@46[0] net@46[33] net@46[32] ++net@46[31] net@46[30] net@46[29] net@46[28] net@46[27] od[ABORT] od[HEAD] ++od[OTHER] ps[do] ps[skip] rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] ++rq[17] rq[18] rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] ++rq[27] rq[28] rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] ++rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] rq[9] net@0[8] sir[2] sir[3] sir[4] ++sir[5] sir[6] sir[7] sir[8] sir[9] net@36[8] succ take[E] take[P] rqDockStage +.ENDS epiRQod + +*** CELL: orangeTSMC090nm:PMOSx{sch} +.SUBCKT PMOSx-X_40 d g s +MPMOSf@0 d g s vdd pch W='240*(1+ABP/sqrt(240*2))' L='2' ++DELVTO='AVT0P/sqrt(240*2)' +.ENDS PMOSx-X_40 + +*** CELL: redFive:pms2{sch} +.SUBCKT pms2-X_20 d g g2 +XPMOS@0 net@2 g vdd PMOSx-X_40 +XPMOS@1 d g2 net@2 PMOSx-X_40 +.ENDS pms2-X_20 + +*** CELL: redFive:nor2{sch} +.SUBCKT nor2-X_20 ina inb out +XNMOS@0 out ina gnd NMOSx-X_20 +XNMOS@1 out inb gnd NMOSx-X_20 +Xpms2@0 out ina inb pms2-X_20 +.ENDS nor2-X_20 + +*** CELL: redFive:nor2n{sch} +.SUBCKT nor2n-X_20 ina inb out +Xnor2@0 ina inb out nor2-X_20 +.ENDS nor2n-X_20 + +*** CELL: orangeTSMC090nm:PMOSx{sch} +.SUBCKT PMOSx-X_2 d g s +MPMOSf@0 d g s vdd pch W='12*(1+ABP/sqrt(12*2))' L='2' ++DELVTO='AVT0P/sqrt(12*2)' +.ENDS PMOSx-X_2 + +*** CELL: redFive:nand2{sch} +.SUBCKT nand2-X_2 ina inb out +XPMOS@0 out ina vdd PMOSx-X_2 +XPMOS@1 out inb vdd PMOSx-X_2 +Xnms2@0 out ina inb nms2-X_2 +.ENDS nand2-X_2 + +*** CELL: redFive:nms1{sch} +.SUBCKT nms1-X_4 d g +XNMOS@1 d g gnd NMOSx-X_4 +.ENDS nms1-X_4 + +*** CELL: redFive:pms1{sch} +.SUBCKT pms1-X_10 d g +XPMOS@0 d g vdd PMOSx-X_10 +.ENDS pms1-X_10 + +*** CELL: redFive:pms2{sch} +.SUBCKT pms2-X_5 d g g2 +XPMOS@0 net@2 g vdd PMOSx-X_10 +XPMOS@1 d g2 net@2 PMOSx-X_10 +.ENDS pms2-X_5 + +*** CELL: redFive:pms2_sy{sch} +.SUBCKT pms2_sy-X_10 d g g2 +Xpms2@0 d g g2 pms2-X_5 +Xpms2@1 d g2 g pms2-X_5 +.ENDS pms2_sy-X_10 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-413_4-R_34_667m a b -Ccap@0 gnd net@14 1.516f -Ccap@1 gnd net@8 1.516f -Ccap@2 gnd net@11 1.516f -Rres@0 net@14 a 2.389 -Rres@1 net@11 net@14 4.777 -Rres@2 b net@8 2.389 -Rres@3 net@8 net@11 4.777 -.ENDS wire-C_0_011f-413_4-R_34_667m +.SUBCKT wire-C_0_011f-403-R_34_667m a b +Ccap@0 gnd net@14 1.478f +Ccap@1 gnd net@8 1.478f +Ccap@2 gnd net@11 1.478f +Rres@0 net@14 a 2.328 +Rres@1 net@11 net@14 4.657 +Rres@2 b net@8 2.328 +Rres@3 net@8 net@11 4.657 +.ENDS wire-C_0_011f-403-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-413_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-413_4-R_34_667m -.ENDS wire90-413_4-layer_1-width_3 +.SUBCKT wire90-403-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-403-R_34_667m +.ENDS wire90-403-layer_1-width_3 -*** CELL: gaspL:odStage{sch} -.SUBCKT odStage do[L] do[M] do[RQ] fire[ODE] fire[OD] mc pred s[1] wait[M] -XctrAND4i@0 net@863 do[RQ] do[L] do[M] fire[ODE] ctrAND4in40 -Xinv@0 net@863 s[1] inv-X_10 -Xinv@5 pred net@664 inv-X_5 -Xinv@16 fire[ODE] fire[OD] inv-X_60 -Xinv@17 fire[OD] net@1496 inv-X_5 -Xinv@18 net@1497 net@1498 inv-X_5 -XpredDri2@0 fire[OD] mc pred predDri20wMC -XpredDri2@1 net@1499 mc wait[M] predDri20wMC -XsucDri20@3 fire[OD] do[RQ] sucDri20 -Xwire90@15 net@664 net@863 wire90-413_4-layer_1-width_3 -Xwire90@16 net@1499 net@1498 wire90-413_4-layer_1-width_3 -Xwire90@17 net@1497 net@1496 wire90-413_4-layer_1-width_3 -.ENDS odStage - -*** CELL: stepsM:shortODstep{sch} -.SUBCKT shortODstep do[L] do[M] do[RQ] fire[ODE] in[10] in[11] in[12] in[13] -+in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] -+in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] -+in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc od[10] -+od[11] od[12] od[13] od[14] od[15] od[16] od[17] od[18] od[19] od[1] od[20] -+od[21] od[22] od[23] od[24] od[25] od[26] od[27] od[28] od[29] od[2] od[30] -+od[31] od[32] od[33] od[34] od[35] od[36] od[3] od[4] od[5] od[6] od[7] od[8] -+od[9] olcZ outQ[10] outQ[11] outQ[12] outQ[13] outQ[14] outQ[15] outQ[16] -+outQ[17] outQ[18] outQ[19] outQ[1] outQ[20] outQ[22] outQ[23] outQ[24] -+outQ[25] outQ[26] outQ[27] outQ[28] outQ[29] outQ[2] outQ[30] outQ[31] -+outQ[32] outQ[33] outQ[34] outQ[35] outQ[36] outQ[3] outQ[4] outQ[5] outQ[6] -+outQ[7] outQ[8] outQ[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sir[9] sor[1] wait[M] -XlatchDri@0 net@15 take[1] latchDriver60 -XlatchDri@1 net@15 net@76 latchDriver60 -XodStage@0 do[L] do[M] do[RQ] fire[ODE] net@43 mc pred net@87 wait[M] odStage -XscanEx1v@0 net@87 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertA -Xshort20B@0 net@6 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +*** CELL: oneHotM:sucDri10Pair{sch} +.SUBCKT sucDri10Pair bit[1] out[1][F] out[1][T] when +XNMOSx@2 out[1][F] net@105 net@139 NMOSx-X_4 +XNMOSx@3 out[1][F] bit[1] net@144 NMOSx-X_4 +Xinv@2 when net@66 inv-X_4 +Xinv@5 out[1][F] net@92 inv-X_4 +Xinv@6 out[1][T] net@112 inv-X_4 +Xnand2@1 when bit[1] net@64 nand2-X_2 +Xnms1@2 net@139 net@154 nms1-X_4 +Xnms2b@0 out[1][T] net@113 net@4 nms2-X_2 +Xpms1@0 out[1][T] net@4 pms1-X_10 +Xpms2_sy@0 out[1][F] net@105 bit[1] pms2_sy-X_10 +Xwire90@0 net@64 net@4 wire90-403-layer_1-width_3 +Xwire90@1 net@66 net@105 wire90-403-layer_1-width_3 +Xwire90@3 net@113 net@112 wire90-403-layer_1-width_3 +Xwire90@4 net@154 net@92 wire90-403-layer_1-width_3 +Xwire90@5 net@144 net@139 wire90-403-layer_1-width_3 +.ENDS sucDri10Pair + +*** CELL: oneHotM:sucDri10Pairx6{sch} +.SUBCKT sucDri10Pairx6 bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] m1cate[1][F] ++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] ++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] ready when +Xdd[1] bit[1] m1cate[1][F] m1cate[1][T] when sucDri10Pair +Xdd[2] bit[2] m1cate[2][F] m1cate[2][T] when sucDri10Pair +Xdd[3] bit[3] m1cate[3][F] m1cate[3][T] when sucDri10Pair +Xdd[4] bit[4] m1cate[4][F] m1cate[4][T] when sucDri10Pair +Xdd[5] bit[5] m1cate[5][F] m1cate[5][T] when sucDri10Pair +Xdd[6] bit[6] m1cate[6][F] m1cate[6][T] when sucDri10Pair +Xnor2n_sy@0 m1cate[1][T] m1cate[1][F] ready nor2n_sy-X_5 +.ENDS sucDri10Pairx6 + +*** CELL: oneHotM:minusOne{sch} +.SUBCKT minusOne bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] fire[m1] headBit ++m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] ++m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] ++mc pred s[1] succ +Xinv@7 pred net@313 inv-X_5 +XinvI@0 net@235 s[1] inv-X_10 +XinvI@1 net@398 fire[m1] inv-X_10 +Xnand2@1 net@414 net@411 net@398 nand2-X_10 +Xnor2n@0 headBit net@405 net@406 nor2n-X_20 +Xnor2n_sy@1 succ net@235 net@391 nor2n_sy-X_5 +XpredDri2@0 fire[m1] mc pred predDri20wMC +XsucDri10@1 bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] m1cate[1][F] ++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] ++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] net@435 ++net@421 sucDri10Pairx6 +XsucDri20@1 net@407 succ sucDri20 +Xwire90@10 fire[m1] net@407 wire90-403-layer_1-width_3 +Xwire90@11 net@313 net@235 wire90-403-layer_1-width_3 +Xwire90@12 net@414 net@435 wire90-403-layer_1-width_3 +Xwire90@13 net@411 net@391 wire90-403-layer_1-width_3 +Xwire90@14 net@398 net@405 wire90-403-layer_1-width_3 +Xwire90@15 net@406 net@421 wire90-403-layer_1-width_3 +.ENDS minusOne + +*** CELL: stagesM:mOneDockStage{sch} +.SUBCKT mOneDockStage in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] +in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] outQ[10] outQ[11] outQ[12] outQ[13] -+outQ[14] outQ[15] outQ[16] outQ[17] outQ[18] outQ[19] outQ[1] outQ[20] x[21] -+outQ[22] outQ[23] outQ[24] outQ[25] outQ[26] outQ[27] outQ[28] outQ[29] -+outQ[2] outQ[30] outQ[31] outQ[32] outQ[33] outQ[34] outQ[35] outQ[36] -+outQ[3] outQ[4] outQ[5] outQ[6] outQ[7] outQ[8] outQ[9] short20Bx36 -Xshort20B@1 net@78 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[4] in[5] in[6] in[7] in[8] in[9] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] ++m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] ++m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] ++m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] ++m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] ++m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] pred sir[1] sir[2] sir[3] ++sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ take[1] +Xins1in20@0 take[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] +in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] od[10] od[11] od[12] od[13] od[14] od[15] -+od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25] -+od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35] -+od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] short20Bx36 -Xwire90@1 net@6 take[1] wire90-3715_9-layer_1-width_3 -Xwire90@2 net@43 net@15 wire90-3715_9-layer_1-width_3 -Xwire90@3 net@78 net@76 wire90-3715_9-layer_1-width_3 -.ENDS shortODstep ++in[4] in[5] in[6] in[7] in[8] in[9] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] ++m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] ++m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] ++m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ins1in20Bx36 +XlatchDri@0 fire[1] take[1] latchDriver60 +XminusOne@0 in[31] in[32] in[33] in[34] in[35] in[36] net@11 in[30] ++m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] ++m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] ++sir[9] pred net@47 succ minusOne +XscanEx1v@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx1vertA +Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3 +.ENDS mOneDockStage + +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_40 d g s +MNMOSf@0 d g s gnd nch W='120*(1+ABN/sqrt(120*2))' L='2' ++DELVTO='AVT0N/sqrt(120*2)' +.ENDS NMOSx-X_40 + +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_40 in out +XNMOS@0 out in gnd NMOSx-X_40 +XPMOS@0 out in vdd PMOSx-X_40 +.ENDS inv-X_40 + +*** CELL: redFive:nms2{sch} +.SUBCKT nms2-X_15 d g g2 +XNMOS@0 d g2 net@0 NMOSx-X_30 +XNMOS@1 net@0 g gnd NMOSx-X_30 +.ENDS nms2-X_15 + +*** CELL: redFive:nms2_sy{sch} +.SUBCKT nms2_sy-X_30 d g g2 +Xnms2@0 d g g2 nms2-X_15 +Xnms2@1 d g2 g nms2-X_15 +.ENDS nms2_sy-X_30 + +*** CELL: redFive:nand2_sy{sch} +.SUBCKT nand2_sy-X_30 ina inb out +XPMOS@0 out inb vdd PMOSx-X_30 +XPMOS@1 out ina vdd PMOSx-X_30 +Xnms2_sy@0 out ina inb nms2_sy-X_30 +.ENDS nand2_sy-X_30 + +*** CELL: redFive:nand2n_sy{sch} +.SUBCKT nand2n_sy-X_30 ina inb out +Xnand2_sy@0 ina inb out nand2_sy-X_30 +.ENDS nand2n_sy-X_30 + +*** CELL: redFive:nms3{sch} +.SUBCKT nms3-X_20 d g g2 g3 +XNMOS@0 d g3 net@6 NMOSx-X_60 +XNMOS@1 net@7 g gnd NMOSx-X_60 +XNMOS@2 net@6 g2 net@7 NMOSx-X_60 +.ENDS nms3-X_20 *** CELL: orangeTSMC090nm:PMOSx{sch} .SUBCKT PMOSx-X_3 d g s @@ -2389,1069 +1936,1486 @@ MPMOSf@0 d g s vdd pch W='18*(1+ABP/sqrt(18*2))' L='2' +DELVTO='AVT0P/sqrt(18*2)' .ENDS PMOSx-X_3 -*** CELL: redFour:pms3{sch} -.SUBCKT pms3-X_1 d g g2 g3 -XPMOS@0 d g3 net@2 PMOSx-X_3 -XPMOS@1 net@2 g2 net@5 PMOSx-X_3 -XPMOS@2 net@5 g vdd PMOSx-X_3 -.ENDS pms3-X_1 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-162_4-R_34_667m a b -Ccap@0 gnd net@14 0.595f -Ccap@1 gnd net@8 0.595f -Ccap@2 gnd net@11 0.595f -Rres@0 net@14 a 0.938 -Rres@1 net@11 net@14 1.877 -Rres@2 b net@8 0.938 -Rres@3 net@8 net@11 1.877 -.ENDS wire-C_0_011f-162_4-R_34_667m +*** CELL: redFive:pms1{sch} +.SUBCKT pms1-X_3 d g +XPMOS@0 d g vdd PMOSx-X_3 +.ENDS pms1-X_3 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-162_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-162_4-R_34_667m -.ENDS wire90-162_4-layer_1-width_3 +*** CELL: predicateM:nand3in20sr{sch} +.SUBCKT nand3in20sr inA inB inC out resetLO +Xnms3a@0 out inA inB inC nms3-X_20 +Xpms1@0 out inC pms1-X_3 +Xpms1@1 out inB pms1-X_3 +Xpms1@2 out inA pms1-X_3 +Xpms1@3 out resetLO pms1-X_20 +.ENDS nand3in20sr -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-228_5-R_34_667m a b -Ccap@0 gnd net@14 0.838f -Ccap@1 gnd net@8 0.838f -Ccap@2 gnd net@11 0.838f -Rres@0 net@14 a 1.32 -Rres@1 net@11 net@14 2.64 -Rres@2 b net@8 1.32 -Rres@3 net@8 net@11 2.64 -.ENDS wire-C_0_011f-228_5-R_34_667m +*** CELL: driversL:sucDri20plain{sch} +.SUBCKT sucDri20plain in succ +XPMOSx@0 succ in vdd PMOSx-X_20 +Xinv@1 succ net@94 inv-X_4 +Xnms2@0 succ net@127 in nms2-X_2 +Xwire90@0 net@127 net@94 wire90-124_7-layer_1-width_3 +.ENDS sucDri20plain -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-228_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-228_5-R_34_667m -.ENDS wire90-228_5-layer_1-width_3 +*** CELL: predicateM:predSucDri{sch} +.SUBCKT predSucDri do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] sel[Co] ++sel[Ld] sel[Lt] sel[Mv] sel[Tp] +Xna[1] sel[Ld] fire[do] w[1] nand2-X_10 +Xna[2] sel[Co] fire[do] w[2] nand2-X_10 +Xna[3] sel[Mv] fire[do] w[3] nand2-X_10 +Xna[4] sel[Tp] fire[do] w[4] nand2-X_10 +Xna[5] sel[Lt] fire[do] w[5] nand2-X_10 +Xsd[1] w[1] do[Ld] sucDri20plain +Xsd[2] w[2] do[Co] sucDri20plain +Xsd[3] w[3] do[Mv] sucDri20plain +Xsd[4] w[4] do[Tp] sucDri20plain +Xsd[5] w[5] do[Lt] sucDri20plain +Xwire90@0 w[1] wire90@0_b wire90-503_4-layer_1-width_3 +Xwire90@1 w[2] wire90@1_b wire90-503_4-layer_1-width_3 +Xwire90@2 w[3] wire90@2_b wire90-503_4-layer_1-width_3 +Xwire90@3 w[4] wire90@3_b wire90-503_4-layer_1-width_3 +Xwire90@4 w[5] wire90@4_b wire90-503_4-layer_1-width_3 +.ENDS predSucDri + +*** CELL: orangeTSMC090nm:PMOS4x{sch} +.SUBCKT PMOS4x-X_3 b d g s +MPMOS4f@0 d g s b pch W='18*(1+ABP/sqrt(18*2))' L='2' ++DELVTO='AVT0P/sqrt(18*2)' +.ENDS PMOS4x-X_3 -*** CELL: latchesK:rsLatchA{sch} -.SUBCKT rsLatchA mc out outBar reset set -XNMOSx@0 net@193 reset gnd NMOSx-X_10 -XNMOSx@1 net@188 mc gnd NMOSx-X_4 -XPMOSx@3 net@188 net@177 vdd PMOSx-X_10 -Xinv@0 net@193 outBar inv-X_10 -Xinv@1 set net@213 inv-X_4 -Xinv@2 outBar out inv-X_10 -Xnms2@0 net@188 outBar net@177 nms2-X_2 -Xpms3@0 net@193 mc outBar reset pms3-X_1 -Xwire90@0 net@213 net@177 wire90-162_4-layer_1-width_3 -Xwire90@1 net@188 net@193 wire90-228_5-layer_1-width_3 -.ENDS rsLatchA +*** CELL: redFive:nms2{sch} +.SUBCKT nms2-X_20 d g g2 +XNMOS@0 d g2 net@0 NMOSx-X_40 +XNMOS@1 net@0 g gnd NMOSx-X_40 +.ENDS nms2-X_20 -*** CELL: redFour:nor2_sy{sch} -.SUBCKT nor2_sy-X_5 ina inb out -XNMOS@0 out inb gnd NMOSx-X_5 -XNMOS@1 out ina gnd NMOSx-X_5 -Xpms2_sy@0 out ina inb pms2_sy-X_5 -.ENDS nor2_sy-X_5 +*** CELL: redFive:pms2{sch} +.SUBCKT pms2-X_1_5 d g g2 +XPMOS@0 net@2 g vdd PMOSx-X_3 +XPMOS@1 d g2 net@2 PMOSx-X_3 +.ENDS pms2-X_1_5 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1001_8-R_34_667m a b -Ccap@0 gnd net@14 3.673f -Ccap@1 gnd net@8 3.673f -Ccap@2 gnd net@11 3.673f -Rres@0 net@14 a 5.788 -Rres@1 net@11 net@14 11.576 -Rres@2 b net@8 5.788 -Rres@3 net@8 net@11 11.576 -.ENDS wire-C_0_011f-1001_8-R_34_667m +.SUBCKT wire-C_0_011f-243_6-R_34_667m a b +Ccap@0 gnd net@14 0.893f +Ccap@1 gnd net@8 0.893f +Ccap@2 gnd net@11 0.893f +Rres@0 net@14 a 1.407 +Rres@1 net@11 net@14 2.815 +Rres@2 b net@8 1.407 +Rres@3 net@8 net@11 2.815 +.ENDS wire-C_0_011f-243_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1001_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1001_8-R_34_667m -.ENDS wire90-1001_8-layer_1-width_3 +.SUBCKT wire90-243_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-243_6-R_34_667m +.ENDS wire90-243_6-layer_1-width_3 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-209-R_34_667m a b -Ccap@0 gnd net@14 0.766f -Ccap@1 gnd net@8 0.766f -Ccap@2 gnd net@11 0.766f -Rres@0 net@14 a 1.208 -Rres@1 net@11 net@14 2.415 -Rres@2 b net@8 1.208 -Rres@3 net@8 net@11 2.415 -.ENDS wire-C_0_011f-209-R_34_667m +*** CELL: driversL:predCond20wMC{sch} +.SUBCKT predCond20wMC cond in mc pred +XNMOSx@1 pred mc gnd NMOSx-X_10 +XPMOS4x@0 PMOS4x@0_b pred in net@217 PMOS4x-X_3 +XPMOS4x@1 PMOS4x@1_b pred cond net@210 PMOS4x-X_3 +Xinv@0 pred net@145 inv-X_10 +Xnms2@0 pred cond in nms2-X_20 +Xpms2a@0 net@217 mc net@200 pms2-X_1_5 +Xwire90@0 net@200 net@145 wire90-243_6-layer_1-width_3 +Xwire90@1 net@217 net@210 wire90-243_6-layer_1-width_3 +.ENDS predCond20wMC -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-209-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-209-R_34_667m -.ENDS wire90-209-layer_1-width_3 +*** CELL: driversL:predCond20wMS{sch} +.SUBCKT predCond20wMS cond in mc pred +XPMOSx@0 pred cond net@210 PMOSx-X_3 +XPMOSx@1 pred in net@217 PMOSx-X_3 +Xinv@0 pred net@145 inv-X_10 +XinvLT@0 mc net@240 invLT-X_5 +Xnms2@0 pred cond in nms2-X_20 +Xpms1@0 pred net@240 pms1-X_3 +Xpms2a@0 net@217 mc net@200 pms2-X_1_5 +Xwire90@0 net@200 net@145 wire90-243_6-layer_1-width_3 +Xwire90@1 net@217 net@210 wire90-243_6-layer_1-width_3 +.ENDS predCond20wMS + +*** CELL: predicateM:predFlagDri{sch} +.SUBCKT predFlagDri fire[do] flag[A][clr] flag[A][set] flag[B][clr] ++flag[B][set] flag[D][clr] flag[D][set] mc sel[Fl] sel[rD] +XbitAssig@0 bitAssignments +Xpc[1] sel[Fl] fire[do] mc flag[A][set] predCond20wMC +Xpc[2] sel[Fl] fire[do] mc flag[A][clr] predCond20wMC +Xpc[3] sel[Fl] fire[do] mc flag[B][set] predCond20wMC +Xpc[4] sel[Fl] fire[do] mc flag[B][clr] predCond20wMC +XpredCond@0 sel[rD] fire[do] mc flag[D][clr] predCond20wMC +XpredCond@1 sel[rD] fire[do] mc flag[D][set] predCond20wMS +.ENDS predFlagDri + +*** CELL: predicateM:ohPredDo{sch} +.SUBCKT ohPredDo do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] fire[skip] ++flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] ++mc ps[do] ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] +XbitAssig@0 bitAssignments +XohPredDo@3 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] sel[Co] sel[Ld] ++sel[Lt] sel[Mv] sel[Tp] predSucDri +XpredFlag@1 fire[do] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] ++flag[D][clr] flag[D][set] mc sel[Fl] sel[rD] predFlagDri +XsucDri20@0 net@55 ps[skip] sucDri20 +XsucDri20@1 fire[do] ps[do] sucDri20 +Xwire90@2 fire[skip] net@55 wire90-309-layer_1-width_3 +.ENDS ohPredDo + +*** CELL: redFive:pms1{sch} +.SUBCKT pms1-X_5 d g +XPMOS@0 d g vdd PMOSx-X_5 +.ENDS pms1-X_5 + +*** CELL: redFive:pms2{sch} +.SUBCKT pms2-X_1 d g g2 +XPMOS@0 net@2 g vdd PMOSx-X_2 +XPMOS@1 d g2 net@2 PMOSx-X_2 +.ENDS pms2-X_1 -*** CELL: driversL:sucORdri20{sch} -.SUBCKT sucORdri20 inA inB succ -XPMOSx@0 succ net@51 vdd PMOSx-X_20 -Xinv@0 succ net@71 inv-X_4 -Xnms2@0 succ net@73 net@51 nms2-X_2 -Xnor2_sy@0 inA inB net@67 nor2_sy-X_5 -Xwire90@0 net@67 net@51 wire90-1001_8-layer_1-width_3 -Xwire90@1 net@73 net@71 wire90-209-layer_1-width_3 -.ENDS sucORdri20 +*** CELL: predicateM:ohSRxor{sch} +.SUBCKT ohSRxor flag[F] flag[T] out resetLO sel[1] sel[2] +Xnms2b@4 out flag[T] sel[1] nms2-X_5 +Xnms2b@5 out flag[F] sel[2] nms2-X_5 +Xpms1@0 out resetLO pms1-X_5 +Xpms2@0 out flag[T] sel[2] pms2-X_1 +Xpms2@1 out flag[F] sel[1] pms2-X_1 +.ENDS ohSRxor + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-395_6-R_34_667m a b +Ccap@0 gnd net@14 1.451f +Ccap@1 gnd net@8 1.451f +Ccap@2 gnd net@11 1.451f +Rres@0 net@14 a 2.286 +Rres@1 net@11 net@14 4.571 +Rres@2 b net@8 2.286 +Rres@3 net@8 net@11 4.571 +.ENDS wire-C_0_011f-395_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-395_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-395_6-R_34_667m +.ENDS wire90-395_6-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-313_6-R_34_667m a b +Ccap@0 gnd net@14 1.15f +Ccap@1 gnd net@8 1.15f +Ccap@2 gnd net@11 1.15f +Rres@0 net@14 a 1.812 +Rres@1 net@11 net@14 3.624 +Rres@2 b net@8 1.812 +Rres@3 net@8 net@11 3.624 +.ENDS wire-C_0_011f-313_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-313_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-313_6-R_34_667m +.ENDS wire90-313_6-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-339-R_34_667m a b +Ccap@0 gnd net@14 1.243f +Ccap@1 gnd net@8 1.243f +Ccap@2 gnd net@11 1.243f +Rres@0 net@14 a 1.959 +Rres@1 net@11 net@14 3.917 +Rres@2 b net@8 1.959 +Rres@3 net@8 net@11 3.917 +.ENDS wire-C_0_011f-339-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-339-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-339-R_34_667m +.ENDS wire90-339-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-286_1-R_34_667m a b +Ccap@0 gnd net@14 1.049f +Ccap@1 gnd net@8 1.049f +Ccap@2 gnd net@11 1.049f +Rres@0 net@14 a 1.653 +Rres@1 net@11 net@14 3.306 +Rres@2 b net@8 1.653 +Rres@3 net@8 net@11 3.306 +.ENDS wire-C_0_011f-286_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-286_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-286_1-R_34_667m +.ENDS wire90-286_1-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-358_1-R_34_667m a b +Ccap@0 gnd net@14 1.313f +Ccap@1 gnd net@8 1.313f +Ccap@2 gnd net@11 1.313f +Rres@0 net@14 a 2.069 +Rres@1 net@11 net@14 4.138 +Rres@2 b net@8 2.069 +Rres@3 net@8 net@11 4.138 +.ENDS wire-C_0_011f-358_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-358_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-358_1-R_34_667m +.ENDS wire90-358_1-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-415_1-R_34_667m a b +Ccap@0 gnd net@14 1.522f +Ccap@1 gnd net@8 1.522f +Ccap@2 gnd net@11 1.522f +Rres@0 net@14 a 2.398 +Rres@1 net@11 net@14 4.797 +Rres@2 b net@8 2.398 +Rres@3 net@8 net@11 4.797 +.ENDS wire-C_0_011f-415_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-415_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-415_1-R_34_667m +.ENDS wire90-415_1-layer_1-width_3 + +*** CELL: predicateM:ohSRxor6x12{sch} +.SUBCKT ohSRxor6x12 all any flag[A][clr] flag[A][set] flag[B][clr] ++flag[B][set] flag[D][clr] flag[D][set] in[1][F] in[1][T] in[2][F] in[2][T] ++in[3][F] in[3][T] in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T] ++resetLO +Xnand3in6@3 match[12T] match[34T] match[56T] any nand3in6_6sym +Xnor3in3_@2 match[12F] match[34F] match[56F] all nor3in6_6sym +XohSRxor@6 flag[A][clr] flag[A][set] net@106 resetLO in[1][T] in[2][T] ++ohSRxor +XohSRxor@7 flag[A][clr] flag[A][set] net@107 resetLO in[1][F] in[2][F] ++ohSRxor +XohSRxor@8 flag[B][clr] flag[B][set] net@125 resetLO in[3][F] in[4][F] ++ohSRxor +XohSRxor@9 flag[B][clr] flag[B][set] net@122 resetLO in[3][T] in[4][T] ++ohSRxor +XohSRxor@10 flag[D][clr] flag[D][set] net@177 resetLO in[5][F] in[6][F] ++ohSRxor +XohSRxor@11 flag[D][clr] flag[D][set] net@178 resetLO in[5][T] in[6][T] ++ohSRxor +Xwire90@1 match[34T] net@122 wire90-395_6-layer_1-width_3 +Xwire90@3 match[56T] net@178 wire90-313_6-layer_1-width_3 +Xwire90@4 net@107 match[12F] wire90-339-layer_1-width_3 +Xwire90@5 match[12T] net@106 wire90-286_1-layer_1-width_3 +Xwire90@6 match[34F] net@125 wire90-358_1-layer_1-width_3 +Xwire90@7 net@177 match[56F] wire90-415_1-layer_1-width_3 +.ENDS ohSRxor6x12 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-625_1-R_34_667m a b +Ccap@0 gnd net@14 2.292f +Ccap@1 gnd net@8 2.292f +Ccap@2 gnd net@11 2.292f +Rres@0 net@14 a 3.612 +Rres@1 net@11 net@14 7.223 +Rres@2 b net@8 3.612 +Rres@3 net@8 net@11 7.223 +.ENDS wire-C_0_011f-625_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-625_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-625_1-R_34_667m +.ENDS wire90-625_1-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-215_4-R_34_667m a b +Ccap@0 gnd net@14 0.79f +Ccap@1 gnd net@8 0.79f +Ccap@2 gnd net@11 0.79f +Rres@0 net@14 a 1.245 +Rres@1 net@11 net@14 2.489 +Rres@2 b net@8 1.245 +Rres@3 net@8 net@11 2.489 +.ENDS wire-C_0_011f-215_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-215_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-215_4-R_34_667m +.ENDS wire90-215_4-layer_1-width_3 + +*** CELL: predicateM:ohPredPred{sch} +.SUBCKT ohPredPred any do fire[both] flag[A][clr] flag[A][set] flag[B][clr] ++flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F] ++m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] ++m1cate[5][T] m1cate[6][F] m1cate[6][T] mc resetLO s[1] s[2] +Xinv@0 net@51 resetLO inv-X_10 +Xinv@2 fire[both] net@54 inv-X_10 +XinvI@0 net@18 net@49 inv-X_5 +XinvI@1 net@66 s[1] inv-X_10 +XinvI@2 net@71 s[2] inv-X_10 +Xnor2_sy@2 m1cate[1][F] m1cate[1][T] net@62 nor2_sy-X_5 +Xnor2_sy@3 flag[A][clr] flag[A][set] net@67 nor2_sy-X_5 +XohSRxor6@1 do any flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] ++flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] ++m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] ++m1cate[6][F] m1cate[6][T] net@18 ohSRxor6x12 +Xpp[1] fire[both] mc m1cate[1][T] predDri20wMC +Xpp[2] fire[both] mc m1cate[1][F] predDri20wMC +Xpp[3] fire[both] mc m1cate[2][T] predDri20wMC +Xpp[4] fire[both] mc m1cate[2][F] predDri20wMC +Xpp[5] fire[both] mc m1cate[3][T] predDri20wMC +Xpp[6] fire[both] mc m1cate[3][F] predDri20wMC +Xpp[7] fire[both] mc m1cate[4][T] predDri20wMC +Xpp[8] fire[both] mc m1cate[4][F] predDri20wMC +Xpp[9] fire[both] mc m1cate[5][T] predDri20wMC +Xpp[10] fire[both] mc m1cate[5][F] predDri20wMC +Xpp[11] fire[both] mc m1cate[6][T] predDri20wMC +Xpp[12] fire[both] mc m1cate[6][F] predDri20wMC +Xwire90@1 net@54 net@18 wire90-625_1-layer_1-width_3 +Xwire90@3 net@49 net@51 wire90-142_6-layer_1-width_3 +Xwire90@4 net@62 net@66 wire90-215_4-layer_1-width_3 +Xwire90@5 net@67 net@71 wire90-215_4-layer_1-width_3 +.ENDS ohPredPred + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-556_1-R_34_667m a b +Ccap@0 gnd net@14 2.039f +Ccap@1 gnd net@8 2.039f +Ccap@2 gnd net@11 2.039f +Rres@0 net@14 a 3.213 +Rres@1 net@11 net@14 6.426 +Rres@2 b net@8 3.213 +Rres@3 net@8 net@11 6.426 +.ENDS wire-C_0_011f-556_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-556_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-556_1-R_34_667m +.ENDS wire90-556_1-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-557-R_34_667m a b +Ccap@0 gnd net@14 2.042f +Ccap@1 gnd net@8 2.042f +Ccap@2 gnd net@11 2.042f +Rres@0 net@14 a 3.218 +Rres@1 net@11 net@14 6.436 +Rres@2 b net@8 3.218 +Rres@3 net@8 net@11 6.436 +.ENDS wire-C_0_011f-557-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-557-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-557-R_34_667m +.ENDS wire90-557-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-775_9-R_34_667m a b +Ccap@0 gnd net@14 2.845f +Ccap@1 gnd net@8 2.845f +Ccap@2 gnd net@11 2.845f +Rres@0 net@14 a 4.483 +Rres@1 net@11 net@14 8.966 +Rres@2 b net@8 4.483 +Rres@3 net@8 net@11 8.966 +.ENDS wire-C_0_011f-775_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-775_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-775_9-R_34_667m +.ENDS wire90-775_9-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-318_8-R_34_667m a b +Ccap@0 gnd net@14 1.169f +Ccap@1 gnd net@8 1.169f +Ccap@2 gnd net@11 1.169f +Rres@0 net@14 a 1.842 +Rres@1 net@11 net@14 3.684 +Rres@2 b net@8 1.842 +Rres@3 net@8 net@11 3.684 +.ENDS wire-C_0_011f-318_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-318_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-318_8-R_34_667m +.ENDS wire90-318_8-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1035_5-R_34_667m a b +Ccap@0 gnd net@14 3.797f +Ccap@1 gnd net@8 3.797f +Ccap@2 gnd net@11 3.797f +Rres@0 net@14 a 5.983 +Rres@1 net@11 net@14 11.966 +Rres@2 b net@8 5.983 +Rres@3 net@8 net@11 11.966 +.ENDS wire-C_0_011f-1035_5-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1035_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1035_5-R_34_667m +.ENDS wire90-1035_5-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-945_6-R_34_667m a b +Ccap@0 gnd net@14 3.467f +Ccap@1 gnd net@8 3.467f +Ccap@2 gnd net@11 3.467f +Rres@0 net@14 a 5.463 +Rres@1 net@11 net@14 10.927 +Rres@2 b net@8 5.463 +Rres@3 net@8 net@11 10.927 +.ENDS wire-C_0_011f-945_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-945_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-945_6-R_34_667m +.ENDS wire90-945_6-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1126_1-R_34_667m a b +Ccap@0 gnd net@14 4.129f +Ccap@1 gnd net@8 4.129f +Ccap@2 gnd net@11 4.129f +Rres@0 net@14 a 6.506 +Rres@1 net@11 net@14 13.013 +Rres@2 b net@8 6.506 +Rres@3 net@8 net@11 13.013 +.ENDS wire-C_0_011f-1126_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1126_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1126_1-R_34_667m +.ENDS wire90-1126_1-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-361_6-R_34_667m a b +Ccap@0 gnd net@14 1.326f +Ccap@1 gnd net@8 1.326f +Ccap@2 gnd net@11 1.326f +Rres@0 net@14 a 2.089 +Rres@1 net@11 net@14 4.178 +Rres@2 b net@8 2.089 +Rres@3 net@8 net@11 4.178 +.ENDS wire-C_0_011f-361_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-361_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-361_6-R_34_667m +.ENDS wire90-361_6-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-2526_6-R_34_667m a b +Ccap@0 gnd net@14 9.264f +Ccap@1 gnd net@8 9.264f +Ccap@2 gnd net@11 9.264f +Rres@0 net@14 a 14.598 +Rres@1 net@11 net@14 29.196 +Rres@2 b net@8 14.598 +Rres@3 net@8 net@11 29.196 +.ENDS wire-C_0_011f-2526_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-2526_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-2526_6-R_34_667m +.ENDS wire90-2526_6-layer_1-width_3 + +*** CELL: predicateM:ohPredAll{sch} +.SUBCKT ohPredAll do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr] ++flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] ++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] ++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc ps[do] ++ps[skip] s[1] s[2] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] +XbitAssig@0 bitAssignments +XinvI@0 net@82 fire[do] inv-X_40 +XinvI@1 net@63 fire[skip] inv-X_10 +Xnand2_sy@0 net@94 net@11 net@63 nand2_sy-X_10 +Xnand2n_s@0 net@147 net@84 fire[both] nand2n_sy-X_30 +Xnand3in2@1 net@46 net@41 net@11 net@82 net@21 nand3in20sr +Xnor2n_sy@0 ps[skip] ps[do] net@39 nor2n_sy-X_5 +Xnor2n_sy@2 do[Lt] do[Mv] net@38 nor2n_sy-X_5 +XohPredDo@1 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] net@149 flag[A][clr] ++flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] mc ps[do] ++ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] ohPredDo +XohPredPr@1 net@92 net@139 net@160 flag[A][clr] flag[A][set] flag[B][clr] ++flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F] ++m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] ++m1cate[5][T] m1cate[6][F] m1cate[6][T] mc net@19 s[1] s[2] ohPredPred +Xwire90@0 net@39 net@11 wire90-556_1-layer_1-width_3 +Xwire90@1 net@38 net@41 wire90-557-layer_1-width_3 +Xwire90@2 net@46 net@139 wire90-775_9-layer_1-width_3 +Xwire90@3 net@21 net@19 wire90-318_8-layer_1-width_3 +Xwire90@4 net@82 net@84 wire90-1035_5-layer_1-width_3 +Xwire90@5 net@147 net@63 wire90-945_6-layer_1-width_3 +Xwire90@6 net@92 net@94 wire90-1126_1-layer_1-width_3 +Xwire90@7 net@149 fire[skip] wire90-361_6-layer_1-width_3 +Xwire90@9 fire[both] net@160 wire90-2526_6-layer_1-width_3 +.ENDS ohPredAll + +*** CELL: stagesM:predDockStage{sch} +.SUBCKT predDockStage do[Co] do[Ld] do[Lt] do[Mv] do[Tp] flag[A][clr] ++flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] in[10] ++in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] ++in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] ++in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] ++in[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] ++m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] ++m1cate[6][T] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ++ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27] ps[28] ++ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[3] ps[4] ++ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] ++sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] take[1] +XbitAssig@0 bitAssignments +Xins1in20@0 take[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] ++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] ++in[4] in[5] in[6] in[7] in[8] in[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ++ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ++ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ins1in20Bx36 +XlatchDri@0 fire[1] take[1] latchDriver60 +XohPredAl@1 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] net@78 flag[A][clr] ++flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] ++m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] ++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9] ++ps[do] ps[skip] net@69[1] net@69[0] in[24] in[22] in[23] in[27] in[25] in[26] ++in[21] ohPredAll +XscanEx2v@3 net@69[1] net@69[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sor[1] scanEx2 +Xwire90@1 net@78 fire[1] wire90-791_7-layer_1-width_3 +.ENDS predDockStage + +*** CELL: stageGroupsM:m1predicate{sch} +.SUBCKT m1predicate do[Co] do[Ld] do[Lt] do[Mv] do[Tp] do[od] flag[A][clr] ++flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] in[10] ++in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] ++in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] ++in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] ++in[9] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] ++m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] ++m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] ++m1[6] m1[7] m1[8] m1[9] pred ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ++ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ++ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ++ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] sir[1] sir[2] ++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] +XmOneDock@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] ++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] ++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] ++in[5] in[6] in[7] in[8] in[9] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] ++m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] ++m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] ++m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] net@15[10] net@15[11] ++net@15[8] net@15[9] net@15[6] net@15[7] net@15[4] net@15[5] net@15[2] ++net@15[3] net@15[0] net@15[1] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sir[9] net@2[8] do[od] take[m1] mOneDockStage +XpredDock@0 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] flag[A][clr] flag[A][set] ++flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[10] m1[11] m1[12] ++m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] ++m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] ++m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ++net@15[10] net@15[11] net@15[8] net@15[9] net@15[6] net@15[7] net@15[4] ++net@15[5] net@15[2] net@15[3] net@15[0] net@15[1] ps[10] ps[11] ps[12] ps[13] ++ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ++ps[24] ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ++ps[34] ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ++ps[skip] net@2[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] ++sor[1] take[ps] predDockStage +.ENDS m1predicate + +*** CELL: stageGroupsM:centerFive{sch} +.SUBCKT centerFive do[Co] do[Ld] do[Lt] do[Mv] do[Tp] do[epi] epi[TORP] ++flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] ++in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] ++in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] ++in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] ++in[7] in[8] in[9] in[T] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] ++m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] ++m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] ++m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] pred[R] ps[10] ps[11] ps[12] ps[13] ++ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ++ps[24] ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ++ps[34] ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ring[10] ++ring[11] ring[12] ring[13] ring[14] ring[15] ring[16] ring[17] ring[18] ++ring[19] ring[1] ring[20] ring[21] ring[22] ring[23] ring[24] ring[25] ++ring[26] ring[27] ring[28] ring[29] ring[2] ring[30] ring[31] ring[32] ++ring[33] ring[34] ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ++ring[8] ring[9] rq[10] rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] ++rq[18] rq[19] rq[1] rq[20] rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] ++rq[28] rq[29] rq[2] rq[30] rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] ++rq[4] rq[5] rq[6] rq[7] rq[8] rq[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sir[9] sor[1] succ +XepiRQod@0 do[epi] net@46 epi[TORP] flag[A][clr] flag[A][set] flag[D][clr] ++flag[D][set] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] ++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] ++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] ++in[5] in[6] in[7] in[8] in[9] in[T] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] ++m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] ++m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] ++m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] net@11[0] net@11[1] rq[10] ++rq[11] rq[12] rq[13] rq[14] rq[15] rq[16] rq[17] rq[18] rq[19] rq[1] rq[20] ++rq[21] rq[22] rq[23] rq[24] rq[25] rq[26] rq[27] rq[28] rq[29] rq[2] rq[30] ++rq[31] rq[32] rq[33] rq[34] rq[35] rq[36] rq[3] rq[4] rq[5] rq[6] rq[7] rq[8] ++rq[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] ++net@35[8] succ epiRQod +Xm1predic@0 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] net@45 flag[A][clr] ++flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] ring[10] ++ring[11] ring[12] ring[13] ring[14] ring[15] ring[16] ring[17] ring[18] ++ring[19] ring[1] ring[20] ring[21] ring[22] ring[23] ring[24] ring[25] ++ring[26] ring[27] ring[28] ring[29] ring[2] ring[30] ring[31] ring[32] ++ring[33] ring[34] ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ++ring[8] ring[9] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] ++m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] ++m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] ++m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] pred[R] ps[10] ps[11] ps[12] ps[13] ++ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ++ps[24] ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ++ps[34] ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] net@11[0] ++net@11[1] net@35[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] ++sor[1] m1predicate +Xwire90@0 net@45 net@46 wire90-791_7-layer_1-width_3 +.ENDS centerFive + +*** CELL: redFive:nand2n{sch} +.SUBCKT nand2n-X_10 ina inb out +Xnand2@0 ina inb out nand2-X_10 +.ENDS nand2n-X_10 + +*** CELL: redFive:nor2_sy{sch} +.SUBCKT nor2_sy-X_10 ina inb out +XNMOS@0 out inb gnd NMOSx-X_10 +XNMOS@1 out ina gnd NMOSx-X_10 +Xpms2_sy@0 out ina inb pms2_sy-X_10 +.ENDS nor2_sy-X_10 + +*** CELL: redFive:nor2n_sy{sch} +.SUBCKT nor2n_sy-X_10 ina inb out +Xnor2@0 ina inb out nor2_sy-X_10 +.ENDS nor2n_sy-X_10 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-345_1-R_34_667m a b -Ccap@0 gnd net@14 1.265f -Ccap@1 gnd net@8 1.265f -Ccap@2 gnd net@11 1.265f -Rres@0 net@14 a 1.994 -Rres@1 net@11 net@14 3.988 -Rres@2 b net@8 1.994 -Rres@3 net@8 net@11 3.988 -.ENDS wire-C_0_011f-345_1-R_34_667m +.SUBCKT wire-C_0_011f-405_3-R_34_667m a b +Ccap@0 gnd net@14 1.486f +Ccap@1 gnd net@8 1.486f +Ccap@2 gnd net@11 1.486f +Rres@0 net@14 a 2.342 +Rres@1 net@11 net@14 4.683 +Rres@2 b net@8 2.342 +Rres@3 net@8 net@11 4.683 +.ENDS wire-C_0_011f-405_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-345_1-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-345_1-R_34_667m -.ENDS wire90-345_1-layer_1-width_3 +.SUBCKT wire90-405_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-405_3-R_34_667m +.ENDS wire90-405_3-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-537-R_34_667m a b -Ccap@0 gnd net@14 1.969f -Ccap@1 gnd net@8 1.969f -Ccap@2 gnd net@11 1.969f -Rres@0 net@14 a 3.103 -Rres@1 net@11 net@14 6.205 -Rres@2 b net@8 3.103 -Rres@3 net@8 net@11 6.205 -.ENDS wire-C_0_011f-537-R_34_667m +.SUBCKT wire-C_0_011f-385_8-R_34_667m a b +Ccap@0 gnd net@14 1.415f +Ccap@1 gnd net@8 1.415f +Ccap@2 gnd net@11 1.415f +Rres@0 net@14 a 2.229 +Rres@1 net@11 net@14 4.458 +Rres@2 b net@8 2.229 +Rres@3 net@8 net@11 4.458 +.ENDS wire-C_0_011f-385_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-537-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-537-R_34_667m -.ENDS wire90-537-layer_1-width_3 +.SUBCKT wire90-385_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-385_8-R_34_667m +.ENDS wire90-385_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-470_7-R_34_667m a b -Ccap@0 gnd net@14 1.726f -Ccap@1 gnd net@8 1.726f -Ccap@2 gnd net@11 1.726f -Rres@0 net@14 a 2.72 -Rres@1 net@11 net@14 5.439 -Rres@2 b net@8 2.72 -Rres@3 net@8 net@11 5.439 -.ENDS wire-C_0_011f-470_7-R_34_667m +.SUBCKT wire-C_0_011f-406_4-R_34_667m a b +Ccap@0 gnd net@14 1.49f +Ccap@1 gnd net@8 1.49f +Ccap@2 gnd net@11 1.49f +Rres@0 net@14 a 2.348 +Rres@1 net@11 net@14 4.696 +Rres@2 b net@8 2.348 +Rres@3 net@8 net@11 4.696 +.ENDS wire-C_0_011f-406_4-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-470_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-470_7-R_34_667m -.ENDS wire90-470_7-layer_1-width_3 - -*** CELL: gaspL:anAltEnd{sch} -.SUBCKT anAltEnd fire[A] fire[B] mc predA predB s[1] s[2] s[3] succ -XctrAND4i@2 net@1013 succ fire[B] net@1133 fire[A] ctrAND4in30 -XctrAND4i@3 net@1007 succ net@1142 fire[A] fire[B] ctrAND4in30 -Xinv@3 net@822 s[1] inv-X_10 -Xinv@4 net@824 s[3] inv-X_10 -Xinv@5 predA net@822 inv-X_5 -Xinv@6 predB net@824 inv-X_5 -Xinv@7 net@1133 s[2] inv-X_10 -XpredDri2@0 fire[A] mc predA predDri20wMC -XpredDri2@1 fire[B] mc predB predDri20wMC -XrsLatchA@1 mc net@1040 net@1082 fire[B] fire[A] rsLatchA -XsucORdri@0 fire[A] fire[B] succ sucORdri20 -Xwire90@34 net@824 net@1007 wire90-345_1-layer_1-width_3 -Xwire90@35 net@822 net@1013 wire90-345_1-layer_1-width_3 -Xwire90@36 net@1142 net@1082 wire90-537-layer_1-width_3 -Xwire90@37 net@1133 net@1040 wire90-470_7-layer_1-width_3 -.ENDS anAltEnd +.SUBCKT wire90-406_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-406_4-R_34_667m +.ENDS wire90-406_4-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1336_2-R_34_667m a b -Ccap@0 gnd net@14 4.899f -Ccap@1 gnd net@8 4.899f -Ccap@2 gnd net@11 4.899f -Rres@0 net@14 a 7.72 -Rres@1 net@11 net@14 15.441 -Rres@2 b net@8 7.72 -Rres@3 net@8 net@11 15.441 -.ENDS wire-C_0_011f-1336_2-R_34_667m +.SUBCKT wire-C_0_011f-329_2-R_34_667m a b +Ccap@0 gnd net@14 1.207f +Ccap@1 gnd net@8 1.207f +Ccap@2 gnd net@11 1.207f +Rres@0 net@14 a 1.902 +Rres@1 net@11 net@14 3.804 +Rres@2 b net@8 1.902 +Rres@3 net@8 net@11 3.804 +.ENDS wire-C_0_011f-329_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1336_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1336_2-R_34_667m -.ENDS wire90-1336_2-layer_1-width_3 +.SUBCKT wire90-329_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-329_2-R_34_667m +.ENDS wire90-329_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1307-R_34_667m a b -Ccap@0 gnd net@14 4.792f -Ccap@1 gnd net@8 4.792f -Ccap@2 gnd net@11 4.792f -Rres@0 net@14 a 7.552 -Rres@1 net@11 net@14 15.103 -Rres@2 b net@8 7.552 -Rres@3 net@8 net@11 15.103 -.ENDS wire-C_0_011f-1307-R_34_667m +.SUBCKT wire-C_0_011f-407_9-R_34_667m a b +Ccap@0 gnd net@14 1.496f +Ccap@1 gnd net@8 1.496f +Ccap@2 gnd net@11 1.496f +Rres@0 net@14 a 2.357 +Rres@1 net@11 net@14 4.714 +Rres@2 b net@8 2.357 +Rres@3 net@8 net@11 4.714 +.ENDS wire-C_0_011f-407_9-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1307-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1307-R_34_667m -.ENDS wire90-1307-layer_1-width_3 +.SUBCKT wire90-407_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-407_9-R_34_667m +.ENDS wire90-407_9-layer_1-width_3 -*** CELL: stepsM:altEndStep{sch} -.SUBCKT altEndStep inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] inA[16] -+inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] inA[24] -+inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] inA[32] -+inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7] inA[8] -+inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17] -+inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25] -+inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33] -+inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9] mc -+out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] -+out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] -+out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] -+out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] predA predB -+sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ -XanAltEnd@0 fire[A] fire[B] mc predA predB s[1] s[2] s[3] succ anAltEnd -XlatchDri@0 net@3 net@27 latchDriver60 -XlatchDri@1 net@7 net@23 latchDriver60 -XscanEx3h@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sor[1] scanEx3hor -Xshort2in@2 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] inA[16] inA[17] -+inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] inA[24] inA[25] -+inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] inA[32] inA[33] -+inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7] inA[8] inA[9] -+inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17] inB[18] -+inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25] inB[26] -+inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33] inB[34] -+inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9] out[10] -+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] -+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] -+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] -+out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] take[A] take[B] -+short2in20Ax36 -Xwire90@0 net@7 fire[B] wire90-1336_2-layer_1-width_3 -Xwire90@1 net@3 fire[A] wire90-1307-layer_1-width_3 -Xwire90@2 net@23 take[B] wire90-1336_2-layer_1-width_3 -Xwire90@3 net@27 take[A] wire90-1307-layer_1-width_3 -.ENDS altEndStep +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-247-R_34_667m a b +Ccap@0 gnd net@14 0.906f +Ccap@1 gnd net@8 0.906f +Ccap@2 gnd net@11 0.906f +Rres@0 net@14 a 1.427 +Rres@1 net@11 net@14 2.854 +Rres@2 b net@8 1.427 +Rres@3 net@8 net@11 2.854 +.ENDS wire-C_0_011f-247-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-247-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-247-R_34_667m +.ENDS wire90-247-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-456_8-R_34_667m a b +Ccap@0 gnd net@14 1.675f +Ccap@1 gnd net@8 1.675f +Ccap@2 gnd net@11 1.675f +Rres@0 net@14 a 2.639 +Rres@1 net@11 net@14 5.279 +Rres@2 b net@8 2.639 +Rres@3 net@8 net@11 5.279 +.ENDS wire-C_0_011f-456_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-456_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-456_8-R_34_667m +.ENDS wire90-456_8-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-477_4-R_34_667m a b +Ccap@0 gnd net@14 1.75f +Ccap@1 gnd net@8 1.75f +Ccap@2 gnd net@11 1.75f +Rres@0 net@14 a 2.758 +Rres@1 net@11 net@14 5.517 +Rres@2 b net@8 2.758 +Rres@3 net@8 net@11 5.517 +.ENDS wire-C_0_011f-477_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-477_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-477_4-R_34_667m +.ENDS wire90-477_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-480_2-R_34_667m a b +Ccap@0 gnd net@14 1.761f +Ccap@1 gnd net@8 1.761f +Ccap@2 gnd net@11 1.761f +Rres@0 net@14 a 2.774 +Rres@1 net@11 net@14 5.549 +Rres@2 b net@8 2.774 +Rres@3 net@8 net@11 5.549 +.ENDS wire-C_0_011f-480_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-480_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-480_2-R_34_667m +.ENDS wire90-480_2-layer_1-width_3 + +*** CELL: redFive:xor2{sch} +.SUBCKT xor2-X_5 ina inaB inb inbB out +Xnms2@0 out inb ina nms2-X_5 +Xnms2@1 out inbB inaB nms2-X_5 +Xpms2@0 out inbB ina pms2-X_5 +Xpms2@1 out inb inaB pms2-X_5 +.ENDS xor2-X_5 + +*** CELL: oneHotM:ohXor{sch} +.SUBCKT ohXor flag[F] flag[T] in[1][F] in[1][T] out +Xxor2@0 in[1][T] in[1][F] flag[T] flag[F] out xor2-X_5 +.ENDS ohXor *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-237_2-R_34_667m a b -Ccap@0 gnd net@14 0.87f -Ccap@1 gnd net@8 0.87f -Ccap@2 gnd net@11 0.87f -Rres@0 net@14 a 1.37 -Rres@1 net@11 net@14 2.741 -Rres@2 b net@8 1.37 -Rres@3 net@8 net@11 2.741 -.ENDS wire-C_0_011f-237_2-R_34_667m +.SUBCKT wire-C_0_011f-357-R_34_667m a b +Ccap@0 gnd net@14 1.309f +Ccap@1 gnd net@8 1.309f +Ccap@2 gnd net@11 1.309f +Rres@0 net@14 a 2.063 +Rres@1 net@11 net@14 4.125 +Rres@2 b net@8 2.063 +Rres@3 net@8 net@11 4.125 +.ENDS wire-C_0_011f-357-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-237_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-237_2-R_34_667m -.ENDS wire90-237_2-layer_1-width_3 +.SUBCKT wire90-357-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-357-R_34_667m +.ENDS wire90-357-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-221_8-R_34_667m a b -Ccap@0 gnd net@14 0.813f -Ccap@1 gnd net@8 0.813f -Ccap@2 gnd net@11 0.813f -Rres@0 net@14 a 1.282 -Rres@1 net@11 net@14 2.563 -Rres@2 b net@8 1.282 -Rres@3 net@8 net@11 2.563 -.ENDS wire-C_0_011f-221_8-R_34_667m +.SUBCKT wire-C_0_011f-394_5-R_34_667m a b +Ccap@0 gnd net@14 1.447f +Ccap@1 gnd net@8 1.447f +Ccap@2 gnd net@11 1.447f +Rres@0 net@14 a 2.279 +Rres@1 net@11 net@14 4.559 +Rres@2 b net@8 2.279 +Rres@3 net@8 net@11 4.559 +.ENDS wire-C_0_011f-394_5-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-221_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-221_8-R_34_667m -.ENDS wire90-221_8-layer_1-width_3 +.SUBCKT wire90-394_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-394_5-R_34_667m +.ENDS wire90-394_5-layer_1-width_3 -*** CELL: centersJ:ctrAND4in30M{sch} -.SUBCKT ctrAND4in30M inA inB inC inD out outM -Xinv@1 outM out inv-X_30 -Xnand2@1 net@43 net@58 outM nand2-X_10 -Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4 -Xnor2n@0 inD inC net@64 nor2n-X_5 -Xwire90@0 net@64 net@43 wire90-237_2-layer_1-width_3 -Xwire90@2 net@61 net@58 wire90-221_8-layer_1-width_3 -.ENDS ctrAND4in30M +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-372_2-R_34_667m a b +Ccap@0 gnd net@14 1.365f +Ccap@1 gnd net@8 1.365f +Ccap@2 gnd net@11 1.365f +Rres@0 net@14 a 2.15 +Rres@1 net@11 net@14 4.301 +Rres@2 b net@8 2.15 +Rres@3 net@8 net@11 4.301 +.ENDS wire-C_0_011f-372_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-372_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-372_2-R_34_667m +.ENDS wire90-372_2-layer_1-width_3 -*** CELL: redFour:nand2_sy{sch} -.SUBCKT nand2_sy-X_10 ina inb out -XPMOS@0 out inb vdd PMOSx-X_10 -XPMOS@1 out ina vdd PMOSx-X_10 -Xnms2_sy@0 out ina inb nms2_sy-X_10 -.ENDS nand2_sy-X_10 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-319_8-R_34_667m a b +Ccap@0 gnd net@14 1.173f +Ccap@1 gnd net@8 1.173f +Ccap@2 gnd net@11 1.173f +Rres@0 net@14 a 1.848 +Rres@1 net@11 net@14 3.695 +Rres@2 b net@8 1.848 +Rres@3 net@8 net@11 3.695 +.ENDS wire-C_0_011f-319_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-319_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-319_8-R_34_667m +.ENDS wire90-319_8-layer_1-width_3 -*** CELL: redFour:nand2n_sy{sch} -.SUBCKT nand2n_sy-X_10 ina inb out -Xnand2_sy@0 ina inb out nand2_sy-X_10 -.ENDS nand2n_sy-X_10 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-386_5-R_34_667m a b +Ccap@0 gnd net@14 1.417f +Ccap@1 gnd net@8 1.417f +Ccap@2 gnd net@11 1.417f +Rres@0 net@14 a 2.233 +Rres@1 net@11 net@14 4.466 +Rres@2 b net@8 2.233 +Rres@3 net@8 net@11 4.466 +.ENDS wire-C_0_011f-386_5-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-386_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-386_5-R_34_667m +.ENDS wire90-386_5-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-700-R_34_667m a b -Ccap@0 gnd net@14 2.567f -Ccap@1 gnd net@8 2.567f -Ccap@2 gnd net@11 2.567f -Rres@0 net@14 a 4.044 -Rres@1 net@11 net@14 8.089 -Rres@2 b net@8 4.044 -Rres@3 net@8 net@11 8.089 -.ENDS wire-C_0_011f-700-R_34_667m +.SUBCKT wire-C_0_011f-297_8-R_34_667m a b +Ccap@0 gnd net@14 1.092f +Ccap@1 gnd net@8 1.092f +Ccap@2 gnd net@11 1.092f +Rres@0 net@14 a 1.721 +Rres@1 net@11 net@14 3.441 +Rres@2 b net@8 1.721 +Rres@3 net@8 net@11 3.441 +.ENDS wire-C_0_011f-297_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-297_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-297_8-R_34_667m +.ENDS wire90-297_8-layer_1-width_3 + +*** CELL: oneHotM:xor6x12{sch} +.SUBCKT xor6x12 all any flag[1][F] flag[1][T] flag[2][F] flag[2][T] ++flag[3][F] flag[3][T] in[1][F] in[1][T] in[2][F] in[2][T] in[3][F] in[3][T] ++in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T] +Xnand3in6@2 match[12T] match[34T] match[56T] any nand3in6_6sym +Xnor3in3_@1 match[56F] match[34F] match[12F] all nor3in6_6sym +XohMux@6 flag[1][F] flag[1][T] in[2][F] in[1][F] net@84 ohXor +XohMux@7 flag[1][F] flag[1][T] in[2][T] in[1][T] net@91 ohXor +XohMux@8 flag[2][F] flag[2][T] in[4][F] in[3][F] net@94 ohXor +XohMux@9 flag[2][F] flag[2][T] in[4][T] in[3][T] net@93 ohXor +XohMux@10 flag[3][F] flag[3][T] in[6][F] in[5][F] net@102 ohXor +XohMux@11 flag[3][F] flag[3][T] in[6][T] in[5][T] net@101 ohXor +Xwire90@0 net@94 match[34F] wire90-357-layer_1-width_3 +Xwire90@1 match[34T] net@93 wire90-394_5-layer_1-width_3 +Xwire90@2 net@102 match[56F] wire90-372_2-layer_1-width_3 +Xwire90@3 match[56T] net@101 wire90-319_8-layer_1-width_3 +Xwire90@4 net@84 match[12F] wire90-386_5-layer_1-width_3 +Xwire90@5 match[12T] net@91 wire90-297_8-layer_1-width_3 +.ENDS xor6x12 + +*** CELL: oneHotM:aFlag{sch} +.SUBCKT aFlag flag[1][F] flag[1][T] flag[1][clr] flag[1][set] flag[A][F] ++flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] in[1][T] in[2][T] ++in[3][T] in[4][T] in[5][T] in[6][T] mc +Xinv@0 net@257 flag[1][T] inv-X_20 +Xinv@2 net@258 flag[1][F] inv-X_20 +Xinv@3 net@2 net@267 inv-X_10 +Xinv@4 mc net@305 inv-X_10 +XinvI@10 net@9 net@308 inv-X_5 +XinvI@11 net@176 net@306 inv-X_5 +Xinv[1] in[1][T] in[1][F] inv-X_10 +Xinv[2] in[2][T] in[2][F] inv-X_10 +Xinv[3] in[3][T] in[3][F] inv-X_10 +Xinv[4] in[4][T] in[4][F] inv-X_10 +Xinv[5] in[5][T] in[5][F] inv-X_10 +Xinv[6] in[6][T] in[6][F] inv-X_10 +Xnand2@0 net@5 net@2 net@9 nand2-X_5 +Xnand2@1 net@69 net@71 net@176 nand2-X_5 +Xnand2@2 net@51 net@267 net@239 nand2-X_5 +Xnand2@3 net@22 net@265 net@240 nand2-X_5 +Xnand2n@0 net@64 net@49 net@51 nand2n-X_10 +Xnand2n@1 net@172 net@50 net@22 nand2n-X_10 +Xnand2n@2 net@236 net@235 net@258 nand2n-X_10 +Xnand2n@3 net@259 net@234 net@257 nand2n-X_10 +Xnor2n_sy@0 flag[1][clr] flag[1][set] net@2 nor2n_sy-X_10 +XsucANDdr@0 net@305 net@308 flag[1][set] sucANDdri20 +XsucANDdr@3 net@319 net@306 flag[1][clr] sucANDdri20 +Xwire90@1 net@8 net@5 wire90-405_3-layer_1-width_3 +Xwire90@4 net@22 net@49 wire90-385_8-layer_1-width_3 +Xwire90@5 net@50 net@51 wire90-406_4-layer_1-width_3 +Xwire90@6 net@64 net@9 wire90-329_2-layer_1-width_3 +Xwire90@8 net@69 net@68 wire90-407_9-layer_1-width_3 +Xwire90@19 net@176 net@172 wire90-329_2-layer_1-width_3 +Xwire90@22 net@240 net@259 wire90-247-layer_1-width_3 +Xwire90@23 net@236 net@239 wire90-247-layer_1-width_3 +Xwire90@24 net@257 net@235 wire90-456_8-layer_1-width_3 +Xwire90@25 net@234 net@258 wire90-477_4-layer_1-width_3 +Xwire90@26 net@71 net@2 wire90-775_9-layer_1-width_3 +Xwire90@27 net@265 net@267 wire90-480_2-layer_1-width_3 +Xwire90@28 net@319 net@305 wire90-385_8-layer_1-width_3 +Xxor6x12@0 net@68 net@8 flag[A][F] flag[A][T] flag[B][F] flag[B][T] ++flag[C][F] flag[C][T] in[1][F] in[1][T] in[2][F] in[2][T] in[3][F] in[3][T] ++in[4][F] in[4][T] in[5][F] in[5][T] in[6][F] in[6][T] xor6x12 +.ENDS aFlag + +*** CELL: oneHotM:flags{sch} +.SUBCKT flags flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][F] ++flag[C][T] m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] ++m1[8] m1[9] mc +XaFlag@0 flag[A][F] flag[A][T] flag[A][clr] flag[A][set] flag[A][F] ++flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] m1[1] m1[2] m1[3] ++m1[4] m1[5] m1[6] mc aFlag +XaFlag@1 flag[B][F] flag[B][T] flag[B][clr] flag[B][set] flag[A][F] ++flag[A][T] flag[B][F] flag[B][T] flag[C][F] flag[C][T] m1[7] m1[8] m1[9] ++m1[10] m1[11] m1[12] mc aFlag +.ENDS flags + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-549_2-R_34_667m a b +Ccap@0 gnd net@14 2.014f +Ccap@1 gnd net@8 2.014f +Ccap@2 gnd net@11 2.014f +Rres@0 net@14 a 3.173 +Rres@1 net@11 net@14 6.346 +Rres@2 b net@8 3.173 +Rres@3 net@8 net@11 6.346 +.ENDS wire-C_0_011f-549_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-700-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-700-R_34_667m -.ENDS wire90-700-layer_1-width_3 +.SUBCKT wire90-549_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-549_2-R_34_667m +.ENDS wire90-549_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-839_6-R_34_667m a b -Ccap@0 gnd net@14 3.079f -Ccap@1 gnd net@8 3.079f -Ccap@2 gnd net@11 3.079f -Rres@0 net@14 a 4.851 -Rres@1 net@11 net@14 9.702 -Rres@2 b net@8 4.851 -Rres@3 net@8 net@11 9.702 -.ENDS wire-C_0_011f-839_6-R_34_667m +.SUBCKT wire-C_0_011f-703_8-R_34_667m a b +Ccap@0 gnd net@14 2.581f +Ccap@1 gnd net@8 2.581f +Ccap@2 gnd net@11 2.581f +Rres@0 net@14 a 4.066 +Rres@1 net@11 net@14 8.133 +Rres@2 b net@8 4.066 +Rres@3 net@8 net@11 8.133 +.ENDS wire-C_0_011f-703_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-839_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-839_6-R_34_667m -.ENDS wire90-839_6-layer_1-width_3 +.SUBCKT wire90-703_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-703_8-R_34_667m +.ENDS wire90-703_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-438_2-R_34_667m a b -Ccap@0 gnd net@14 1.607f -Ccap@1 gnd net@8 1.607f -Ccap@2 gnd net@11 1.607f -Rres@0 net@14 a 2.532 -Rres@1 net@11 net@14 5.064 -Rres@2 b net@8 2.532 -Rres@3 net@8 net@11 5.064 -.ENDS wire-C_0_011f-438_2-R_34_667m +.SUBCKT wire-C_0_011f-543_6-R_34_667m a b +Ccap@0 gnd net@14 1.993f +Ccap@1 gnd net@8 1.993f +Ccap@2 gnd net@11 1.993f +Rres@0 net@14 a 3.141 +Rres@1 net@11 net@14 6.282 +Rres@2 b net@8 3.141 +Rres@3 net@8 net@11 6.282 +.ENDS wire-C_0_011f-543_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-438_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-438_2-R_34_667m -.ENDS wire90-438_2-layer_1-width_3 +.SUBCKT wire90-543_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-543_6-R_34_667m +.ENDS wire90-543_6-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-257_4-R_34_667m a b -Ccap@0 gnd net@14 0.944f -Ccap@1 gnd net@8 0.944f -Ccap@2 gnd net@11 0.944f -Rres@0 net@14 a 1.487 -Rres@1 net@11 net@14 2.974 -Rres@2 b net@8 1.487 -Rres@3 net@8 net@11 2.974 -.ENDS wire-C_0_011f-257_4-R_34_667m +.SUBCKT wire-C_0_011f-645_3-R_34_667m a b +Ccap@0 gnd net@14 2.366f +Ccap@1 gnd net@8 2.366f +Ccap@2 gnd net@11 2.366f +Rres@0 net@14 a 3.728 +Rres@1 net@11 net@14 7.457 +Rres@2 b net@8 3.728 +Rres@3 net@8 net@11 7.457 +.ENDS wire-C_0_011f-645_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-257_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-257_4-R_34_667m -.ENDS wire90-257_4-layer_1-width_3 +.SUBCKT wire90-645_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-645_3-R_34_667m +.ENDS wire90-645_3-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-458_8-R_34_667m a b -Ccap@0 gnd net@14 1.682f -Ccap@1 gnd net@8 1.682f -Ccap@2 gnd net@11 1.682f -Rres@0 net@14 a 2.651 -Rres@1 net@11 net@14 5.302 -Rres@2 b net@8 2.651 -Rres@3 net@8 net@11 5.302 -.ENDS wire-C_0_011f-458_8-R_34_667m +.SUBCKT wire-C_0_011f-378_8-R_34_667m a b +Ccap@0 gnd net@14 1.389f +Ccap@1 gnd net@8 1.389f +Ccap@2 gnd net@11 1.389f +Rres@0 net@14 a 2.189 +Rres@1 net@11 net@14 4.377 +Rres@2 b net@8 2.189 +Rres@3 net@8 net@11 4.377 +.ENDS wire-C_0_011f-378_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-378_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-378_8-R_34_667m +.ENDS wire90-378_8-layer_1-width_3 + +*** CELL: loopCountM:calculate{sch} +.SUBCKT calculate bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] do[2] do[3] do[4] ++do[5] do[6] zero zoo +Xinv@0 net@257 do[2] inv-X_10 +Xinv@1 bit[2] net@128 inv-X_10 +Xinv@2 bit[1] net@257 inv-X_10 +Xnand2@0 bit[3] bit[1] net@145 nand2-X_10 +Xnand2@1 bit[4] bit[2] net@195 nand2-X_10 +Xnand2@2 bit[3] bit[5] net@315 nand2-X_10 +Xnand3@0 bit[5] bit[3] bit[1] net@264 nand3-X_6_667 +Xnand3@1 bit[6] bit[4] bit[2] net@198 nand3-X_6_667 +Xnor2n@1 net@128 net@257 do[3] nor2n-X_10 +Xnor2n@2 net@145 net@146 do[4] nor2n-X_10 +Xnor2n@3 net@195 net@58 do[5] nor2n-X_10 +Xnor2n@4 net@221 net@56 do[6] nor2n-X_10 +Xnor2n@5 net@289 net@267 zoo nor2n-X_10 +Xnor2n@6 net@198 net@264 zero nor2n-X_10 +Xwire90@0 net@264 net@221 wire90-549_2-layer_1-width_3 +Xwire90@1 net@58 net@145 wire90-703_8-layer_1-width_3 +Xwire90@3 net@56 net@195 wire90-703_8-layer_1-width_3 +Xwire90@5 net@198 net@289 wire90-543_6-layer_1-width_3 +Xwire90@6 net@146 net@128 wire90-645_3-layer_1-width_3 +Xwire90@8 net@267 net@315 wire90-378_8-layer_1-width_3 +.ENDS calculate + +*** CELL: redFive:pms2{sch} +.SUBCKT pms2-X_2 d g g2 +XPMOS@0 net@2 g vdd PMOSx-X_4 +XPMOS@1 d g2 net@2 PMOSx-X_4 +.ENDS pms2-X_2 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-185-R_34_667m a b +Ccap@0 gnd net@14 0.678f +Ccap@1 gnd net@8 0.678f +Ccap@2 gnd net@11 0.678f +Rres@0 net@14 a 1.069 +Rres@1 net@11 net@14 2.138 +Rres@2 b net@8 1.069 +Rres@3 net@8 net@11 2.138 +.ENDS wire-C_0_011f-185-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-458_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-458_8-R_34_667m -.ENDS wire90-458_8-layer_1-width_3 +.SUBCKT wire90-185-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-185-R_34_667m +.ENDS wire90-185-layer_1-width_3 + +*** CELL: latchesK:mlat1in10{sch} +.SUBCKT mlat1in10 cl[F] cl[T] in[1] out[1] +Xinv@0 net@26 out[1] inv-X_10 +Xnms2@0 net@4 out[1] cl[F] nms2-X_2 +Xnms2@1 net@4 in[1] cl[T] nms2-X_2 +Xpms2@0 net@4 out[1] cl[T] pms2-X_1 +Xpms2@1 net@4 in[1] cl[F] pms2-X_2 +Xwire90@0 net@4 net@26 wire90-185-layer_1-width_3 +.ENDS mlat1in10 + +*** CELL: redFive:invLT{sch} +.SUBCKT invLT-X_2 in out +XNMOS@0 out in gnd NMOSx-X_4 +XPMOS@0 out in vdd PMOSx-X_2 +.ENDS invLT-X_2 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-744_5-R_34_667m a b -Ccap@0 gnd net@14 2.73f -Ccap@1 gnd net@8 2.73f -Ccap@2 gnd net@11 2.73f -Rres@0 net@14 a 4.302 -Rres@1 net@11 net@14 8.603 -Rres@2 b net@8 4.302 -Rres@3 net@8 net@11 8.603 -.ENDS wire-C_0_011f-744_5-R_34_667m +.SUBCKT wire-C_0_011f-133_8-R_34_667m a b +Ccap@0 gnd net@14 0.491f +Ccap@1 gnd net@8 0.491f +Ccap@2 gnd net@11 0.491f +Rres@0 net@14 a 0.773 +Rres@1 net@11 net@14 1.546 +Rres@2 b net@8 0.773 +Rres@3 net@8 net@11 1.546 +.ENDS wire-C_0_011f-133_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-744_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-744_5-R_34_667m -.ENDS wire90-744_5-layer_1-width_3 +.SUBCKT wire90-133_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-133_8-R_34_667m +.ENDS wire90-133_8-layer_1-width_3 -*** CELL: gaspL:anAltStart{sch} -.SUBCKT anAltStart fire[A] fire[B] mc pred s[1] s[2] succA succB -XctrAND4i@1 net@634 succA fire[B] net@912 fire[A] net@866 ctrAND4in30M -XctrAND4i@3 net@634 succB net@909 fire[A] fire[B] net@885 ctrAND4in30M -Xinv@3 net@634 s[1] inv-X_10 -Xinv@4 pred net@787 inv-X_10 -Xinv@5 net@912 s[2] inv-X_10 -Xnand2n_s@0 net@143 net@410 net@422 nand2n_sy-X_10 -XpredDri2@0 net@815 mc pred predDri20wMC -XrsLatchA@1 mc net@905 net@911 fire[B] fire[A] rsLatchA -XsucDri20@0 fire[A] succA sucDri20 -XsucDri20@1 fire[B] succB sucDri20 -Xwire90@16 net@410 net@866 wire90-700-layer_1-width_3 -Xwire90@17 net@143 net@885 wire90-839_6-layer_1-width_3 -Xwire90@19 net@912 net@905 wire90-438_2-layer_1-width_3 -Xwire90@20 net@815 net@422 wire90-257_4-layer_1-width_3 -Xwire90@27 net@909 net@911 wire90-458_8-layer_1-width_3 -Xwire90@28 net@787 net@634 wire90-744_5-layer_1-width_3 -.ENDS anAltStart +*** CELL: latchesK:mlat1in5i{sch} +.SUBCKT mlat1in5i c[F] c[T] in out +XinvLT@0 out net@119 invLT-X_2 +Xnms2@2 out in c[T] nms2-X_5 +Xnms2@3 out net@114 c[F] nms2-X_2 +Xpms2@0 out net@114 c[T] pms2-X_1 +Xpms2@1 out in c[F] pms2-X_5 +Xwire90@19 net@114 net@119 wire90-133_8-layer_1-width_3 +.ENDS mlat1in5i -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1300-R_34_667m a b -Ccap@0 gnd net@14 4.767f -Ccap@1 gnd net@8 4.767f -Ccap@2 gnd net@11 4.767f -Rres@0 net@14 a 7.511 -Rres@1 net@11 net@14 15.022 -Rres@2 b net@8 7.511 -Rres@3 net@8 net@11 15.022 -.ENDS wire-C_0_011f-1300-R_34_667m +*** CELL: redFive:nms3{sch} +.SUBCKT nms3-X_2 d g g2 g3 +XNMOS@0 d g3 net@6 NMOSx-X_6 +XNMOS@1 net@7 g gnd NMOSx-X_6 +XNMOS@2 net@6 g2 net@7 NMOSx-X_6 +.ENDS nms3-X_2 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1300-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1300-R_34_667m -.ENDS wire90-1300-layer_1-width_3 +*** CELL: redFive:pms3{sch} +.SUBCKT pms3-X_1 d g g2 g3 +XPMOS@0 d g3 net@2 PMOSx-X_3 +XPMOS@1 net@2 g2 net@5 PMOSx-X_3 +XPMOS@2 net@5 g vdd PMOSx-X_3 +.ENDS pms3-X_1 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1301_9-R_34_667m a b -Ccap@0 gnd net@14 4.774f -Ccap@1 gnd net@8 4.774f -Ccap@2 gnd net@11 4.774f -Rres@0 net@14 a 7.522 -Rres@1 net@11 net@14 15.044 -Rres@2 b net@8 7.522 -Rres@3 net@8 net@11 15.044 -.ENDS wire-C_0_011f-1301_9-R_34_667m +.SUBCKT wire-C_0_011f-200_9-R_34_667m a b +Ccap@0 gnd net@14 0.737f +Ccap@1 gnd net@8 0.737f +Ccap@2 gnd net@11 0.737f +Rres@0 net@14 a 1.161 +Rres@1 net@11 net@14 2.322 +Rres@2 b net@8 1.161 +Rres@3 net@8 net@11 2.322 +.ENDS wire-C_0_011f-200_9-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1301_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1301_9-R_34_667m -.ENDS wire90-1301_9-layer_1-width_3 +.SUBCKT wire90-200_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-200_9-R_34_667m +.ENDS wire90-200_9-layer_1-width_3 -*** CELL: stepsM:altStartStep{sch} -.SUBCKT altStartStep in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] mc outA[10] outA[11] outA[12] outA[13] -+outA[14] outA[15] outA[16] outA[17] outA[18] outA[19] outA[1] outA[20] -+outA[21] outA[22] outA[23] outA[24] outA[25] outA[26] outA[27] outA[28] -+outA[29] outA[2] outA[30] outA[31] outA[32] outA[33] outA[34] outA[35] -+outA[36] outA[3] outA[4] outA[5] outA[6] outA[7] outA[8] outA[9] outB[10] -+outB[11] outB[12] outB[13] outB[14] outB[15] outB[16] outB[17] outB[18] -+outB[19] outB[1] outB[20] outB[21] outB[22] outB[23] outB[24] outB[25] -+outB[26] outB[27] outB[28] outB[29] outB[2] outB[30] outB[31] outB[32] -+outB[33] outB[34] outB[35] outB[36] outB[3] outB[4] outB[5] outB[6] outB[7] -+outB[8] outB[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] -+sor[1] succA succB -XanAltSta@0 fire[A] fire[B] mc pred s[1] s[2] succA succB anAltStart -XlatchDri@0 net@5 net@20 latchDriver60 -XlatchDri@1 net@6 net@22 latchDriver60 -XscanEx1v@0 s[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] -+net@29[8] scanEx1vertA -XscanEx1v@1 s[2] mc net@29[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertA -Xshort30B@0 net@23 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] outA[10] outA[11] outA[12] outA[13] -+outA[14] outA[15] outA[16] outA[17] outA[18] outA[19] outA[1] outA[20] -+outA[21] outA[22] outA[23] outA[24] outA[25] outA[26] outA[27] outA[28] -+outA[29] outA[2] outA[30] outA[31] outA[32] outA[33] outA[34] outA[35] -+outA[36] outA[3] outA[4] outA[5] outA[6] outA[7] outA[8] outA[9] short20Bx36 -Xshort30B@1 net@25 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] outB[10] outB[11] outB[12] outB[13] -+outB[14] outB[15] outB[16] outB[17] outB[18] outB[19] outB[1] outB[20] -+outB[21] outB[22] outB[23] outB[24] outB[25] outB[26] outB[27] outB[28] -+outB[29] outB[2] outB[30] outB[31] outB[32] outB[33] outB[34] outB[35] -+outB[36] outB[3] outB[4] outB[5] outB[6] outB[7] outB[8] outB[9] short20Bx36 -Xwire90@0 fire[A] net@5 wire90-1300-layer_1-width_3 -Xwire90@1 fire[B] net@6 wire90-1301_9-layer_1-width_3 -Xwire90@2 net@20 net@23 wire90-1300-layer_1-width_3 -Xwire90@3 net@22 net@25 wire90-1300-layer_1-width_3 -.ENDS altStartStep +*** CELL: latchesK:mlat2in10i{sch} +.SUBCKT mlat2in10i clA[F] clA[T] clB[F] clB[T] inA inB out[1] +Xinv@0 out[1] net@33 inv-X_4 +Xnms2@0 out[1] inB clB[T] nms2-X_10 +Xnms2@1 out[1] inA clA[T] nms2-X_10 +Xnms3@0 out[1] clB[F] clA[F] net@33 nms3-X_2 +Xpms2@0 out[1] inB clB[F] pms2-X_10 +Xpms2@1 out[1] inA clA[F] pms2-X_10 +Xpms3@0 out[1] clA[T] clB[T] net@81 pms3-X_1 +Xwire90@1 net@81 net@33 wire90-200_9-layer_1-width_3 +.ENDS mlat2in10i *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-291_8-R_34_667m a b -Ccap@0 gnd net@14 1.07f -Ccap@1 gnd net@8 1.07f -Ccap@2 gnd net@11 1.07f -Rres@0 net@14 a 1.686 -Rres@1 net@11 net@14 3.372 -Rres@2 b net@8 1.686 -Rres@3 net@8 net@11 3.372 -.ENDS wire-C_0_011f-291_8-R_34_667m +.SUBCKT wire-C_0_011f-173_2-R_34_667m a b +Ccap@0 gnd net@14 0.635f +Ccap@1 gnd net@8 0.635f +Ccap@2 gnd net@11 0.635f +Rres@0 net@14 a 1.001 +Rres@1 net@11 net@14 2.001 +Rres@2 b net@8 1.001 +Rres@3 net@8 net@11 2.001 +.ENDS wire-C_0_011f-173_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-291_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-291_8-R_34_667m -.ENDS wire90-291_8-layer_1-width_3 - -*** CELL: gaspL:aStage{sch} -.SUBCKT aStage fire mc pred s[1] succ -XctrAND2i@4 net@494 succ fire ctrAND2in30 -Xinv@4 net@987 s[1] inv-X_10 -Xinv@5 pred net@987 inv-X_5 -XpredDri2@1 fire mc pred predDri20wMC -XsucDri20@1 fire succ sucDri20 -Xwire90@0 net@987 net@494 wire90-291_8-layer_1-width_3 -.ENDS aStage +.SUBCKT wire90-173_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-173_2-R_34_667m +.ENDS wire90-173_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-4997_2-R_34_667m a b -Ccap@0 gnd net@14 18.323f -Ccap@1 gnd net@8 18.323f -Ccap@2 gnd net@11 18.323f -Rres@0 net@14 a 28.873 -Rres@1 net@11 net@14 57.745 -Rres@2 b net@8 28.873 -Rres@3 net@8 net@11 57.745 -.ENDS wire-C_0_011f-4997_2-R_34_667m +.SUBCKT wire-C_0_011f-381_1-R_34_667m a b +Ccap@0 gnd net@14 1.397f +Ccap@1 gnd net@8 1.397f +Ccap@2 gnd net@11 1.397f +Rres@0 net@14 a 2.202 +Rres@1 net@11 net@14 4.404 +Rres@2 b net@8 2.202 +Rres@3 net@8 net@11 4.404 +.ENDS wire-C_0_011f-381_1-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-4997_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-4997_2-R_34_667m -.ENDS wire90-4997_2-layer_1-width_3 +.SUBCKT wire90-381_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-381_1-R_34_667m +.ENDS wire90-381_1-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-791_7-R_34_667m a b -Ccap@0 gnd net@14 2.903f -Ccap@1 gnd net@8 2.903f -Ccap@2 gnd net@11 2.903f -Rres@0 net@14 a 4.574 -Rres@1 net@11 net@14 9.149 -Rres@2 b net@8 4.574 -Rres@3 net@8 net@11 9.149 -.ENDS wire-C_0_011f-791_7-R_34_667m +.SUBCKT wire-C_0_011f-981_4-R_34_667m a b +Ccap@0 gnd net@14 3.598f +Ccap@1 gnd net@8 3.598f +Ccap@2 gnd net@11 3.598f +Rres@0 net@14 a 5.67 +Rres@1 net@11 net@14 11.341 +Rres@2 b net@8 5.67 +Rres@3 net@8 net@11 11.341 +.ENDS wire-C_0_011f-981_4-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-791_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-791_7-R_34_667m -.ENDS wire90-791_7-layer_1-width_3 +.SUBCKT wire90-981_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-981_4-R_34_667m +.ENDS wire90-981_4-layer_1-width_3 -*** CELL: stepsM:shortStep{sch} -.SUBCKT shortStep in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] mc out[10] out[11] out[12] out[13] -+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] -+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] -+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] -+out[6] out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sir[9] sor[1] succ take[1] -XaStage@0 net@1 mc pred net@17 succ aStage -XlatchDri@0 fire[1] take[1] latchDriver60 -XscanEx1v@0 net@17 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertA -Xshort30B@0 net@9 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] -+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] -+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] -+out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] -+out[7] out[8] out[9] short20Bx36 -Xwire90@0 net@9 take[1] wire90-4997_2-layer_1-width_3 -Xwire90@1 net@1 fire[1] wire90-791_7-layer_1-width_3 -.ENDS shortStep +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-523_4-R_34_667m a b +Ccap@0 gnd net@14 1.919f +Ccap@1 gnd net@8 1.919f +Ccap@2 gnd net@11 1.919f +Rres@0 net@14 a 3.024 +Rres@1 net@11 net@14 6.048 +Rres@2 b net@8 3.024 +Rres@3 net@8 net@11 6.048 +.ENDS wire-C_0_011f-523_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-523_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-523_4-R_34_667m +.ENDS wire90-523_4-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-838-R_34_667m a b -Ccap@0 gnd net@14 3.073f -Ccap@1 gnd net@8 3.073f -Ccap@2 gnd net@11 3.073f -Rres@0 net@14 a 4.842 -Rres@1 net@11 net@14 9.684 -Rres@2 b net@8 4.842 -Rres@3 net@8 net@11 9.684 -.ENDS wire-C_0_011f-838-R_34_667m +.SUBCKT wire-C_0_011f-535_1-R_34_667m a b +Ccap@0 gnd net@14 1.962f +Ccap@1 gnd net@8 1.962f +Ccap@2 gnd net@11 1.962f +Rres@0 net@14 a 3.092 +Rres@1 net@11 net@14 6.183 +Rres@2 b net@8 3.092 +Rres@3 net@8 net@11 6.183 +.ENDS wire-C_0_011f-535_1-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-838-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-838-R_34_667m -.ENDS wire90-838-layer_1-width_3 +.SUBCKT wire90-535_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-535_1-R_34_667m +.ENDS wire90-535_1-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1014-R_34_667m a b -Ccap@0 gnd net@14 3.718f -Ccap@1 gnd net@8 3.718f -Ccap@2 gnd net@11 3.718f -Rres@0 net@14 a 5.859 -Rres@1 net@11 net@14 11.717 -Rres@2 b net@8 5.859 -Rres@3 net@8 net@11 11.717 -.ENDS wire-C_0_011f-1014-R_34_667m +.SUBCKT wire-C_0_011f-555_1-R_34_667m a b +Ccap@0 gnd net@14 2.035f +Ccap@1 gnd net@8 2.035f +Ccap@2 gnd net@11 2.035f +Rres@0 net@14 a 3.207 +Rres@1 net@11 net@14 6.414 +Rres@2 b net@8 3.207 +Rres@3 net@8 net@11 6.414 +.ENDS wire-C_0_011f-555_1-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1014-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1014-R_34_667m -.ENDS wire90-1014-layer_1-width_3 +.SUBCKT wire90-555_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-555_1-R_34_667m +.ENDS wire90-555_1-layer_1-width_3 -*** CELL: stepsM:threeStepU{sch} -.SUBCKT threeStepU in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] mc out[10] out[11] out[12] out[13] -+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] -+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] -+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] -+out[6] out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sir[9] sor[1] succ take[1] -XshortSte@0 net@34[26] net@34[25] net@34[24] net@34[23] net@34[22] net@34[21] -+net@34[20] net@34[19] net@34[18] net@34[17] net@34[35] net@34[16] net@34[15] -+net@34[14] net@34[13] net@34[12] net@34[11] net@34[10] net@34[9] net@34[8] -+net@34[7] net@34[34] net@34[6] net@34[5] net@34[4] net@34[3] net@34[2] -+net@34[1] net@34[0] net@34[33] net@34[32] net@34[31] net@34[30] net@34[29] -+net@34[28] net@34[27] mc net@15[26] net@15[25] net@15[24] net@15[23] -+net@15[22] net@15[21] net@15[20] net@15[19] net@15[18] net@15[17] net@15[35] -+net@15[16] net@15[15] net@15[14] net@15[13] net@15[12] net@15[11] net@15[10] -+net@15[9] net@15[8] net@15[7] net@15[34] net@15[6] net@15[5] net@15[4] -+net@15[3] net@15[2] net@15[1] net@15[0] net@15[33] net@15[32] net@15[31] -+net@15[30] net@15[29] net@15[28] net@15[27] net@20 net@35[8] sir[2] sir[3] -+sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@36[8] net@21 take[1] shortStep -XshortSte@1 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] -+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] -+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] -+in[5] in[6] in[7] in[8] in[9] mc net@34[26] net@34[25] net@34[24] net@34[23] -+net@34[22] net@34[21] net@34[20] net@34[19] net@34[18] net@34[17] net@34[35] -+net@34[16] net@34[15] net@34[14] net@34[13] net@34[12] net@34[11] net@34[10] -+net@34[9] net@34[8] net@34[7] net@34[34] net@34[6] net@34[5] net@34[4] -+net@34[3] net@34[2] net@34[1] net@34[0] net@34[33] net@34[32] net@34[31] -+net@34[30] net@34[29] net@34[28] net@34[27] pred sir[1] sir[2] sir[3] sir[4] -+sir[5] sir[6] sir[7] sir[8] sir[9] net@35[8] net@19 shortSte@1_take[1] -+shortStep -XshortSte@2 net@15[26] net@15[25] net@15[24] net@15[23] net@15[22] net@15[21] -+net@15[20] net@15[19] net@15[18] net@15[17] net@15[35] net@15[16] net@15[15] -+net@15[14] net@15[13] net@15[12] net@15[11] net@15[10] net@15[9] net@15[8] -+net@15[7] net@15[34] net@15[6] net@15[5] net@15[4] net@15[3] net@15[2] -+net@15[1] net@15[0] net@15[33] net@15[32] net@15[31] net@15[30] net@15[29] -+net@15[28] net@15[27] mc out[10] out[11] out[12] out[13] out[14] out[15] -+out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] -+out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] -+out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] out[7] -+out[8] out[9] net@22 net@36[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sir[9] sor[1] succ shortSte@2_take[1] shortStep -Xwire90@0 net@19 net@20 wire90-838-layer_1-width_3 -Xwire90@1 net@21 net@22 wire90-1014-layer_1-width_3 -.ENDS threeStepU - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1303_4-R_34_667m a b -Ccap@0 gnd net@14 4.779f -Ccap@1 gnd net@8 4.779f -Ccap@2 gnd net@11 4.779f -Rres@0 net@14 a 7.531 -Rres@1 net@11 net@14 15.062 -Rres@2 b net@8 7.531 -Rres@3 net@8 net@11 15.062 -.ENDS wire-C_0_011f-1303_4-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1303_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1303_4-R_34_667m -.ENDS wire90-1303_4-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1588_4-R_34_667m a b -Ccap@0 gnd net@14 5.824f -Ccap@1 gnd net@8 5.824f -Ccap@2 gnd net@11 5.824f -Rres@0 net@14 a 9.177 -Rres@1 net@11 net@14 18.355 -Rres@2 b net@8 9.177 -Rres@3 net@8 net@11 18.355 -.ENDS wire-C_0_011f-1588_4-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1588_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1588_4-R_34_667m -.ENDS wire90-1588_4-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1022_3-R_34_667m a b -Ccap@0 gnd net@14 3.748f -Ccap@1 gnd net@8 3.748f -Ccap@2 gnd net@11 3.748f -Rres@0 net@14 a 5.907 -Rres@1 net@11 net@14 11.813 -Rres@2 b net@8 5.907 -Rres@3 net@8 net@11 11.813 -.ENDS wire-C_0_011f-1022_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1022_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1022_3-R_34_667m -.ENDS wire90-1022_3-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1873_3-R_34_667m a b -Ccap@0 gnd net@14 6.869f -Ccap@1 gnd net@8 6.869f -Ccap@2 gnd net@11 6.869f -Rres@0 net@14 a 10.824 -Rres@1 net@11 net@14 21.647 -Rres@2 b net@8 10.824 -Rres@3 net@8 net@11 21.647 -.ENDS wire-C_0_011f-1873_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1873_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1873_3-R_34_667m -.ENDS wire90-1873_3-layer_1-width_3 - -*** CELL: stepsM:splitStep9{sch} -.SUBCKT splitStep9 freqOut in[10] in[11] in[12] in[13] in[14] in[15] in[16] -+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] -+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] -+in[3] in[4] in[5] in[6] in[7] in[8] in[9] mc out[10] out[11] out[12] out[13] -+out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] -+out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] -+out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] -+out[6] out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sor[1] succ -XaltEndSt@0 net@35[26] net@35[25] net@35[24] net@35[23] net@35[22] net@35[21] -+net@35[20] net@35[19] net@35[18] net@35[17] net@35[35] net@35[16] net@35[15] -+net@35[14] net@35[13] net@35[12] net@35[11] net@35[10] net@35[9] net@35[8] -+net@35[7] net@35[34] net@35[6] net@35[5] net@35[4] net@35[3] net@35[2] -+net@35[1] net@35[0] net@35[33] net@35[32] net@35[31] net@35[30] net@35[29] -+net@35[28] net@35[27] net@26[26] net@26[25] net@26[24] net@26[23] net@26[22] -+net@26[21] net@26[20] net@26[19] net@26[18] net@26[17] net@26[35] net@26[16] -+net@26[15] net@26[14] net@26[13] net@26[12] net@26[11] net@26[10] net@26[9] -+net@26[8] net@26[7] net@26[34] net@26[6] net@26[5] net@26[4] net@26[3] -+net@26[2] net@26[1] net@26[0] net@26[33] net@26[32] net@26[31] net@26[30] -+net@26[29] net@26[28] net@26[27] mc out[10] out[11] out[12] out[13] out[14] -+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] -+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] -+out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] -+out[7] out[8] out[9] net@9 net@10 net@80[8] sir[2] sir[3] sir[4] sir[5] -+sir[6] sir[7] sir[8] mc sor[1] succ altEndStep -XaltStart@1 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] -+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] -+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] -+in[5] in[6] in[7] in[8] in[9] mc net@59[26] net@59[25] net@59[24] net@59[23] -+net@59[22] net@59[21] net@59[20] net@59[19] net@59[18] net@59[17] net@59[35] -+net@59[16] net@59[15] net@59[14] net@59[13] net@59[12] net@59[11] net@59[10] -+net@59[9] net@59[8] net@59[7] net@59[34] net@59[6] net@59[5] net@59[4] -+net@59[3] net@59[2] net@59[1] net@59[0] net@59[33] net@59[32] net@59[31] -+net@59[30] net@59[29] net@59[28] net@59[27] net@23[26] net@23[25] net@23[24] -+net@23[23] net@23[22] net@23[21] net@23[20] net@23[19] net@23[18] net@23[17] -+net@23[35] net@23[16] net@23[15] net@23[14] net@23[13] net@23[12] net@23[11] -+net@23[10] net@23[9] net@23[8] net@23[7] net@23[34] net@23[6] net@23[5] -+net@23[4] net@23[3] net@23[2] net@23[1] net@23[0] net@23[33] net@23[32] -+net@23[31] net@23[30] net@23[29] net@23[28] net@23[27] pred net@73[8] sir[2] -+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] net@83[8] net@5 net@1 altStartStep -XthreeSte@0 net@23[26] net@23[25] net@23[24] net@23[23] net@23[22] net@23[21] -+net@23[20] net@23[19] net@23[18] net@23[17] net@23[35] net@23[16] net@23[15] -+net@23[14] net@23[13] net@23[12] net@23[11] net@23[10] net@23[9] net@23[8] -+net@23[7] net@23[34] net@23[6] net@23[5] net@23[4] net@23[3] net@23[2] -+net@23[1] net@23[0] net@23[33] net@23[32] net@23[31] net@23[30] net@23[29] -+net@23[28] net@23[27] mc net@26[26] net@26[25] net@26[24] net@26[23] -+net@26[22] net@26[21] net@26[20] net@26[19] net@26[18] net@26[17] net@26[35] -+net@26[16] net@26[15] net@26[14] net@26[13] net@26[12] net@26[11] net@26[10] -+net@26[9] net@26[8] net@26[7] net@26[34] net@26[6] net@26[5] net@26[4] -+net@26[3] net@26[2] net@26[1] net@26[0] net@26[33] net@26[32] net@26[31] -+net@26[30] net@26[29] net@26[28] net@26[27] net@2 sir[1] sir[2] sir[3] sir[4] -+sir[5] sir[6] sir[7] sir[8] mc net@73[8] net@14 freqOut threeStepU -XthreeSte@1 net@59[26] net@59[25] net@59[24] net@59[23] net@59[22] net@59[21] -+net@59[20] net@59[19] net@59[18] net@59[17] net@59[35] net@59[16] net@59[15] -+net@59[14] net@59[13] net@59[12] net@59[11] net@59[10] net@59[9] net@59[8] -+net@59[7] net@59[34] net@59[6] net@59[5] net@59[4] net@59[3] net@59[2] -+net@59[1] net@59[0] net@59[33] net@59[32] net@59[31] net@59[30] net@59[29] -+net@59[28] net@59[27] mc net@35[26] net@35[25] net@35[24] net@35[23] -+net@35[22] net@35[21] net@35[20] net@35[19] net@35[18] net@35[17] net@35[35] -+net@35[16] net@35[15] net@35[14] net@35[13] net@35[12] net@35[11] net@35[10] -+net@35[9] net@35[8] net@35[7] net@35[34] net@35[6] net@35[5] net@35[4] -+net@35[3] net@35[2] net@35[1] net@35[0] net@35[33] net@35[32] net@35[31] -+net@35[30] net@35[29] net@35[28] net@35[27] net@4 net@83[8] sir[2] sir[3] -+sir[4] sir[5] sir[6] sir[7] sir[8] mc net@80[8] net@11 threeSte@1_take[1] -+threeStepU -Xwire90@0 net@1 net@2 wire90-1303_4-layer_1-width_3 -Xwire90@1 net@5 net@4 wire90-1588_4-layer_1-width_3 -Xwire90@2 net@11 net@9 wire90-1022_3-layer_1-width_3 -Xwire90@3 net@14 net@10 wire90-1873_3-layer_1-width_3 -.ENDS splitStep9 - -*** CELL: stepsM:shortRing{sch} -.SUBCKT shortRing do[L] do[M] fire[ODE] fire[m1] fire[m2] freqOut in[10] -+in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] -+in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] -+in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] -+in[9] in[T] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] -+m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] -+m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] -+m1[5] m1[6] m1[7] m1[8] m1[9] mc od[10] od[11] od[12] od[13] od[14] od[15] -+od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25] -+od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35] -+od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] olcZ pout[10] pout[11] -+pout[12] pout[13] pout[14] pout[15] pout[16] pout[17] pout[18] pout[1] -+pout[2] pout[3] pout[4] pout[5] pout[6] pout[7] pout[8] pout[9] pred sir[1] -+sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sor[1] torp -XepiStep@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] -+in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] -+in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] -+in[5] in[6] in[7] in[8] in[9] in[T] mc net@3[26] net@3[25] net@3[24] -+net@3[23] net@3[22] net@3[21] net@3[20] net@3[19] net@3[18] net@3[17] -+net@3[35] net@3[16] net@3[15] net@3[14] net@3[13] net@3[12] net@3[11] -+net@3[10] net@3[9] net@3[8] net@3[7] net@3[34] net@3[6] net@3[5] net@3[4] -+net@3[3] net@3[2] net@3[1] net@3[0] net@3[33] net@3[32] net@3[31] net@3[30] -+net@3[29] net@3[28] net@3[27] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] mc net@48[8] net@26 torp epiStep -Xm2m1step@0 do[M] fire[m1] fire[m2] pout[10] pout[11] pout[12] net@5[23] -+net@5[22] net@5[21] net@5[20] net@5[19] net@5[18] net@5[17] pout[1] net@5[16] -+net@5[15] net@5[14] net@5[13] net@5[12] net@5[11] net@5[10] net@5[9] net@5[8] -+net@5[7] pout[2] net@5[6] pout[13] pout[14] pout[15] pout[16] pout[17] -+pout[18] pout[3] pout[4] pout[5] pout[6] pout[7] pout[8] pout[9] m1[10] -+m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] -+m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] -+m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] -+m1[9] mc net@30 net@50[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] mc -+net@51[8] net@31[1] net@31[0] m2m1step -XreQstep@0 net@32 net@26 net@29 net@3[26] net@3[25] net@3[24] net@3[23] -+net@3[22] net@3[21] net@3[20] net@3[19] net@3[18] net@3[17] net@3[35] -+net@3[16] net@3[15] net@3[14] net@3[13] net@3[12] net@3[11] net@3[10] -+net@3[9] net@3[8] net@3[7] net@3[34] net@3[6] net@3[5] net@3[4] net@3[3] -+net@3[2] net@3[1] net@3[0] net@3[33] net@3[32] net@3[31] net@3[30] net@3[29] -+net@3[28] net@3[27] net@11[26] net@11[25] net@11[24] net@11[23] net@11[22] -+net@11[21] net@11[20] net@11[19] net@11[18] net@11[17] net@11[35] net@11[16] -+olcZ net@11[14] net@11[13] net@11[12] net@11[11] net@11[10] net@11[9] -+net@11[8] net@11[7] net@11[34] net@11[6] net@11[5] net@11[4] net@11[3] -+net@11[2] net@11[1] net@11[0] net@11[33] net@11[32] net@11[31] net@11[30] -+net@11[29] net@11[28] net@11[27] mc net@4[26] net@4[25] net@4[24] net@4[23] -+net@4[22] net@4[21] net@4[20] net@4[19] net@4[18] net@4[17] net@4[35] -+net@4[16] net@4[15] net@4[14] net@4[13] net@4[12] net@4[11] net@4[10] -+net@4[9] net@4[8] net@4[7] net@4[34] net@4[6] net@4[5] net@4[4] net@4[3] -+net@4[2] net@4[1] net@4[0] net@4[33] net@4[32] net@4[31] net@4[30] net@4[29] -+net@4[28] net@4[27] net@48[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] mc net@49[8] reQstep -XshortODs@0 do[L] do[M] net@32 fire[ODE] m1[10] m1[11] m1[12] m1[13] m1[14] -+m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] -+m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] -+m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc od[10] od[11] -+od[12] od[13] od[14] od[15] od[16] od[17] od[18] od[19] od[1] od[20] od[21] -+od[22] od[23] od[24] od[25] od[26] od[27] od[28] od[29] od[2] od[30] od[31] -+od[32] od[33] od[34] od[35] od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] -+olcZ net@11[26] net@11[25] net@11[24] net@11[23] net@11[22] net@11[21] -+net@11[20] net@11[19] net@11[18] net@11[17] net@11[35] net@11[16] net@11[14] -+net@11[13] net@11[12] net@11[11] net@11[10] net@11[9] net@11[8] net@11[7] -+net@11[34] net@11[6] net@11[5] net@11[4] net@11[3] net@11[2] net@11[1] -+net@11[0] net@11[33] net@11[32] net@11[31] net@11[30] net@11[29] net@11[28] -+net@11[27] net@31[1] net@51[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] mc sor[1] net@31[0] shortODstep -XsplitSte@2 freqOut net@4[26] net@4[25] net@4[24] net@4[23] net@4[22] -+net@4[21] net@4[20] net@4[19] net@4[18] net@4[17] net@4[35] net@4[16] -+net@4[15] net@4[14] net@4[13] net@4[12] net@4[11] net@4[10] net@4[9] net@4[8] -+net@4[7] net@4[34] net@4[6] net@4[5] net@4[4] net@4[3] net@4[2] net@4[1] -+net@4[0] net@4[33] net@4[32] net@4[31] net@4[30] net@4[29] net@4[28] -+net@4[27] mc pout[10] pout[11] pout[12] net@5[23] net@5[22] net@5[21] -+net@5[20] net@5[19] net@5[18] net@5[17] pout[1] net@5[16] net@5[15] net@5[14] -+net@5[13] net@5[12] net@5[11] net@5[10] net@5[9] net@5[8] net@5[7] pout[2] -+net@5[6] pout[13] pout[14] pout[15] pout[16] pout[17] pout[18] pout[3] -+pout[4] pout[5] pout[6] pout[7] pout[8] pout[9] net@29 net@49[8] sir[2] -+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] net@50[8] net@30 splitStep9 -.ENDS shortRing +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-677_1-R_34_667m a b +Ccap@0 gnd net@14 2.483f +Ccap@1 gnd net@8 2.483f +Ccap@2 gnd net@11 2.483f +Rres@0 net@14 a 3.912 +Rres@1 net@11 net@14 7.824 +Rres@2 b net@8 3.912 +Rres@3 net@8 net@11 7.824 +.ENDS wire-C_0_011f-677_1-R_34_667m -*** CELL: driversL:predCond20wMC{sch} -.SUBCKT predCond20wMC cond in mc pred -XNMOSx@1 pred mc gnd NMOSx-X_10 -Xinv@0 pred net@145 inv-X_10 -Xnms2@0 pred cond in nms2-X_20 -Xpms3@0 pred mc in net@186 pms3-X_1 -Xwire90@0 net@186 net@145 wire90-243_6-layer_1-width_3 -.ENDS predCond20wMC +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-677_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-677_1-R_34_667m +.ENDS wire90-677_1-layer_1-width_3 -*** CELL: dockPartsK:moveD{sch} -.SUBCKT moveD fire[M] mc od[15] od[16] od[18] od[19] pred[D] pred[T] s[1] -+s[2] succ[D] succ[T] -Xinv@0 pred[T] net@294 inv-X_5 -Xinv@1 pred[D] net@295 inv-X_5 -Xinv@2 net@298 s[1] inv-X_10 -Xinv@3 net@303 s[2] inv-X_10 -XpredCond@3 od[18] fire[M] mc pred[D] predCond20wMC -XpredCond@4 od[19] fire[M] mc pred[T] predCond20wMC -XsucANDdr@3 od[16] fire[M] succ[D] sucANDdri20 -XsucANDdr@4 od[15] fire[M] succ[T] sucANDdri20 -Xwire90@0 net@303 net@294 wire90-243_6-layer_1-width_3 -Xwire90@1 net@298 net@295 wire90-243_6-layer_1-width_3 -.ENDS moveD - -*** CELL: redFour:nand2LT_sy{sch} -.SUBCKT nand2LT_sy-X_10 ina inb out -XPMOS@0 out ina vdd PMOSx-X_5 -XPMOS@1 out inb vdd PMOSx-X_5 -Xnms2_sy@0 out ina inb nms2_sy-X_10 -.ENDS nand2LT_sy-X_10 +*** CELL: loopCountM:ringB{sch} +.SUBCKT ringB bit[1] count[F] count[T] do[1] inLO[1] load[F] load[T] +Xinv@0 net@60 bit[1] inv-X_20 +Xinv@1 bit[1] net@67 inv-X_5 +Xinv@2 net@68 net@65 inv-X_10 +Xinv@3 xx[T] net@64 inv-X_10 +Xmlat1in5@0 xx[T] xx[F] net@66 net@9 mlat1in5i +Xmlat1in5@1 count[T] count[F] do[1] net@77 mlat1in5i +Xmlat2in1@0 load[F] load[T] xx[F] xx[T] inLO[1] net@63 net@61 mlat2in10i +Xnor2n@0 net@78 count[F] net@84 nor2n-X_10 +Xwire90@1 net@67 net@68 wire90-173_2-layer_1-width_3 +Xwire90@2 net@65 net@66 wire90-381_1-layer_1-width_3 +Xwire90@3 net@60 net@61 wire90-981_4-layer_1-width_3 +Xwire90@5 net@63 net@9 wire90-523_4-layer_1-width_3 +Xwire90@6 net@64 xx[F] wire90-535_1-layer_1-width_3 +Xwire90@7 net@77 net@78 wire90-555_1-layer_1-width_3 +Xwire90@8 net@84 xx[T] wire90-677_1-layer_1-width_3 +.ENDS ringB -*** CELL: redFour:nor2n_sy{sch} -.SUBCKT nor2n_sy-X_5 ina inb out -Xnor2@0 ina inb out nor2_sy-X_5 -.ENDS nor2n_sy-X_5 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-2064_2-R_34_667m a b +Ccap@0 gnd net@14 7.569f +Ccap@1 gnd net@8 7.569f +Ccap@2 gnd net@11 7.569f +Rres@0 net@14 a 11.926 +Rres@1 net@11 net@14 23.853 +Rres@2 b net@8 11.926 +Rres@3 net@8 net@11 23.853 +.ENDS wire-C_0_011f-2064_2-R_34_667m -*** CELL: centersJ:ctrAND3in30B{sch} -.SUBCKT ctrAND3in30B inA inB inC out -Xinv@4 inC net@30 inv-X_5 -Xinv@5 net@9 out inv-X_30 -Xnand2LT_@0 net@15 net@19 net@27 nand2LT_sy-X_10 -Xnor2n_sy@0 inA inB net@6 nor2n_sy-X_5 -Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3 -Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3 -Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3 -.ENDS ctrAND3in30B +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-2064_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-2064_2-R_34_667m +.ENDS wire90-2064_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-414-R_34_667m a b -Ccap@0 gnd net@14 1.518f -Ccap@1 gnd net@8 1.518f -Ccap@2 gnd net@11 1.518f -Rres@0 net@14 a 2.392 -Rres@1 net@11 net@14 4.784 -Rres@2 b net@8 2.392 -Rres@3 net@8 net@11 4.784 -.ENDS wire-C_0_011f-414-R_34_667m +.SUBCKT wire-C_0_011f-1795_1-R_34_667m a b +Ccap@0 gnd net@14 6.582f +Ccap@1 gnd net@8 6.582f +Ccap@2 gnd net@11 6.582f +Rres@0 net@14 a 10.372 +Rres@1 net@11 net@14 20.743 +Rres@2 b net@8 10.372 +Rres@3 net@8 net@11 20.743 +.ENDS wire-C_0_011f-1795_1-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-414-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-414-R_34_667m -.ENDS wire90-414-layer_1-width_3 +.SUBCKT wire90-1795_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1795_1-R_34_667m +.ENDS wire90-1795_1-layer_1-width_3 -*** CELL: fifoL:litStage{sch} -.SUBCKT litStage do[L] fire[L] mc s[1] succ[D] succ[T] -XctrAND3i@0 succ[T] succ[D] net@54 fire[L] ctrAND3in30B -Xinv@0 net@54 s[1] inv-X_10 -Xinv@1 do[L] net@190 inv-X_5 -XpredDri2@1 fire[L] mc do[L] predDri20wMC -Xwire90@1 net@190 net@54 wire90-414-layer_1-width_3 -.ENDS litStage +*** CELL: loopCountM:ilcEven{sch} +.SUBCKT ilcEven bit[2] bit[4] bit[6] bit[8] count[T] do[2] do[4] do[6] ++inLO[2] inLO[4] inLO[6] inLO[8] load[T] +Xinv@7 count[T] net@273 inv-X_30 +Xinv@8 load[T] net@275 inv-X_30 +Xmlat1in1@1 load[F] load[T] inLO[8] bit[8] mlat1in10 +XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB +XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB +XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB +Xwire90@8 net@273 count[F] wire90-2064_2-layer_1-width_3 +Xwire90@9 net@275 load[F] wire90-1795_1-layer_1-width_3 +.ENDS ilcEven -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_25 d g s -MPMOSf@0 d g s vdd pch W='150*(1+ABP/sqrt(150*2))' L='2' -+DELVTO='AVT0P/sqrt(150*2)' -.ENDS PMOSx-X_25 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-2344-R_34_667m a b +Ccap@0 gnd net@14 8.595f +Ccap@1 gnd net@8 8.595f +Ccap@2 gnd net@11 8.595f +Rres@0 net@14 a 13.543 +Rres@1 net@11 net@14 27.086 +Rres@2 b net@8 13.543 +Rres@3 net@8 net@11 27.086 +.ENDS wire-C_0_011f-2344-R_34_667m -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_50 d g s -MNMOSf@0 d g s gnd nch W='150*(1+ABN/sqrt(150*2))' L='2' -+DELVTO='AVT0N/sqrt(150*2)' -.ENDS NMOSx-X_50 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-2344-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-2344-R_34_667m +.ENDS wire90-2344-layer_1-width_3 -*** CELL: redFour:nms2{sch} -.SUBCKT nms2-X_25 d g g2 -XNMOS@0 d g2 net@0 NMOSx-X_50 -XNMOS@1 net@0 g gnd NMOSx-X_50 -.ENDS nms2-X_25 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1810_4-R_34_667m a b +Ccap@0 gnd net@14 6.638f +Ccap@1 gnd net@8 6.638f +Ccap@2 gnd net@11 6.638f +Rres@0 net@14 a 10.46 +Rres@1 net@11 net@14 20.92 +Rres@2 b net@8 10.46 +Rres@3 net@8 net@11 20.92 +.ENDS wire-C_0_011f-1810_4-R_34_667m -*** CELL: redFour:nand2{sch} -.SUBCKT nand2-X_25 ina inb out -XPMOS@0 out ina vdd PMOSx-X_25 -XPMOS@1 out inb vdd PMOSx-X_25 -Xnms2@0 out ina inb nms2-X_25 -.ENDS nand2-X_25 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1810_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1810_4-R_34_667m +.ENDS wire90-1810_4-layer_1-width_3 -*** CELL: arbiterK:half2inArb{sch} -.SUBCKT half2inArb cross grant[B] inA req[B] -XNMOSx@0 vdd req[B] grant[B] PMOSx-X_10 -XPMOSx@0 cross inA grant[B] NMOSx-X_10 -Xnor2n@0 inA req[B] cross nand2-X_25 -.ENDS half2inArb +*** CELL: loopCountM:ilcOdd{sch} +.SUBCKT ilcOdd bit[1] bit[3] bit[5] bit[7] check[T] count[T] do[3] do[5] ++do[7] inLO[1] inLO[3] inLO[5] load[T] +Xinv@5 count[T] net@273 inv-X_30 +Xinv@6 load[T] net@275 inv-X_30 +Xinv@7 check[T] net@441 inv-X_5 +Xmlat2in1@1 load[F] load[T] check[F] check[T] gnd do[7] bit[7] mlat2in10i +XringB@3 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB +XringB@4 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB +XringB@5 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB +Xwire90@4 net@273 count[F] wire90-2344-layer_1-width_3 +Xwire90@5 net@275 load[F] wire90-1810_4-layer_1-width_3 +Xwire90@6 net@441 check[F] wire90-2344-layer_1-width_3 +.ENDS ilcOdd *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-830_7-R_34_667m a b -Ccap@0 gnd net@14 3.046f -Ccap@1 gnd net@8 3.046f -Ccap@2 gnd net@11 3.046f -Rres@0 net@14 a 4.8 -Rres@1 net@11 net@14 9.599 -Rres@2 b net@8 4.8 -Rres@3 net@8 net@11 9.599 -.ENDS wire-C_0_011f-830_7-R_34_667m +.SUBCKT wire-C_0_011f-374_2-R_34_667m a b +Ccap@0 gnd net@14 1.372f +Ccap@1 gnd net@8 1.372f +Ccap@2 gnd net@11 1.372f +Rres@0 net@14 a 2.162 +Rres@1 net@11 net@14 4.324 +Rres@2 b net@8 2.162 +Rres@3 net@8 net@11 4.324 +.ENDS wire-C_0_011f-374_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-830_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-830_7-R_34_667m -.ENDS wire90-830_7-layer_1-width_3 +.SUBCKT wire90-374_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-374_2-R_34_667m +.ENDS wire90-374_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-834_6-R_34_667m a b -Ccap@0 gnd net@14 3.06f -Ccap@1 gnd net@8 3.06f -Ccap@2 gnd net@11 3.06f -Rres@0 net@14 a 4.822 -Rres@1 net@11 net@14 9.644 -Rres@2 b net@8 4.822 -Rres@3 net@8 net@11 9.644 -.ENDS wire-C_0_011f-834_6-R_34_667m +.SUBCKT wire-C_0_011f-464_8-R_34_667m a b +Ccap@0 gnd net@14 1.704f +Ccap@1 gnd net@8 1.704f +Ccap@2 gnd net@11 1.704f +Rres@0 net@14 a 2.686 +Rres@1 net@11 net@14 5.371 +Rres@2 b net@8 2.686 +Rres@3 net@8 net@11 5.371 +.ENDS wire-C_0_011f-464_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-834_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-834_6-R_34_667m -.ENDS wire90-834_6-layer_1-width_3 - -*** CELL: arbiterK:arbiter2{sch} -.SUBCKT arbiter2 grant[A] grant[B] req[A] req[B] -XhalfArb@2 net@12 grant[A] net@5 req[A] half2inArb -XhalfArb@3 net@13 grant[B] net@8 req[B] half2inArb -Xwire90@0 net@12 net@8 wire90-830_7-layer_1-width_3 -Xwire90@1 net@5 net@13 wire90-834_6-layer_1-width_3 -.ENDS arbiter2 - -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_2 d g s -MPMOSf@0 d g s vdd pch W='12*(1+ABP/sqrt(12*2))' L='2' -+DELVTO='AVT0P/sqrt(12*2)' -.ENDS PMOSx-X_2 - -*** CELL: redFour:invLT{sch} -.SUBCKT invLT-X_2 in out -XNMOS@0 out in gnd NMOSx-X_4 -XPMOS@0 out in vdd PMOSx-X_2 -.ENDS invLT-X_2 - -*** CELL: redFour:pms2{sch} -.SUBCKT pms2-X_1 d g g2 -XPMOS@0 net@2 g vdd PMOSx-X_2 -XPMOS@1 d g2 net@2 PMOSx-X_2 -.ENDS pms2-X_1 +.SUBCKT wire90-464_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-464_8-R_34_667m +.ENDS wire90-464_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-133_8-R_34_667m a b -Ccap@0 gnd net@14 0.491f -Ccap@1 gnd net@8 0.491f -Ccap@2 gnd net@11 0.491f -Rres@0 net@14 a 0.773 -Rres@1 net@11 net@14 1.546 -Rres@2 b net@8 0.773 -Rres@3 net@8 net@11 1.546 -.ENDS wire-C_0_011f-133_8-R_34_667m +.SUBCKT wire-C_0_011f-398_8-R_34_667m a b +Ccap@0 gnd net@14 1.462f +Ccap@1 gnd net@8 1.462f +Ccap@2 gnd net@11 1.462f +Rres@0 net@14 a 2.304 +Rres@1 net@11 net@14 4.608 +Rres@2 b net@8 2.304 +Rres@3 net@8 net@11 4.608 +.ENDS wire-C_0_011f-398_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-133_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-133_8-R_34_667m -.ENDS wire90-133_8-layer_1-width_3 - -*** CELL: latchesK:mlat1in5i{sch} -.SUBCKT mlat1in5i c[F] c[T] in out -XinvLT@0 out net@119 invLT-X_2 -Xnms2@2 out in c[T] nms2-X_5 -Xnms2@3 out net@114 c[F] nms2-X_2 -Xpms2@0 out net@114 c[T] pms2-X_1 -Xpms2@1 out in c[F] pms2-X_5 -Xwire90@19 net@114 net@119 wire90-133_8-layer_1-width_3 -.ENDS mlat1in5i +.SUBCKT wire90-398_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-398_8-R_34_667m +.ENDS wire90-398_8-layer_1-width_3 -*** CELL: redFour:nor2{sch} -.SUBCKT nor2-X_20 ina inb out -XNMOS@0 out ina gnd NMOSx-X_20 -XNMOS@1 out inb gnd NMOSx-X_20 -Xpms2@0 out ina inb pms2-X_20 -.ENDS nor2-X_20 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-474_8-R_34_667m a b +Ccap@0 gnd net@14 1.741f +Ccap@1 gnd net@8 1.741f +Ccap@2 gnd net@11 1.741f +Rres@0 net@14 a 2.743 +Rres@1 net@11 net@14 5.487 +Rres@2 b net@8 2.743 +Rres@3 net@8 net@11 5.487 +.ENDS wire-C_0_011f-474_8-R_34_667m -*** CELL: redFour:nor2n{sch} -.SUBCKT nor2n-X_20 ina inb out -Xnor2@0 ina inb out nor2-X_20 -.ENDS nor2n-X_20 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-474_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-474_8-R_34_667m +.ENDS wire90-474_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-383_8-R_34_667m a b @@ -3469,50 +3433,399 @@ Rres@3 net@8 net@11 4.435 Xwire@0 a b wire-C_0_011f-383_8-R_34_667m .ENDS wire90-383_8-layer_1-width_3 -*** CELL: dockPartsK:moveE{sch} -.SUBCKT moveE exit fire[AE] fire[M] ilc[cnt] ilc[dLO] ilc[i] ilc[zLO] -+ilc[zoo] -Xinv@7 ilc[dLO] net@178 inv-X_10 -Xinv@8 ilc[i] net@228 inv-X_10 -Xinv@9 fire[AE] net@258 inv-X_10 -Xmlat1in5@0 xx fire[AE] net@183 net@202 mlat1in5i -Xmlat1in5@1 xx fire[AE] net@188 net@198 mlat1in5i -Xmlat1in5@2 xx fire[AE] ilc[zLO] net@209 mlat1in5i -Xnand2_sy@0 net@208 net@204 net@189 nand2_sy-X_10 -Xnor2_sy@1 ilc[i] net@200 net@195 nor2_sy-X_10 -Xnor2_sy@2 ilc[zoo] done net@181 nor2_sy-X_10 -Xnor2_sy@3 ilc[zLO] done net@185 nor2_sy-X_10 -Xnor2n@3 net@192 fire[AE] exit nor2n-X_20 -Xnor2n@5 net@220 fire[AE] fire[M] nor2n-X_20 -Xnor2n@9 net@212 fire[AE] ilc[cnt] nor2n-X_20 -Xwire90@3 net@178 done wire90-383_8-layer_1-width_3 -Xwire90@4 net@181 net@183 wire90-383_8-layer_1-width_3 -Xwire90@5 net@185 net@188 wire90-383_8-layer_1-width_3 -Xwire90@6 net@189 net@192 wire90-383_8-layer_1-width_3 -Xwire90@7 net@195 net@220 wire90-383_8-layer_1-width_3 -Xwire90@8 net@198 net@200 wire90-383_8-layer_1-width_3 -Xwire90@9 net@202 net@204 wire90-383_8-layer_1-width_3 -Xwire90@10 net@209 net@212 wire90-383_8-layer_1-width_3 -Xwire90@11 net@208 net@228 wire90-383_8-layer_1-width_3 -Xwire90@12 xx net@258 wire90-383_8-layer_1-width_3 -.ENDS moveE - -*** CELL: redFour:nand2n{sch} -.SUBCKT nand2n-X_10 ina inb out -Xnand2@0 ina inb out nand2-X_10 -.ENDS nand2n-X_10 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-399_8-R_34_667m a b +Ccap@0 gnd net@14 1.466f +Ccap@1 gnd net@8 1.466f +Ccap@2 gnd net@11 1.466f +Rres@0 net@14 a 2.31 +Rres@1 net@11 net@14 4.62 +Rres@2 b net@8 2.31 +Rres@3 net@8 net@11 4.62 +.ENDS wire-C_0_011f-399_8-R_34_667m -*** CELL: redFour:pms2{sch} -.SUBCKT pms2-X_1_5 d g g2 -XPMOS@0 net@2 g vdd PMOSx-X_3 -XPMOS@1 d g2 net@2 PMOSx-X_3 -.ENDS pms2-X_1_5 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-399_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-399_8-R_34_667m +.ENDS wire90-399_8-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-975_7-R_34_667m a b +Ccap@0 gnd net@14 3.578f +Ccap@1 gnd net@8 3.578f +Ccap@2 gnd net@11 3.578f +Rres@0 net@14 a 5.637 +Rres@1 net@11 net@14 11.275 +Rres@2 b net@8 5.637 +Rres@3 net@8 net@11 11.275 +.ENDS wire-C_0_011f-975_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-975_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-975_7-R_34_667m +.ENDS wire90-975_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1009_4-R_34_667m a b +Ccap@0 gnd net@14 3.701f +Ccap@1 gnd net@8 3.701f +Ccap@2 gnd net@11 3.701f +Rres@0 net@14 a 5.832 +Rres@1 net@11 net@14 11.664 +Rres@2 b net@8 5.832 +Rres@3 net@8 net@11 11.664 +.ENDS wire-C_0_011f-1009_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1009_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1009_4-R_34_667m +.ENDS wire90-1009_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-905_8-R_34_667m a b +Ccap@0 gnd net@14 3.321f +Ccap@1 gnd net@8 3.321f +Ccap@2 gnd net@11 3.321f +Rres@0 net@14 a 5.234 +Rres@1 net@11 net@14 10.467 +Rres@2 b net@8 5.234 +Rres@3 net@8 net@11 10.467 +.ENDS wire-C_0_011f-905_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-905_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-905_8-R_34_667m +.ENDS wire90-905_8-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-758_3-R_34_667m a b +Ccap@0 gnd net@14 2.78f +Ccap@1 gnd net@8 2.78f +Ccap@2 gnd net@11 2.78f +Rres@0 net@14 a 4.381 +Rres@1 net@11 net@14 8.763 +Rres@2 b net@8 4.381 +Rres@3 net@8 net@11 8.763 +.ENDS wire-C_0_011f-758_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-758_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-758_3-R_34_667m +.ENDS wire90-758_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-643_7-R_34_667m a b +Ccap@0 gnd net@14 2.36f +Ccap@1 gnd net@8 2.36f +Ccap@2 gnd net@11 2.36f +Rres@0 net@14 a 3.719 +Rres@1 net@11 net@14 7.438 +Rres@2 b net@8 3.719 +Rres@3 net@8 net@11 7.438 +.ENDS wire-C_0_011f-643_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-643_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-643_7-R_34_667m +.ENDS wire90-643_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-561_7-R_34_667m a b +Ccap@0 gnd net@14 2.06f +Ccap@1 gnd net@8 2.06f +Ccap@2 gnd net@11 2.06f +Rres@0 net@14 a 3.245 +Rres@1 net@11 net@14 6.491 +Rres@2 b net@8 3.245 +Rres@3 net@8 net@11 6.491 +.ENDS wire-C_0_011f-561_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-561_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-561_7-R_34_667m +.ENDS wire90-561_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-902_4-R_34_667m a b +Ccap@0 gnd net@14 3.309f +Ccap@1 gnd net@8 3.309f +Ccap@2 gnd net@11 3.309f +Rres@0 net@14 a 5.214 +Rres@1 net@11 net@14 10.428 +Rres@2 b net@8 5.214 +Rres@3 net@8 net@11 10.428 +.ENDS wire-C_0_011f-902_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-902_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-902_4-R_34_667m +.ENDS wire90-902_4-layer_1-width_3 + +*** CELL: loopCountM:ilc{sch} +.SUBCKT ilc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8] ++ilc[ck] ilc[decLO] ilc[do] ilc[ho] ilc[load] ilc[mo] inLO[1] inLO[2] inLO[3] ++inLO[4] inLO[5] inLO[6] inLO[8] +Xcalculat@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4] ++do[5] do[6] ilc[ho] do[7] calculate +XilcEven@0 bitt[2] bitt[4] bitt[6] bitt[8] net@88 do[2] do[4] do[6] inLO[2] ++inLO[4] inLO[6] inLO[8] ilc[load] ilcEven +XilcOdd@0 bitt[1] bitt[3] bitt[5] bitt[7] ilc[ck] net@88 do[3] do[5] do[7] ++inLO[1] inLO[3] inLO[5] ilc[load] ilcOdd +XinvI@0 ilc[decLO] net@88 inv-X_30 +Xnand2@0 bitt[8] do[7] ilc[mo] nand2-X_10 +Xnand3@0 bitt[8] bitt[7] ilc[ho] ilc[do] nand3-X_6_667 +Xwire90@1 wire90@1_a do[2] wire90-374_2-layer_1-width_3 +Xwire90@2 wire90@2_a do[3] wire90-464_8-layer_1-width_3 +Xwire90@3 wire90@3_a do[4] wire90-398_8-layer_1-width_3 +Xwire90@4 wire90@4_a do[5] wire90-474_8-layer_1-width_3 +Xwire90@5 wire90@5_a do[6] wire90-383_8-layer_1-width_3 +Xwire90@6 wire90@6_a do[7] wire90-399_8-layer_1-width_3 +Xwire90@7 wire90@7_a bitt[1] wire90-975_7-layer_1-width_3 +Xwire90@8 wire90@8_a bitt[2] wire90-1009_4-layer_1-width_3 +Xwire90@9 wire90@9_a bitt[3] wire90-905_8-layer_1-width_3 +Xwire90@10 wire90@10_a bitt[4] wire90-758_3-layer_1-width_3 +Xwire90@11 wire90@11_a bitt[5] wire90-643_7-layer_1-width_3 +Xwire90@12 wire90@12_a bitt[6] wire90-561_7-layer_1-width_3 +Xwire90@36 wire90@36_a bitt[7] wire90-902_4-layer_1-width_3 +.ENDS ilc + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-407_4-R_34_667m a b +Ccap@0 gnd net@14 1.494f +Ccap@1 gnd net@8 1.494f +Ccap@2 gnd net@11 1.494f +Rres@0 net@14 a 2.354 +Rres@1 net@11 net@14 4.708 +Rres@2 b net@8 2.354 +Rres@3 net@8 net@11 4.708 +.ENDS wire-C_0_011f-407_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-407_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-407_4-R_34_667m +.ENDS wire90-407_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-416_9-R_34_667m a b +Ccap@0 gnd net@14 1.529f +Ccap@1 gnd net@8 1.529f +Ccap@2 gnd net@11 1.529f +Rres@0 net@14 a 2.409 +Rres@1 net@11 net@14 4.818 +Rres@2 b net@8 2.409 +Rres@3 net@8 net@11 4.818 +.ENDS wire-C_0_011f-416_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-416_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-416_9-R_34_667m +.ENDS wire90-416_9-layer_1-width_3 + +*** CELL: arbiterM:mutex{sch} +.SUBCKT mutex in[A] in[B] out[A] out[B] reset[A] reset[B] +XNMOSx@2 gnd reset[A] net@0 NMOSx-X_4 +XNMOSx@3 net@1 reset[B] gnd NMOSx-X_4 +XPMOSx@0 net@0 net@1 in[A] PMOSx-X_20 +XPMOSx@4 net@1 net@0 in[B] PMOSx-X_20 +XPMOSx@5 out[B] net@33 net@1 PMOSx-X_20 +XPMOSx@6 out[A] net@35 net@0 PMOSx-X_20 +Xnms1@0 net@0 net@1 nms1-X_4 +Xnms1@2 net@1 net@0 nms1-X_4 +Xwire90@0 net@35 net@1 wire90-407_4-layer_1-width_3 +Xwire90@1 net@0 net@33 wire90-416_9-layer_1-width_3 +.ENDS mutex + +*** CELL: redFive:pms2{sch} +.SUBCKT pms2-X_30 d g g2 +XPMOS@0 net@2 g vdd PMOSx-X_60 +XPMOS@1 d g2 net@2 PMOSx-X_60 +.ENDS pms2-X_30 + +*** CELL: redFive:nor2{sch} +.SUBCKT nor2-X_30 ina inb out +XNMOS@0 out ina gnd NMOSx-X_30 +XNMOS@1 out inb gnd NMOSx-X_30 +Xpms2@0 out ina inb pms2-X_30 +.ENDS nor2-X_30 + +*** CELL: redFive:nor2n{sch} +.SUBCKT nor2n-X_30 ina inb out +Xnor2@0 ina inb out nor2-X_30 +.ENDS nor2n-X_30 + +*** CELL: arbiterM:outputNand{sch} +.SUBCKT outputNand inA inB out +XPMOSx@0 out inB vdd PMOSx-X_20 +XPMOSx@1 out inA vdd PMOSx-X_20 +Xnms2b@2 out inA inB nms2-X_20 +.ENDS outputNand + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-376-R_34_667m a b +Ccap@0 gnd net@14 1.379f +Ccap@1 gnd net@8 1.379f +Ccap@2 gnd net@11 1.379f +Rres@0 net@14 a 2.172 +Rres@1 net@11 net@14 4.345 +Rres@2 b net@8 2.172 +Rres@3 net@8 net@11 4.345 +.ENDS wire-C_0_011f-376-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-376-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-376-R_34_667m +.ENDS wire90-376-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-711_9-R_34_667m a b +Ccap@0 gnd net@14 2.61f +Ccap@1 gnd net@8 2.61f +Ccap@2 gnd net@11 2.61f +Rres@0 net@14 a 4.113 +Rres@1 net@11 net@14 8.226 +Rres@2 b net@8 4.113 +Rres@3 net@8 net@11 8.226 +.ENDS wire-C_0_011f-711_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-711_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-711_9-R_34_667m +.ENDS wire90-711_9-layer_1-width_3 + +*** CELL: arbiterM:meArbiter{sch} +.SUBCKT meArbiter in[A] in[B] out[A] out[B] req[A1] req[A2] req[B1] req[B2] +Xmutex@0 net@9 net@11 net@5 net@0 req[A1] req[B1] mutex +Xnms1@0 net@19 req[A2] nms1-X_4 +Xnms1@1 net@19 req[A1] nms1-X_4 +Xnms1@2 net@33 req[B1] nms1-X_4 +Xnms1@3 net@33 req[B2] nms1-X_4 +Xnor2n@0 req[A2] req[A1] net@13 nor2n-X_30 +Xnor2n@2 req[B2] req[B1] net@17 nor2n-X_30 +XoutputNa@0 in[A] net@19 out[A] outputNand +XoutputNa@1 in[B] net@33 out[B] outputNand +Xwire90@0 net@0 net@33 wire90-376-layer_1-width_3 +Xwire90@1 net@19 net@5 wire90-376-layer_1-width_3 +Xwire90@2 net@11 net@17 wire90-711_9-layer_1-width_3 +Xwire90@3 net@13 net@9 wire90-711_9-layer_1-width_3 +.ENDS meArbiter + +*** CELL: redFive:nand2{sch} +.SUBCKT nand2-X_20 ina inb out +XPMOS@0 out ina vdd PMOSx-X_20 +XPMOS@1 out inb vdd PMOSx-X_20 +Xnms2@0 out ina inb nms2-X_20 +.ENDS nand2-X_20 + +*** CELL: redFive:nor2{sch} +.SUBCKT nor2-X_5 ina inb out +XNMOS@0 out ina gnd NMOSx-X_5 +XNMOS@1 out inb gnd NMOSx-X_5 +Xpms2@0 out ina inb pms2-X_5 +.ENDS nor2-X_5 + +*** CELL: redFive:nor2n{sch} +.SUBCKT nor2n-X_5 ina inb out +Xnor2@0 ina inb out nor2-X_5 +.ENDS nor2n-X_5 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-495_9-R_34_667m a b +Ccap@0 gnd net@14 1.818f +Ccap@1 gnd net@8 1.818f +Ccap@2 gnd net@11 1.818f +Rres@0 net@14 a 2.865 +Rres@1 net@11 net@14 5.73 +Rres@2 b net@8 2.865 +Rres@3 net@8 net@11 5.73 +.ENDS wire-C_0_011f-495_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-495_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-495_9-R_34_667m +.ENDS wire90-495_9-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-224_6-R_34_667m a b +Ccap@0 gnd net@14 0.824f +Ccap@1 gnd net@8 0.824f +Ccap@2 gnd net@11 0.824f +Rres@0 net@14 a 1.298 +Rres@1 net@11 net@14 2.595 +Rres@2 b net@8 1.298 +Rres@3 net@8 net@11 2.595 +.ENDS wire-C_0_011f-224_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-224_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-224_6-R_34_667m +.ENDS wire90-224_6-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-222_9-R_34_667m a b +Ccap@0 gnd net@14 0.817f +Ccap@1 gnd net@8 0.817f +Ccap@2 gnd net@11 0.817f +Rres@0 net@14 a 1.288 +Rres@1 net@11 net@14 2.576 +Rres@2 b net@8 1.288 +Rres@3 net@8 net@11 2.576 +.ENDS wire-C_0_011f-222_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-222_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-222_9-R_34_667m +.ENDS wire90-222_9-layer_1-width_3 + +*** CELL: oneHotM:moveAnd{sch} +.SUBCKT moveAnd again bit[Di] bit[Ti] do[Mv] done[D] done[M] done[T] fire[M] ++ilc[ck] ilc[decLO] ilc[do] ilc[ho] ilc[mo] win[M] +Xinv@0 ilc[do] net@20 inv-X_5 +Xinv@1 net@49 net@52 inv-X_10 +Xinv@2 net@75 ilc[decLO] inv-X_20 +XinvI@0 win[M] net@46 inv-X_5 +XinvI@1 win[M] ilc[ck] inv-X_10 +Xnand2@0 ilc[do] bit[Di] net@66 nand2-X_5 +Xnand2@1 ilc[do] bit[Ti] net@70 nand2-X_5 +Xnand2@2 do[Mv] net@53 again nand2-X_20 +Xnor2n@0 skip win[M] fire[M] nor2n-X_20 +Xnor2n@1 ilc[mo] win[M] done[M] nor2n-X_5 +Xnor2n@2 net@64 win[M] done[D] nor2n-X_5 +Xnor2n@3 net@68 win[M] done[T] nor2n-X_5 +Xnor2n@4 ilc[ho] win[M] net@76 nor2n-X_5 +Xwire90@0 net@20 skip wire90-495_9-layer_1-width_3 +Xwire90@1 net@49 net@46 wire90-142_6-layer_1-width_3 +Xwire90@2 net@52 net@53 wire90-224_6-layer_1-width_3 +Xwire90@4 net@66 net@64 wire90-222_9-layer_1-width_3 +Xwire90@5 net@70 net@68 wire90-222_9-layer_1-width_3 +Xwire90@6 net@76 net@75 wire90-224_6-layer_1-width_3 +.ENDS moveAnd + +*** CELL: driversL:predDri60wMC{sch} +.SUBCKT driversL__predDri60wMC in mc pred +XNMOSx@0 pred in gnd NMOSx-X_60 +XNMOSx@1 pred mc gnd NMOSx-X_10 +Xinv@0 pred net@145 inv-X_10 +Xpms3@0 pred mc in net@174 pms3-X_3_333 +Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3 +.ENDS driversL__predDri60wMC + +*** CELL: driversL:predORdri20wMC{sch} +.SUBCKT predORdri20wMC inA inB mc pred +XNMOSx@0 pred inA gnd NMOSx-X_20 +XNMOSx@1 pred mc gnd NMOSx-X_4 +XNMOSx@2 pred inB gnd NMOSx-X_20 +XPMOSx@1 pred net@217 net@203 PMOSx-X_4 +XPMOSx@2 net@203 inB net@204 PMOSx-X_4 +XPMOSx@3 net@204 inA net@205 PMOSx-X_4 +XPMOSx@4 net@205 mc vdd PMOSx-X_4 +Xinv@0 pred net@145 inv-X_4 +Xwire90@0 net@217 net@145 wire90-243_6-layer_1-width_3 +.ENDS predORdri20wMC -*** CELL: redFour:pms2_sy{sch} -.SUBCKT pms2_sy-X_3 d g g2 -Xpms2@0 d g g2 pms2-X_1_5 -Xpms2@1 d g2 g pms2-X_1_5 -.ENDS pms2_sy-X_3 +*** CELL: redFive:nms1{sch} +.SUBCKT nms1-X_10 d g +XNMOS@1 d g gnd NMOSx-X_10 +.ENDS nms1-X_10 *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-218_6-R_34_667m a b @@ -3530,2575 +3843,2787 @@ Rres@3 net@8 net@11 2.526 Xwire@0 a b wire-C_0_011f-218_6-R_34_667m .ENDS wire90-218_6-layer_1-width_3 -*** CELL: dockPartsK:predWait{sch} -.SUBCKT predWait ign[2] ign[3] out pred[1] pred[2] pred[3] -XNMOSx@6 net@108 ign[3] out NMOSx-X_10 -XNMOSx@8 net@87 pred[2] net@108 NMOSx-X_20 -XNMOSx@9 net@87 ign[2] net@86 NMOSx-X_10 -XNMOSx@10 net@86 pred[3] out NMOSx-X_20 -XNMOSx@11 gnd pred[1] net@87 NMOSx-X_20 -XPMOSx@0 vdd pred[1] out PMOSx-X_10 -Xpms2_sy@2 out pred[2] ign[2] pms2_sy-X_3 -Xpms2_sy@3 out pred[3] ign[3] pms2_sy-X_3 -Xwire90@0 net@108 net@86 wire90-218_6-layer_1-width_3 -.ENDS predWait - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-795_4-R_34_667m a b -Ccap@0 gnd net@14 2.916f -Ccap@1 gnd net@8 2.916f -Ccap@2 gnd net@11 2.916f -Rres@0 net@14 a 4.596 -Rres@1 net@11 net@14 9.191 -Rres@2 b net@8 4.596 -Rres@3 net@8 net@11 9.191 -.ENDS wire-C_0_011f-795_4-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-795_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-795_4-R_34_667m -.ENDS wire90-795_4-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-459_9-R_34_667m a b -Ccap@0 gnd net@14 1.686f -Ccap@1 gnd net@8 1.686f -Ccap@2 gnd net@11 1.686f -Rres@0 net@14 a 2.657 -Rres@1 net@11 net@14 5.314 -Rres@2 b net@8 2.657 -Rres@3 net@8 net@11 5.314 -.ENDS wire-C_0_011f-459_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-459_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-459_9-R_34_667m -.ENDS wire90-459_9-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-361_8-R_34_667m a b -Ccap@0 gnd net@14 1.327f -Ccap@1 gnd net@8 1.327f -Ccap@2 gnd net@11 1.327f -Rres@0 net@14 a 2.09 -Rres@1 net@11 net@14 4.181 -Rres@2 b net@8 2.09 -Rres@3 net@8 net@11 4.181 -.ENDS wire-C_0_011f-361_8-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-361_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-361_8-R_34_667m -.ENDS wire90-361_8-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-307-R_34_667m a b -Ccap@0 gnd net@14 1.126f -Ccap@1 gnd net@8 1.126f -Ccap@2 gnd net@11 1.126f -Rres@0 net@14 a 1.774 -Rres@1 net@11 net@14 3.548 -Rres@2 b net@8 1.774 -Rres@3 net@8 net@11 3.548 -.ENDS wire-C_0_011f-307-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-307-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-307-R_34_667m -.ENDS wire90-307-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-258_6-R_34_667m a b -Ccap@0 gnd net@14 0.948f -Ccap@1 gnd net@8 0.948f -Ccap@2 gnd net@11 0.948f -Rres@0 net@14 a 1.494 -Rres@1 net@11 net@14 2.988 -Rres@2 b net@8 1.494 -Rres@3 net@8 net@11 2.988 -.ENDS wire-C_0_011f-258_6-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-258_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-258_6-R_34_667m -.ENDS wire90-258_6-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-386_2-R_34_667m a b -Ccap@0 gnd net@14 1.416f -Ccap@1 gnd net@8 1.416f -Ccap@2 gnd net@11 1.416f -Rres@0 net@14 a 2.231 -Rres@1 net@11 net@14 4.463 -Rres@2 b net@8 2.231 -Rres@3 net@8 net@11 4.463 -.ENDS wire-C_0_011f-386_2-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-386_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-386_2-R_34_667m -.ENDS wire90-386_2-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1409_3-R_34_667m a b -Ccap@0 gnd net@14 5.167f -Ccap@1 gnd net@8 5.167f -Ccap@2 gnd net@11 5.167f -Rres@0 net@14 a 8.143 -Rres@1 net@11 net@14 16.285 -Rres@2 b net@8 8.143 -Rres@3 net@8 net@11 16.285 -.ENDS wire-C_0_011f-1409_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1409_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1409_3-R_34_667m -.ENDS wire90-1409_3-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-316-R_34_667m a b -Ccap@0 gnd net@14 1.159f -Ccap@1 gnd net@8 1.159f -Ccap@2 gnd net@11 1.159f -Rres@0 net@14 a 1.826 -Rres@1 net@11 net@14 3.652 -Rres@2 b net@8 1.826 -Rres@3 net@8 net@11 3.652 -.ENDS wire-C_0_011f-316-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-316-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-316-R_34_667m -.ENDS wire90-316-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-324_9-R_34_667m a b -Ccap@0 gnd net@14 1.191f -Ccap@1 gnd net@8 1.191f -Ccap@2 gnd net@11 1.191f -Rres@0 net@14 a 1.877 -Rres@1 net@11 net@14 3.754 -Rres@2 b net@8 1.877 -Rres@3 net@8 net@11 3.754 -.ENDS wire-C_0_011f-324_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-324_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-324_9-R_34_667m -.ENDS wire90-324_9-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1083_5-R_34_667m a b -Ccap@0 gnd net@14 3.973f -Ccap@1 gnd net@8 3.973f -Ccap@2 gnd net@11 3.973f -Rres@0 net@14 a 6.26 -Rres@1 net@11 net@14 12.52 -Rres@2 b net@8 6.26 -Rres@3 net@8 net@11 12.52 -.ENDS wire-C_0_011f-1083_5-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1083_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1083_5-R_34_667m -.ENDS wire90-1083_5-layer_1-width_3 - -*** CELL: dockPartsK:moveC{sch} -.SUBCKT moveC do[M] fire[M] fire[T] ilc[cnt] ilc[dLO] ilc[i] ilc[zLO] -+ilc[zoo] m1[18] m1[19] m1[20] mc pred[D] pred[T] s[1] s[2] succ[D] succ[T] -+torp -Xarbiter2@0 net@1653 net@1652 torp net@860 arbiter2 -XctrAND4i@1 net@1475 net@1481 net@1498 m1[20] fire[T] ctrAND4in30 -Xinv@39 do[M] net@1494 inv-X_10 -Xinv@43 fire[T] net@1388 inv-X_10 -Xinv@47 net@1415 net@1589 inv-X_10 -Xinv@49 fire[AE] net@1593 inv-X_10 -Xinv@51 m1[18] ign[D] inv-X_10 -Xinv@52 m1[19] ign[T] inv-X_10 -Xinv@54 torp net@1705 inv-X_5 -Xinv@55 net@1704 s[2] inv-X_10 -Xinv@56 do[M] net@1709 inv-X_5 -Xinv@57 net@1708 s[1] inv-X_10 -XmoveE@1 net@1682 fire[AE] fire[M] ilc[cnt] ilc[dLO] ilc[i] ilc[zLO] ilc[zoo] -+moveE -Xnand2@3 m1[20] net@860 net@925 nand2-X_10 -Xnand2_sy@0 net@1612 net@1335 net@1574 nand2_sy-X_20 -Xnand2n@1 net@877 net@926 net@1334 nand2n-X_10 -Xnor2n@5 fire[A] okLO net@652 nor2n-X_20 -Xnor2n_sy@0 succ[D] succ[T] net@1619 nor2n_sy-X_10 -XpredDri2@1 net@1401 mc torp predDri20wMC -XpredORdr@0 net@1401 net@1698 mc do[M] predORdri20wMC -XpredWait@0 ign[D] ign[T] net@1530 do[M] pred[D] pred[T] predWait -Xwire90@18 net@860 net@652 wire90-795_4-layer_1-width_3 -Xwire90@19 net@1498 net@1494 wire90-459_9-layer_1-width_3 -Xwire90@21 net@1652 net@877 wire90-361_8-layer_1-width_3 -Xwire90@22 net@1653 net@1475 wire90-307-layer_1-width_3 -Xwire90@25 net@925 net@926 wire90-258_6-layer_1-width_3 -Xwire90@33 net@1682 net@1698 wire90-386_2-layer_1-width_3 -Xwire90@38 net@1401 fire[T] wire90-1409_3-layer_1-width_3 -Xwire90@42 net@1388 net@1415 wire90-316-layer_1-width_3 -Xwire90@43 net@1334 net@1335 wire90-324_9-layer_1-width_3 -Xwire90@49 okLO net@1530 wire90-795_4-layer_1-width_3 -Xwire90@53 net@1574 fire[AE] wire90-1083_5-layer_1-width_3 -Xwire90@55 net@1481 net@1589 wire90-316-layer_1-width_3 -Xwire90@56 net@1593 fire[A] wire90-795_4-layer_1-width_3 -Xwire90@57 net@1612 net@1619 wire90-324_9-layer_1-width_3 -Xwire90@58 net@1705 net@1704 wire90-459_9-layer_1-width_3 -Xwire90@59 net@1709 net@1708 wire90-459_9-layer_1-width_3 -.ENDS moveC +*** CELL: oneHotM:predWaitB{sch} +.SUBCKT predWaitB ign[1] ign[2] out pred[1] pred[2] +XNMOSx@6 net@108 ign[1] out NMOSx-X_10 +XNMOSx@11 net@90 pred[1] out NMOSx-X_10 +Xnms1@1 net@108 pred[2] nms1-X_10 +Xnms1@4 net@90 ign[2] nms1-X_10 +Xpms2@0 out ign[2] pred[2] pms2-X_5 +Xpms2@1 out ign[1] pred[1] pms2-X_5 +Xwire90@0 net@108 net@90 wire90-218_6-layer_1-width_3 +.ENDS predWaitB + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-153_6-R_34_667m a b +Ccap@0 gnd net@14 0.563f +Ccap@1 gnd net@8 0.563f +Ccap@2 gnd net@11 0.563f +Rres@0 net@14 a 0.887 +Rres@1 net@11 net@14 1.775 +Rres@2 b net@8 0.887 +Rres@3 net@8 net@11 1.775 +.ENDS wire-C_0_011f-153_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-153_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-153_6-R_34_667m +.ENDS wire90-153_6-layer_1-width_3 + +*** CELL: oneHotM:movePreds{sch} +.SUBCKT movePreds do[Mv] done[D] done[M] done[T] done[Tp] ign[D] ign[T] mc ++pred[D] pred[T] s[1] s[2] s[3] wait +Xinv@0 net@29 s[1] inv-X_10 +Xinv@1 net@33 s[2] inv-X_10 +Xinv@2 net@36 s[3] inv-X_10 +XinvI@0 do[Mv] net@28 inv-X_5 +XinvI@1 pred[T] net@32 inv-X_5 +XinvI@2 pred[D] net@35 inv-X_5 +XinvI@3 ign[T] net@69 inv-X_5 +XinvI@4 ign[D] net@74 inv-X_5 +XpredDri6@0 done[D] mc pred[D] driversL__predDri60wMC +XpredDri6@1 done[T] mc pred[T] driversL__predDri60wMC +XpredORdr@0 done[Tp] done[M] mc do[Mv] predORdri20wMC +XpredWait@0 net@71 net@76 wait pred[T] pred[D] predWaitB +Xwire90@0 net@29 net@28 wire90-142_6-layer_1-width_3 +Xwire90@1 net@33 net@32 wire90-142_6-layer_1-width_3 +Xwire90@2 net@36 net@35 wire90-142_6-layer_1-width_3 +Xwire90@3 net@69 net@71 wire90-153_6-layer_1-width_3 +Xwire90@4 net@76 net@74 wire90-153_6-layer_1-width_3 +.ENDS movePreds + +*** CELL: oneHotM:moveTorpPreds{sch} +.SUBCKT moveTorpPreds TpBAR do[Tp] done[M] fire[T] mc s[4] s[5] torp torpBAR ++win[T] +Xinv@0 TpBAR s[4] inv-X_10 +Xinv@1 torpBAR s[5] inv-X_10 +XinvI@1 do[Tp] TpBAR inv-X_10 +XinvI@2 torp torpBAR inv-X_10 +XinvI@3 win[T] fire[T] inv-X_30 +XpredDri2@0 fire[T] mc torp predDri20wMC +XpredORdr@0 fire[T] done[M] mc do[Tp] predORdri20wMC +.ENDS moveTorpPreds + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-617-R_34_667m a b +Ccap@0 gnd net@14 2.262f +Ccap@1 gnd net@8 2.262f +Ccap@2 gnd net@11 2.262f +Rres@0 net@14 a 3.565 +Rres@1 net@11 net@14 7.13 +Rres@2 b net@8 3.565 +Rres@3 net@8 net@11 7.13 +.ENDS wire-C_0_011f-617-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-617-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-617-R_34_667m +.ENDS wire90-617-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1348_3-R_34_667m a b +Ccap@0 gnd net@14 4.944f +Ccap@1 gnd net@8 4.944f +Ccap@2 gnd net@11 4.944f +Rres@0 net@14 a 7.79 +Rres@1 net@11 net@14 15.58 +Rres@2 b net@8 7.79 +Rres@3 net@8 net@11 15.58 +.ENDS wire-C_0_011f-1348_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1348_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1348_3-R_34_667m +.ENDS wire90-1348_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-865_4-R_34_667m a b +Ccap@0 gnd net@14 3.173f +Ccap@1 gnd net@8 3.173f +Ccap@2 gnd net@11 3.173f +Rres@0 net@14 a 5 +Rres@1 net@11 net@14 10 +Rres@2 b net@8 5 +Rres@3 net@8 net@11 10 +.ENDS wire-C_0_011f-865_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-865_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-865_4-R_34_667m +.ENDS wire90-865_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1509_4-R_34_667m a b +Ccap@0 gnd net@14 5.534f +Ccap@1 gnd net@8 5.534f +Ccap@2 gnd net@11 5.534f +Rres@0 net@14 a 8.721 +Rres@1 net@11 net@14 17.442 +Rres@2 b net@8 8.721 +Rres@3 net@8 net@11 17.442 +.ENDS wire-C_0_011f-1509_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1509_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1509_4-R_34_667m +.ENDS wire90-1509_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-479_8-R_34_667m a b +Ccap@0 gnd net@14 1.759f +Ccap@1 gnd net@8 1.759f +Ccap@2 gnd net@11 1.759f +Rres@0 net@14 a 2.772 +Rres@1 net@11 net@14 5.544 +Rres@2 b net@8 2.772 +Rres@3 net@8 net@11 5.544 +.ENDS wire-C_0_011f-479_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-479_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-479_8-R_34_667m +.ENDS wire90-479_8-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-930_7-R_34_667m a b +Ccap@0 gnd net@14 3.413f +Ccap@1 gnd net@8 3.413f +Ccap@2 gnd net@11 3.413f +Rres@0 net@14 a 5.377 +Rres@1 net@11 net@14 10.755 +Rres@2 b net@8 5.377 +Rres@3 net@8 net@11 10.755 +.ENDS wire-C_0_011f-930_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-930_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-930_7-R_34_667m +.ENDS wire90-930_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-682_4-R_34_667m a b +Ccap@0 gnd net@14 2.502f +Ccap@1 gnd net@8 2.502f +Ccap@2 gnd net@11 2.502f +Rres@0 net@14 a 3.943 +Rres@1 net@11 net@14 7.886 +Rres@2 b net@8 3.943 +Rres@3 net@8 net@11 7.886 +.ENDS wire-C_0_011f-682_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-682_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-682_4-R_34_667m +.ENDS wire90-682_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-897_3-R_34_667m a b +Ccap@0 gnd net@14 3.29f +Ccap@1 gnd net@8 3.29f +Ccap@2 gnd net@11 3.29f +Rres@0 net@14 a 5.184 +Rres@1 net@11 net@14 10.369 +Rres@2 b net@8 5.184 +Rres@3 net@8 net@11 10.369 +.ENDS wire-C_0_011f-897_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-897_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-897_3-R_34_667m +.ENDS wire90-897_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1010_4-R_34_667m a b +Ccap@0 gnd net@14 3.705f +Ccap@1 gnd net@8 3.705f +Ccap@2 gnd net@11 3.705f +Rres@0 net@14 a 5.838 +Rres@1 net@11 net@14 11.676 +Rres@2 b net@8 5.838 +Rres@3 net@8 net@11 11.676 +.ENDS wire-C_0_011f-1010_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1010_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1010_4-R_34_667m +.ENDS wire90-1010_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-918_3-R_34_667m a b +Ccap@0 gnd net@14 3.367f +Ccap@1 gnd net@8 3.367f +Ccap@2 gnd net@11 3.367f +Rres@0 net@14 a 5.306 +Rres@1 net@11 net@14 10.611 +Rres@2 b net@8 5.306 +Rres@3 net@8 net@11 10.611 +.ENDS wire-C_0_011f-918_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-918_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-918_3-R_34_667m +.ENDS wire90-918_3-layer_1-width_3 + +*** CELL: oneHotM:moveAll{sch} +.SUBCKT moveAll bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] fire[M] flag[D][set] ++ilc[ck] ilc[decLO] ilc[do] ilc[ho] ilc[mo] mc pred[D] pred[T] ready s[1] s[2] ++s[3] s[4] s[5] torp +XmeArbite@1 ready vdd net@535 net@508 net@391 net@739 net@500 net@738 ++meArbiter +XmoveAnd@1 net@727 bit[Di] bit[Ti] do[Mv] done[D] do[reD] done[T] fire[M] ++ilc[ck] ilc[decLO] ilc[do] ilc[ho] ilc[mo] win[M] moveAnd +XmovePred@0 do[Mv] done[D] done[M] done[T] done[Tp] bit[5] bit[4] mc pred[D] ++pred[T] s[1] s[2] s[3] wait movePreds +XmoveTorp@1 net@695 do[Tp] done[M] net@751 mc s[4] s[5] torp net@703 win[T] ++moveTorpPreds +Xpms1@0 flag[D][set] win[T] pms1-X_20 +Xwire90@1 net@508 win[T] wire90-617-layer_1-width_3 +Xwire90@5 net@727 net@391 wire90-1348_3-layer_1-width_3 +Xwire90@6 wait net@739 wire90-865_4-layer_1-width_3 +Xwire90@28 net@535 win[M] wire90-1509_4-layer_1-width_3 +Xwire90@29 wire90@29_a done[D] wire90-479_8-layer_1-width_3 +Xwire90@30 done[M] do[reD] wire90-930_7-layer_1-width_3 +Xwire90@31 wire90@31_a done[T] wire90-682_4-layer_1-width_3 +Xwire90@33 net@695 net@500 wire90-897_3-layer_1-width_3 +Xwire90@34 net@703 net@738 wire90-1010_4-layer_1-width_3 +Xwire90@36 net@751 done[Tp] wire90-918_3-layer_1-width_3 +.ENDS moveAll + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1764_4-R_34_667m a b +Ccap@0 gnd net@14 6.469f +Ccap@1 gnd net@8 6.469f +Ccap@2 gnd net@11 6.469f +Rres@0 net@14 a 10.194 +Rres@1 net@11 net@14 20.389 +Rres@2 b net@8 10.194 +Rres@3 net@8 net@11 20.389 +.ENDS wire-C_0_011f-1764_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1764_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1764_4-R_34_667m +.ENDS wire90-1764_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1373_4-R_34_667m a b +Ccap@0 gnd net@14 5.036f +Ccap@1 gnd net@8 5.036f +Ccap@2 gnd net@11 5.036f +Rres@0 net@14 a 7.935 +Rres@1 net@11 net@14 15.87 +Rres@2 b net@8 7.935 +Rres@3 net@8 net@11 15.87 +.ENDS wire-C_0_011f-1373_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1373_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1373_4-R_34_667m +.ENDS wire90-1373_4-layer_1-width_3 + +*** CELL: loopCountM:olcEven{sch} +.SUBCKT olcEven bit[2] bit[4] bit[6] count[T] do[2] do[4] do[6] inLO[2] ++inLO[4] inLO[6] load[T] +Xinv@2 count[T] net@210 inv-X_30 +Xinv@3 load[T] net@211 inv-X_30 +XringB@3 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB +XringB@4 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB +XringB@5 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB +Xwire90@3 net@210 count[F] wire90-1764_4-layer_1-width_3 +Xwire90@4 net@211 load[F] wire90-1373_4-layer_1-width_3 +.ENDS olcEven + +*** CELL: loopCountM:olcOdd{sch} +.SUBCKT olcOdd bit[1] bit[3] bit[5] count[T] do[3] do[5] inLO[1] inLO[3] ++inLO[5] load[T] +Xinv@2 load[T] net@307 inv-X_30 +Xinv@3 count[T] net@310 inv-X_30 +XringB@3 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB +XringB@4 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB +XringB@5 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB +Xwire90@2 net@307 load[F] wire90-1373_4-layer_1-width_3 +Xwire90@3 net@310 count[F] wire90-1764_4-layer_1-width_3 +.ENDS olcOdd *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-185-R_34_667m a b -Ccap@0 gnd net@14 0.678f -Ccap@1 gnd net@8 0.678f -Ccap@2 gnd net@11 0.678f -Rres@0 net@14 a 1.069 -Rres@1 net@11 net@14 2.138 -Rres@2 b net@8 1.069 -Rres@3 net@8 net@11 2.138 -.ENDS wire-C_0_011f-185-R_34_667m +.SUBCKT wire-C_0_011f-380_7-R_34_667m a b +Ccap@0 gnd net@14 1.396f +Ccap@1 gnd net@8 1.396f +Ccap@2 gnd net@11 1.396f +Rres@0 net@14 a 2.2 +Rres@1 net@11 net@14 4.399 +Rres@2 b net@8 2.2 +Rres@3 net@8 net@11 4.399 +.ENDS wire-C_0_011f-380_7-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-185-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-185-R_34_667m -.ENDS wire90-185-layer_1-width_3 +.SUBCKT wire90-380_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-380_7-R_34_667m +.ENDS wire90-380_7-layer_1-width_3 -*** CELL: latchesK:mlat1in10{sch} -.SUBCKT mlat1in10 cl[F] cl[T] in[1] out[1] -Xinv@0 net@26 out[1] inv-X_10 -Xnms2@0 net@4 out[1] cl[F] nms2-X_2 -Xnms2@1 net@4 in[1] cl[T] nms2-X_2 -Xpms2@0 net@4 out[1] cl[T] pms2-X_1 -Xpms2@1 net@4 in[1] cl[F] pms2-X_2 -Xwire90@0 net@4 net@26 wire90-185-layer_1-width_3 -.ENDS mlat1in10 - -*** CELL: redFour:nms2{sch} -.SUBCKT nms2-X_3 d g g2 -XNMOS@0 d g2 net@0 NMOSx-X_6 -XNMOS@1 net@0 g gnd NMOSx-X_6 -.ENDS nms2-X_3 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-544_8-R_34_667m a b +Ccap@0 gnd net@14 1.998f +Ccap@1 gnd net@8 1.998f +Ccap@2 gnd net@11 1.998f +Rres@0 net@14 a 3.148 +Rres@1 net@11 net@14 6.295 +Rres@2 b net@8 3.148 +Rres@3 net@8 net@11 6.295 +.ENDS wire-C_0_011f-544_8-R_34_667m -*** CELL: redFour:nms3{sch} -.SUBCKT nms3-X_2 d g g2 g3 -XNMOS@0 d g3 net@6 NMOSx-X_6 -XNMOS@1 net@7 g gnd NMOSx-X_6 -XNMOS@2 net@6 g2 net@7 NMOSx-X_6 -.ENDS nms3-X_2 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-544_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-544_8-R_34_667m +.ENDS wire90-544_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-339_3-R_34_667m a b -Ccap@0 gnd net@14 1.244f -Ccap@1 gnd net@8 1.244f -Ccap@2 gnd net@11 1.244f -Rres@0 net@14 a 1.96 -Rres@1 net@11 net@14 3.921 -Rres@2 b net@8 1.96 -Rres@3 net@8 net@11 3.921 -.ENDS wire-C_0_011f-339_3-R_34_667m +.SUBCKT wire-C_0_011f-478_3-R_34_667m a b +Ccap@0 gnd net@14 1.754f +Ccap@1 gnd net@8 1.754f +Ccap@2 gnd net@11 1.754f +Rres@0 net@14 a 2.764 +Rres@1 net@11 net@14 5.527 +Rres@2 b net@8 2.764 +Rres@3 net@8 net@11 5.527 +.ENDS wire-C_0_011f-478_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-339_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-339_3-R_34_667m -.ENDS wire90-339_3-layer_1-width_3 - -*** CELL: latchesK:mlat2in10{sch} -.SUBCKT mlat2in10 clA[F] clA[T] clB[F] clB[T] inA inB out[1] -Xinv@0 net@26 out[1] inv-X_10 -Xnms2@0 net@4 inB clB[T] nms2-X_3 -Xnms2@1 net@4 inA clA[T] nms2-X_3 -Xnms3@0 net@4 clA[F] out[1] clB[F] nms3-X_2 -Xpms2@0 net@4 inB clB[F] pms2-X_2_5 -Xpms2@1 net@4 inA clA[F] pms2-X_2_5 -Xpms3@0 net@4 clA[T] out[1] clB[T] pms3-X_1 -Xwire90@0 net@4 net@26 wire90-339_3-layer_1-width_3 -.ENDS mlat2in10 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-271_1-R_34_667m a b -Ccap@0 gnd net@14 0.994f -Ccap@1 gnd net@8 0.994f -Ccap@2 gnd net@11 0.994f -Rres@0 net@14 a 1.566 -Rres@1 net@11 net@14 3.133 -Rres@2 b net@8 1.566 -Rres@3 net@8 net@11 3.133 -.ENDS wire-C_0_011f-271_1-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-271_1-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-271_1-R_34_667m -.ENDS wire90-271_1-layer_1-width_3 - -*** CELL: scanK:scanCellKh{sch} -.SUBCKT scanCellKh clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin sout -Xmlat1in1@1 cl[F] cl[T] sin net@58 mlat1in10 -Xmlat2in1@2 clS[F] clS[T] rd[F] rd[T] net@69 din[1] sout mlat2in10 -Xwire90@0 net@58 net@69 wire90-271_1-layer_1-width_3 -.ENDS scanCellKh - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-297_9-R_34_667m a b -Ccap@0 gnd net@14 1.092f -Ccap@1 gnd net@8 1.092f -Ccap@2 gnd net@11 1.092f -Rres@0 net@14 a 1.721 -Rres@1 net@11 net@14 3.442 -Rres@2 b net@8 1.721 -Rres@3 net@8 net@11 3.442 -.ENDS wire-C_0_011f-297_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-297_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-297_9-R_34_667m -.ENDS wire90-297_9-layer_1-width_3 - -*** CELL: scanK:scanKhx5{sch} -.SUBCKT scanKhx5 clS[F] clS[T] cl[F] cl[T] din[1] din[2] din[3] din[4] din[5] -+mc rd[F] rd[T] sin sout -XscanCell@4 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin net@18 -+scanCellKh -XscanCell@5 clS[F] clS[T] cl[F] cl[T] din[2] rd[F] rd[T] net@31 net@20 -+scanCellKh -XscanCell@6 clS[F] clS[T] cl[F] cl[T] din[3] rd[F] rd[T] net@32 net@24 -+scanCellKh -XscanCell@7 clS[F] clS[T] cl[F] cl[T] din[4] rd[F] rd[T] net@33 net@51 -+scanCellKh -XscanCell@8 clS[F] clS[T] cl[F] cl[T] din[5] rd[F] rd[T] net@50 sout -+scanCellKh -Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3 -Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3 -Xwire90@2 net@24 net@33 wire90-297_9-layer_1-width_3 -Xwire90@3 net@51 net@50 wire90-297_9-layer_1-width_3 -.ENDS scanKhx5 - -*** CELL: dockPartsK:moveLit{sch} -.SUBCKT moveLit clS[F] clS[T] cl[F] cl[T] do[L] do[M] fire[L] fire[M] fire[T] -+ilc[cnt] ilc[dLO] ilc[i] ilc[zLO] ilc[zoo] m1[15] m1[16] m1[18] m1[19] m1[20] -+mc pred[D] pred[T] rd[F] rd[T] sin sout succ[D] succ[T] torp -XdStates@0 fire[M] mc m1[15] m1[16] m1[18] m1[19] pred[D] pred[T] s[1] s[2] -+succ[D] succ[T] moveD -XlitStage@0 do[L] fire[L] mc s[3] succ[D] succ[T] litStage -XmoveC@0 do[M] fire[M] fire[T] ilc[cnt] ilc[dLO] ilc[i] ilc[zLO] ilc[zoo] -+m1[18] m1[19] m1[20] mc pred[D] pred[T] s[4] s[5] succ[D] succ[T] torp moveC -XscanKhx5@0 clS[F] clS[T] cl[F] cl[T] s[1] s[2] s[3] s[4] s[5] mc rd[F] rd[T] -+sin sout scanKhx5 -.ENDS moveLit - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-190_2-R_34_667m a b -Ccap@0 gnd net@14 0.697f -Ccap@1 gnd net@8 0.697f -Ccap@2 gnd net@11 0.697f -Rres@0 net@14 a 1.099 -Rres@1 net@11 net@14 2.198 -Rres@2 b net@8 1.099 -Rres@3 net@8 net@11 2.198 -.ENDS wire-C_0_011f-190_2-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-190_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-190_2-R_34_667m -.ENDS wire90-190_2-layer_1-width_3 - -*** CELL: latchesK:mlat1in10i{sch} -.SUBCKT mlat1in10i cl[F] cl[T] in[1] out[1] -XinvLT@0 out[1] net@33 invLT-X_2 -Xnms2@0 out[1] cl[F] net@33 nms2-X_2 -Xnms2@1 out[1] in[1] cl[T] nms2-X_10 -Xpms2@0 out[1] cl[T] net@138 pms2-X_2 -Xpms2@1 out[1] in[1] cl[F] pms2-X_10 -Xwire90@2 net@138 net@33 wire90-190_2-layer_1-width_3 -.ENDS mlat1in10i +.SUBCKT wire90-478_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-478_3-R_34_667m +.ENDS wire90-478_3-layer_1-width_3 -*** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_6_667 d g s -MPMOSf@0 d g s vdd pch W='40.002*(1+ABP/sqrt(40.002*2))' L='2' -+DELVTO='AVT0P/sqrt(40.002*2)' -.ENDS PMOSx-X_6_667 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-554_3-R_34_667m a b +Ccap@0 gnd net@14 2.032f +Ccap@1 gnd net@8 2.032f +Ccap@2 gnd net@11 2.032f +Rres@0 net@14 a 3.203 +Rres@1 net@11 net@14 6.405 +Rres@2 b net@8 3.203 +Rres@3 net@8 net@11 6.405 +.ENDS wire-C_0_011f-554_3-R_34_667m -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_20_001 d g s -MNMOSf@0 d g s gnd nch W='60.003*(1+ABN/sqrt(60.003*2))' L='2' -+DELVTO='AVT0N/sqrt(60.003*2)' -.ENDS NMOSx-X_20_001 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-554_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-554_3-R_34_667m +.ENDS wire90-554_3-layer_1-width_3 -*** CELL: redFour:nms3{sch} -.SUBCKT nms3-X_6_667 d g g2 g3 -XNMOS@0 d g3 net@6 NMOSx-X_20_001 -XNMOS@1 net@7 g gnd NMOSx-X_20_001 -XNMOS@2 net@6 g2 net@7 NMOSx-X_20_001 -.ENDS nms3-X_6_667 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-463_3-R_34_667m a b +Ccap@0 gnd net@14 1.699f +Ccap@1 gnd net@8 1.699f +Ccap@2 gnd net@11 1.699f +Rres@0 net@14 a 2.677 +Rres@1 net@11 net@14 5.354 +Rres@2 b net@8 2.677 +Rres@3 net@8 net@11 5.354 +.ENDS wire-C_0_011f-463_3-R_34_667m -*** CELL: redFour:nand3{sch} -.SUBCKT nand3-X_6_667 ina inb inc out -XPMOS@0 out inc vdd PMOSx-X_6_667 -XPMOS@1 out inb vdd PMOSx-X_6_667 -XPMOS@2 out ina vdd PMOSx-X_6_667 -Xnms3@0 out ina inb inc nms3-X_6_667 -.ENDS nand3-X_6_667 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-463_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-463_3-R_34_667m +.ENDS wire90-463_3-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-549_2-R_34_667m a b -Ccap@0 gnd net@14 2.014f -Ccap@1 gnd net@8 2.014f -Ccap@2 gnd net@11 2.014f -Rres@0 net@14 a 3.173 -Rres@1 net@11 net@14 6.346 -Rres@2 b net@8 3.173 -Rres@3 net@8 net@11 6.346 -.ENDS wire-C_0_011f-549_2-R_34_667m +.SUBCKT wire-C_0_011f-1413_6-R_34_667m a b +Ccap@0 gnd net@14 5.183f +Ccap@1 gnd net@8 5.183f +Ccap@2 gnd net@11 5.183f +Rres@0 net@14 a 8.167 +Rres@1 net@11 net@14 16.335 +Rres@2 b net@8 8.167 +Rres@3 net@8 net@11 16.335 +.ENDS wire-C_0_011f-1413_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-549_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-549_2-R_34_667m -.ENDS wire90-549_2-layer_1-width_3 +.SUBCKT wire90-1413_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1413_6-R_34_667m +.ENDS wire90-1413_6-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-703_8-R_34_667m a b -Ccap@0 gnd net@14 2.581f -Ccap@1 gnd net@8 2.581f -Ccap@2 gnd net@11 2.581f -Rres@0 net@14 a 4.066 -Rres@1 net@11 net@14 8.133 -Rres@2 b net@8 4.066 -Rres@3 net@8 net@11 8.133 -.ENDS wire-C_0_011f-703_8-R_34_667m +.SUBCKT wire-C_0_011f-1559_3-R_34_667m a b +Ccap@0 gnd net@14 5.717f +Ccap@1 gnd net@8 5.717f +Ccap@2 gnd net@11 5.717f +Rres@0 net@14 a 9.009 +Rres@1 net@11 net@14 18.019 +Rres@2 b net@8 9.009 +Rres@3 net@8 net@11 18.019 +.ENDS wire-C_0_011f-1559_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-703_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-703_8-R_34_667m -.ENDS wire90-703_8-layer_1-width_3 +.SUBCKT wire90-1559_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1559_3-R_34_667m +.ENDS wire90-1559_3-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-543_6-R_34_667m a b -Ccap@0 gnd net@14 1.993f -Ccap@1 gnd net@8 1.993f -Ccap@2 gnd net@11 1.993f -Rres@0 net@14 a 3.141 -Rres@1 net@11 net@14 6.282 -Rres@2 b net@8 3.141 -Rres@3 net@8 net@11 6.282 -.ENDS wire-C_0_011f-543_6-R_34_667m +.SUBCKT wire-C_0_011f-1365_7-R_34_667m a b +Ccap@0 gnd net@14 5.008f +Ccap@1 gnd net@8 5.008f +Ccap@2 gnd net@11 5.008f +Rres@0 net@14 a 7.891 +Rres@1 net@11 net@14 15.781 +Rres@2 b net@8 7.891 +Rres@3 net@8 net@11 15.781 +.ENDS wire-C_0_011f-1365_7-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-543_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-543_6-R_34_667m -.ENDS wire90-543_6-layer_1-width_3 +.SUBCKT wire90-1365_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1365_7-R_34_667m +.ENDS wire90-1365_7-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-645_3-R_34_667m a b -Ccap@0 gnd net@14 2.366f -Ccap@1 gnd net@8 2.366f -Ccap@2 gnd net@11 2.366f -Rres@0 net@14 a 3.728 -Rres@1 net@11 net@14 7.457 -Rres@2 b net@8 3.728 -Rres@3 net@8 net@11 7.457 -.ENDS wire-C_0_011f-645_3-R_34_667m +.SUBCKT wire-C_0_011f-1320_2-R_34_667m a b +Ccap@0 gnd net@14 4.841f +Ccap@1 gnd net@8 4.841f +Ccap@2 gnd net@11 4.841f +Rres@0 net@14 a 7.628 +Rres@1 net@11 net@14 15.256 +Rres@2 b net@8 7.628 +Rres@3 net@8 net@11 15.256 +.ENDS wire-C_0_011f-1320_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-645_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-645_3-R_34_667m -.ENDS wire90-645_3-layer_1-width_3 +.SUBCKT wire90-1320_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1320_2-R_34_667m +.ENDS wire90-1320_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-378_8-R_34_667m a b -Ccap@0 gnd net@14 1.389f -Ccap@1 gnd net@8 1.389f -Ccap@2 gnd net@11 1.389f -Rres@0 net@14 a 2.189 -Rres@1 net@11 net@14 4.377 -Rres@2 b net@8 2.189 -Rres@3 net@8 net@11 4.377 -.ENDS wire-C_0_011f-378_8-R_34_667m +.SUBCKT wire-C_0_011f-1126_6-R_34_667m a b +Ccap@0 gnd net@14 4.131f +Ccap@1 gnd net@8 4.131f +Ccap@2 gnd net@11 4.131f +Rres@0 net@14 a 6.509 +Rres@1 net@11 net@14 13.018 +Rres@2 b net@8 6.509 +Rres@3 net@8 net@11 13.018 +.ENDS wire-C_0_011f-1126_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-378_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-378_8-R_34_667m -.ENDS wire90-378_8-layer_1-width_3 - -*** CELL: loopCountL:countLogicZoo{sch} -.SUBCKT countLogicZoo bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] count do[2] -+do[3] do[4] do[5] do[6] force0 ilc[zoo] -Xinv@0 net@257 do[2] inv-X_10 -Xinv@1 bit[2] net@128 inv-X_10 -Xinv@2 bit[1] net@257 inv-X_10 -Xinv@3 count net@347 inv-X_10 -Xmlat1in1@1 count count[F] ilc[zoo] net@350 mlat1in10i -Xnand2@0 bit[3] bit[1] net@145 nand2-X_10 -Xnand2@1 bit[4] bit[2] net@195 nand2-X_10 -Xnand2@2 bit[3] bit[5] net@315 nand2-X_10 -Xnand3@0 bit[5] bit[3] bit[1] net@264 nand3-X_6_667 -Xnand3@1 bit[6] bit[4] bit[2] net@198 nand3-X_6_667 -Xnor2n@1 net@128 net@257 do[3] nor2n-X_10 -Xnor2n@2 net@145 net@146 do[4] nor2n-X_10 -Xnor2n@3 net@195 net@58 do[5] nor2n-X_10 -Xnor2n@4 net@221 net@56 do[6] nor2n-X_10 -Xnor2n@6 net@289 net@267 ilc[zoo] nor2n-X_10 -Xnor2n@7 net@350 count[F] force0 nor2n-X_10 -Xwire90@0 net@264 net@221 wire90-549_2-layer_1-width_3 -Xwire90@1 net@58 net@145 wire90-703_8-layer_1-width_3 -Xwire90@3 net@56 net@195 wire90-703_8-layer_1-width_3 -Xwire90@5 net@198 net@289 wire90-543_6-layer_1-width_3 -Xwire90@6 net@146 net@128 wire90-645_3-layer_1-width_3 -Xwire90@8 net@267 net@315 wire90-378_8-layer_1-width_3 -Xwire90@9 net@347 count[F] wire90-543_6-layer_1-width_3 -.ENDS countLogicZoo - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-216_3-R_34_667m a b -Ccap@0 gnd net@14 0.793f -Ccap@1 gnd net@8 0.793f -Ccap@2 gnd net@11 0.793f -Rres@0 net@14 a 1.25 -Rres@1 net@11 net@14 2.499 -Rres@2 b net@8 1.25 -Rres@3 net@8 net@11 2.499 -.ENDS wire-C_0_011f-216_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-216_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-216_3-R_34_667m -.ENDS wire90-216_3-layer_1-width_3 - -*** CELL: latchesK:latchZ10{sch} -.SUBCKT latchZ10 c[1] c[2] cl[F] cl[T] in[1] mc out[TT] out[T] -MNMOSf@1 out[T] net@186 gnd gnd nch W='12*(1+ABN/sqrt(12*3))' L='3' -+DELVTO='AVT0N/sqrt(12*3)' -XNMOSx@2 out[T] mc gnd NMOSx-X_10 -XNMOSx@3 out[T] c[1] gnd NMOSx-X_10 -XNMOSx@4 out[T] c[2] gnd NMOSx-X_20 -XPMOSx@2 out[T] net@186 vdd PMOSx-X_2 -Xinv@0 net@240 out[TT] inv-X_10 -XinvLT@0 out[T] net@186 invLT-X_2 -Xnms2@0 out[T] in[1] cl[T] nms2-X_10 -Xpms2@0 out[T] in[1] cl[F] pms2-X_10 -Xwire90@0 net@240 net@186 wire90-216_3-layer_1-width_3 -.ENDS latchZ10 +.SUBCKT wire90-1126_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1126_6-R_34_667m +.ENDS wire90-1126_6-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-200_9-R_34_667m a b -Ccap@0 gnd net@14 0.737f -Ccap@1 gnd net@8 0.737f -Ccap@2 gnd net@11 0.737f -Rres@0 net@14 a 1.161 -Rres@1 net@11 net@14 2.322 -Rres@2 b net@8 1.161 -Rres@3 net@8 net@11 2.322 -.ENDS wire-C_0_011f-200_9-R_34_667m +.SUBCKT wire-C_0_011f-1033_6-R_34_667m a b +Ccap@0 gnd net@14 3.79f +Ccap@1 gnd net@8 3.79f +Ccap@2 gnd net@11 3.79f +Rres@0 net@14 a 5.972 +Rres@1 net@11 net@14 11.944 +Rres@2 b net@8 5.972 +Rres@3 net@8 net@11 11.944 +.ENDS wire-C_0_011f-1033_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-200_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-200_9-R_34_667m -.ENDS wire90-200_9-layer_1-width_3 +.SUBCKT wire90-1033_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1033_6-R_34_667m +.ENDS wire90-1033_6-layer_1-width_3 -*** CELL: latchesK:mlat2in10i{sch} -.SUBCKT mlat2in10i clA[F] clA[T] clB[F] clB[T] inA inB out[1] -Xinv@0 out[1] net@33 inv-X_4 -Xnms2@0 out[1] inB clB[T] nms2-X_10 -Xnms2@1 out[1] inA clA[T] nms2-X_10 -Xnms3@0 out[1] clB[F] clA[F] net@33 nms3-X_2 -Xpms2@0 out[1] inB clB[F] pms2-X_10 -Xpms2@1 out[1] inA clA[F] pms2-X_10 -Xpms3@0 out[1] clA[T] clB[T] net@81 pms3-X_1 -Xwire90@1 net@81 net@33 wire90-200_9-layer_1-width_3 -.ENDS mlat2in10i +*** CELL: loopCountM:olc{sch} +.SUBCKT olc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2] ++inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo] +XcountLog@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4] ++do[5] do[6] olc[zero] olc[zoo] calculate +XolcEven@1 bitt[2] bitt[4] bitt[6] olc[dec] do[2] do[4] do[6] inLO[2] inLO[4] ++inLO[6] olc[load] olcEven +XolcOdd@2 bitt[1] bitt[3] bitt[5] olc[dec] do[3] do[5] inLO[1] inLO[3] ++inLO[5] olc[load] olcOdd +Xwire90@1 wire90@1_a do[2] wire90-380_7-layer_1-width_3 +Xwire90@2 wire90@2_a do[3] wire90-544_8-layer_1-width_3 +Xwire90@3 wire90@3_a do[4] wire90-478_3-layer_1-width_3 +Xwire90@4 wire90@4_a do[5] wire90-554_3-layer_1-width_3 +Xwire90@5 wire90@5_a do[6] wire90-463_3-layer_1-width_3 +Xwire90@7 wire90@7_a bitt[1] wire90-1413_6-layer_1-width_3 +Xwire90@8 wire90@8_a bitt[2] wire90-1559_3-layer_1-width_3 +Xwire90@9 wire90@9_a bitt[3] wire90-1365_7-layer_1-width_3 +Xwire90@10 wire90@10_a bitt[4] wire90-1320_2-layer_1-width_3 +Xwire90@11 wire90@11_a bitt[5] wire90-1126_6-layer_1-width_3 +Xwire90@12 wire90@12_a bitt[6] wire90-1033_6-layer_1-width_3 +.ENDS olc + +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_100 d g s +MNMOSf@0 d g s gnd nch W='300*(1+ABN/sqrt(300*2))' L='2' ++DELVTO='AVT0N/sqrt(300*2)' +.ENDS NMOSx-X_100 + +*** CELL: orangeTSMC090nm:PMOSx{sch} +.SUBCKT PMOSx-X_100 d g s +MPMOSf@0 d g s vdd pch W='600*(1+ABP/sqrt(600*2))' L='2' ++DELVTO='AVT0P/sqrt(600*2)' +.ENDS PMOSx-X_100 + +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_100 in out +XNMOS@0 out in gnd NMOSx-X_100 +XPMOS@0 out in vdd PMOSx-X_100 +.ENDS inv-X_100 + +*** CELL: centersJ:ctrAND1in100{sch} +.SUBCKT ctrAND1in100 in out +Xinv@11 net@125 net@120 inv-X_30 +XinvI@3 in net@101 inv-X_10 +XinvI@4 net@82 out inv-X_100 +Xwire90@1 net@101 net@125 wire90-414-layer_1-width_3 +Xwire90@2 net@120 net@82 wire90-927-layer_1-width_3 +.ENDS ctrAND1in100 + +*** CELL: orangeTSMC090nm:PMOSx{sch} +.SUBCKT PMOSx-X_15 d g s +MPMOSf@0 d g s vdd pch W='90*(1+ABP/sqrt(90*2))' L='2' ++DELVTO='AVT0P/sqrt(90*2)' +.ENDS PMOSx-X_15 + +*** CELL: redFive:nand2LT_sy{sch} +.SUBCKT nand2LT_sy-X_30 ina inb out +XPMOS@0 out ina vdd PMOSx-X_15 +XPMOS@1 out inb vdd PMOSx-X_15 +Xnms2_sy@0 out ina inb nms2_sy-X_30 +.ENDS nand2LT_sy-X_30 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-173_2-R_34_667m a b -Ccap@0 gnd net@14 0.635f -Ccap@1 gnd net@8 0.635f -Ccap@2 gnd net@11 0.635f -Rres@0 net@14 a 1.001 -Rres@1 net@11 net@14 2.001 -Rres@2 b net@8 1.001 -Rres@3 net@8 net@11 2.001 -.ENDS wire-C_0_011f-173_2-R_34_667m +.SUBCKT wire-C_0_011f-399_2-R_34_667m a b +Ccap@0 gnd net@14 1.464f +Ccap@1 gnd net@8 1.464f +Ccap@2 gnd net@11 1.464f +Rres@0 net@14 a 2.306 +Rres@1 net@11 net@14 4.613 +Rres@2 b net@8 2.306 +Rres@3 net@8 net@11 4.613 +.ENDS wire-C_0_011f-399_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-173_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-173_2-R_34_667m -.ENDS wire90-173_2-layer_1-width_3 +.SUBCKT wire90-399_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-399_2-R_34_667m +.ENDS wire90-399_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-381_1-R_34_667m a b -Ccap@0 gnd net@14 1.397f -Ccap@1 gnd net@8 1.397f -Ccap@2 gnd net@11 1.397f -Rres@0 net@14 a 2.202 -Rres@1 net@11 net@14 4.404 -Rres@2 b net@8 2.202 -Rres@3 net@8 net@11 4.404 -.ENDS wire-C_0_011f-381_1-R_34_667m +.SUBCKT wire-C_0_011f-1013_8-R_34_667m a b +Ccap@0 gnd net@14 3.717f +Ccap@1 gnd net@8 3.717f +Ccap@2 gnd net@11 3.717f +Rres@0 net@14 a 5.858 +Rres@1 net@11 net@14 11.715 +Rres@2 b net@8 5.858 +Rres@3 net@8 net@11 11.715 +.ENDS wire-C_0_011f-1013_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-381_1-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-381_1-R_34_667m -.ENDS wire90-381_1-layer_1-width_3 +.SUBCKT wire90-1013_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1013_8-R_34_667m +.ENDS wire90-1013_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-981_4-R_34_667m a b -Ccap@0 gnd net@14 3.598f -Ccap@1 gnd net@8 3.598f -Ccap@2 gnd net@11 3.598f -Rres@0 net@14 a 5.67 -Rres@1 net@11 net@14 11.341 -Rres@2 b net@8 5.67 -Rres@3 net@8 net@11 11.341 -.ENDS wire-C_0_011f-981_4-R_34_667m +.SUBCKT wire-C_0_011f-468_3-R_34_667m a b +Ccap@0 gnd net@14 1.717f +Ccap@1 gnd net@8 1.717f +Ccap@2 gnd net@11 1.717f +Rres@0 net@14 a 2.706 +Rres@1 net@11 net@14 5.411 +Rres@2 b net@8 2.706 +Rres@3 net@8 net@11 5.411 +.ENDS wire-C_0_011f-468_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-981_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-981_4-R_34_667m -.ENDS wire90-981_4-layer_1-width_3 +.SUBCKT wire90-468_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-468_3-R_34_667m +.ENDS wire90-468_3-layer_1-width_3 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-523_4-R_34_667m a b -Ccap@0 gnd net@14 1.919f -Ccap@1 gnd net@8 1.919f -Ccap@2 gnd net@11 1.919f -Rres@0 net@14 a 3.024 -Rres@1 net@11 net@14 6.048 -Rres@2 b net@8 3.024 -Rres@3 net@8 net@11 6.048 -.ENDS wire-C_0_011f-523_4-R_34_667m +*** CELL: centersJ:ctrAND2in100LT{sch} +.SUBCKT ctrAND2in100LT inA inB out +Xinv@8 inB net@135 inv-X_10 +Xinv@9 inA net@139 inv-X_10 +Xinv@10 net@146 out inv-X_100 +Xnand2LT_@0 net@140 net@136 net@144 nand2LT_sy-X_30 +Xwire90@4 net@135 net@136 wire90-399_2-layer_1-width_3 +Xwire90@5 net@144 net@146 wire90-1013_8-layer_1-width_3 +Xwire90@6 net@139 net@140 wire90-468_3-layer_1-width_3 +.ENDS ctrAND2in100LT -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-523_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-523_4-R_34_667m -.ENDS wire90-523_4-layer_1-width_3 +*** CELL: centersJ:ctrAND2in100{sch} +.SUBCKT ctrAND2in100 inA inB out +Xinv@9 net@163 net@161 inv-X_30 +XinvI@1 net@162 out inv-X_100 +Xnor2n_sy@0 inA inB net@158 nor2n_sy-X_10 +Xwire90@6 net@158 net@163 wire90-414-layer_1-width_3 +Xwire90@7 net@161 net@162 wire90-927-layer_1-width_3 +.ENDS ctrAND2in100 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-535_1-R_34_667m a b -Ccap@0 gnd net@14 1.962f -Ccap@1 gnd net@8 1.962f -Ccap@2 gnd net@11 1.962f -Rres@0 net@14 a 3.092 -Rres@1 net@11 net@14 6.183 -Rres@2 b net@8 3.092 -Rres@3 net@8 net@11 6.183 -.ENDS wire-C_0_011f-535_1-R_34_667m +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_3_999 d g s +MNMOSf@0 d g s gnd nch W='11.997*(1+ABN/sqrt(11.997*2))' L='2' ++DELVTO='AVT0N/sqrt(11.997*2)' +.ENDS NMOSx-X_3_999 + +*** CELL: redFive:nms3{sch} +.SUBCKT nms3-X_1_333 d g g2 g3 +XNMOS@0 d g3 net@6 NMOSx-X_3_999 +XNMOS@1 net@7 g gnd NMOSx-X_3_999 +XNMOS@2 net@6 g2 net@7 NMOSx-X_3_999 +.ENDS nms3-X_1_333 + +*** CELL: driversL:sucDri20or{sch} +.SUBCKT sucDri20or inA inB succ +Xinv@1 succ net@94 inv-X_4 +Xnms3b@0 succ net@142 inB inA nms3-X_1_333 +Xpms1@0 succ inA pms1-X_20 +Xpms1@1 succ inB pms1-X_20 +Xwire90@0 net@142 net@94 wire90-124_7-layer_1-width_3 +.ENDS sucDri20or + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-629_6-R_34_667m a b +Ccap@0 gnd net@14 2.309f +Ccap@1 gnd net@8 2.309f +Ccap@2 gnd net@11 2.309f +Rres@0 net@14 a 3.638 +Rres@1 net@11 net@14 7.275 +Rres@2 b net@8 3.638 +Rres@3 net@8 net@11 7.275 +.ENDS wire-C_0_011f-629_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-535_1-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-535_1-R_34_667m -.ENDS wire90-535_1-layer_1-width_3 +.SUBCKT wire90-629_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-629_6-R_34_667m +.ENDS wire90-629_6-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-555_1-R_34_667m a b -Ccap@0 gnd net@14 2.035f -Ccap@1 gnd net@8 2.035f -Ccap@2 gnd net@11 2.035f -Rres@0 net@14 a 3.207 -Rres@1 net@11 net@14 6.414 -Rres@2 b net@8 3.207 -Rres@3 net@8 net@11 6.414 -.ENDS wire-C_0_011f-555_1-R_34_667m +.SUBCKT wire-C_0_011f-867_8-R_34_667m a b +Ccap@0 gnd net@14 3.182f +Ccap@1 gnd net@8 3.182f +Ccap@2 gnd net@11 3.182f +Rres@0 net@14 a 5.014 +Rres@1 net@11 net@14 10.028 +Rres@2 b net@8 5.014 +Rres@3 net@8 net@11 10.028 +.ENDS wire-C_0_011f-867_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-867_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-867_8-R_34_667m +.ENDS wire90-867_8-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-406_2-R_34_667m a b +Ccap@0 gnd net@14 1.489f +Ccap@1 gnd net@8 1.489f +Ccap@2 gnd net@11 1.489f +Rres@0 net@14 a 2.347 +Rres@1 net@11 net@14 4.694 +Rres@2 b net@8 2.347 +Rres@3 net@8 net@11 4.694 +.ENDS wire-C_0_011f-406_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-555_1-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-555_1-R_34_667m -.ENDS wire90-555_1-layer_1-width_3 +.SUBCKT wire90-406_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-406_2-R_34_667m +.ENDS wire90-406_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-677_1-R_34_667m a b -Ccap@0 gnd net@14 2.483f -Ccap@1 gnd net@8 2.483f -Ccap@2 gnd net@11 2.483f -Rres@0 net@14 a 3.912 -Rres@1 net@11 net@14 7.824 -Rres@2 b net@8 3.912 -Rres@3 net@8 net@11 7.824 -.ENDS wire-C_0_011f-677_1-R_34_667m +.SUBCKT wire-C_0_011f-488_9-R_34_667m a b +Ccap@0 gnd net@14 1.793f +Ccap@1 gnd net@8 1.793f +Ccap@2 gnd net@11 1.793f +Rres@0 net@14 a 2.825 +Rres@1 net@11 net@14 5.65 +Rres@2 b net@8 2.825 +Rres@3 net@8 net@11 5.65 +.ENDS wire-C_0_011f-488_9-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-677_1-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-677_1-R_34_667m -.ENDS wire90-677_1-layer_1-width_3 - -*** CELL: loopCountL:ringB{sch} -.SUBCKT ringB bit[1] count[F] count[T] do[1] inLO[1] load[F] load[T] -Xinv@0 net@60 bit[1] inv-X_20 -Xinv@1 bit[1] net@67 inv-X_5 -Xinv@2 net@68 net@65 inv-X_10 -Xinv@3 xx[T] net@64 inv-X_10 -Xmlat1in5@0 xx[T] xx[F] net@66 net@9 mlat1in5i -Xmlat1in5@1 count[T] count[F] do[1] net@77 mlat1in5i -Xmlat2in1@0 load[F] load[T] xx[F] xx[T] inLO[1] net@63 net@61 mlat2in10i -Xnor2n@0 net@78 count[F] net@84 nor2n-X_10 -Xwire90@1 net@67 net@68 wire90-173_2-layer_1-width_3 -Xwire90@2 net@65 net@66 wire90-381_1-layer_1-width_3 -Xwire90@3 net@60 net@61 wire90-981_4-layer_1-width_3 -Xwire90@5 net@63 net@9 wire90-523_4-layer_1-width_3 -Xwire90@6 net@64 xx[F] wire90-535_1-layer_1-width_3 -Xwire90@7 net@77 net@78 wire90-555_1-layer_1-width_3 -Xwire90@8 net@84 xx[T] wire90-677_1-layer_1-width_3 -.ENDS ringB +.SUBCKT wire90-488_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-488_9-R_34_667m +.ENDS wire90-488_9-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1350_3-R_34_667m a b -Ccap@0 gnd net@14 4.951f -Ccap@1 gnd net@8 4.951f -Ccap@2 gnd net@11 4.951f -Rres@0 net@14 a 7.802 -Rres@1 net@11 net@14 15.603 -Rres@2 b net@8 7.802 -Rres@3 net@8 net@11 15.603 -.ENDS wire-C_0_011f-1350_3-R_34_667m +.SUBCKT wire-C_0_011f-348_7-R_34_667m a b +Ccap@0 gnd net@14 1.279f +Ccap@1 gnd net@8 1.279f +Ccap@2 gnd net@11 1.279f +Rres@0 net@14 a 2.015 +Rres@1 net@11 net@14 4.029 +Rres@2 b net@8 2.015 +Rres@3 net@8 net@11 4.029 +.ENDS wire-C_0_011f-348_7-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1350_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1350_3-R_34_667m -.ENDS wire90-1350_3-layer_1-width_3 +.SUBCKT wire90-348_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-348_7-R_34_667m +.ENDS wire90-348_7-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-985_7-R_34_667m a b -Ccap@0 gnd net@14 3.614f -Ccap@1 gnd net@8 3.614f -Ccap@2 gnd net@11 3.614f -Rres@0 net@14 a 5.695 -Rres@1 net@11 net@14 11.39 -Rres@2 b net@8 5.695 -Rres@3 net@8 net@11 11.39 -.ENDS wire-C_0_011f-985_7-R_34_667m +.SUBCKT wire-C_0_011f-411_6-R_34_667m a b +Ccap@0 gnd net@14 1.509f +Ccap@1 gnd net@8 1.509f +Ccap@2 gnd net@11 1.509f +Rres@0 net@14 a 2.378 +Rres@1 net@11 net@14 4.756 +Rres@2 b net@8 2.378 +Rres@3 net@8 net@11 4.756 +.ENDS wire-C_0_011f-411_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-985_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-985_7-R_34_667m -.ENDS wire90-985_7-layer_1-width_3 +.SUBCKT wire90-411_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-411_6-R_34_667m +.ENDS wire90-411_6-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1915_8-R_34_667m a b -Ccap@0 gnd net@14 7.025f -Ccap@1 gnd net@8 7.025f -Ccap@2 gnd net@11 7.025f -Rres@0 net@14 a 11.069 -Rres@1 net@11 net@14 22.138 -Rres@2 b net@8 11.069 -Rres@3 net@8 net@11 22.138 -.ENDS wire-C_0_011f-1915_8-R_34_667m +.SUBCKT wire-C_0_011f-147_3-R_34_667m a b +Ccap@0 gnd net@14 0.54f +Ccap@1 gnd net@8 0.54f +Ccap@2 gnd net@11 0.54f +Rres@0 net@14 a 0.851 +Rres@1 net@11 net@14 1.702 +Rres@2 b net@8 0.851 +Rres@3 net@8 net@11 1.702 +.ENDS wire-C_0_011f-147_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1915_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1915_8-R_34_667m -.ENDS wire90-1915_8-layer_1-width_3 +.SUBCKT wire90-147_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-147_3-R_34_667m +.ENDS wire90-147_3-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1810_4-R_34_667m a b -Ccap@0 gnd net@14 6.638f -Ccap@1 gnd net@8 6.638f -Ccap@2 gnd net@11 6.638f -Rres@0 net@14 a 10.46 -Rres@1 net@11 net@14 20.92 -Rres@2 b net@8 10.46 -Rres@3 net@8 net@11 20.92 -.ENDS wire-C_0_011f-1810_4-R_34_667m +.SUBCKT wire-C_0_011f-143_2-R_34_667m a b +Ccap@0 gnd net@14 0.525f +Ccap@1 gnd net@8 0.525f +Ccap@2 gnd net@11 0.525f +Rres@0 net@14 a 0.827 +Rres@1 net@11 net@14 1.655 +Rres@2 b net@8 0.827 +Rres@3 net@8 net@11 1.655 +.ENDS wire-C_0_011f-143_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1810_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1810_4-R_34_667m -.ENDS wire90-1810_4-layer_1-width_3 - -*** CELL: loopCountL:ilcEvenZoo{sch} -.SUBCKT ilcEvenZoo bit[2] bit[4] bit[6] count do[2] do[4] do[6] ilc[i] -+inLO[2] inLO[4] inLO[6] inLO[8] kill load mc -Xinv@5 load[F] net@269 inv-X_30 -Xinv@6 count[F] net@271 inv-X_30 -Xinv@7 count net@273 inv-X_30 -Xinv@8 load net@275 inv-X_30 -XlatchZ10@0 gnd kill load[F] load[T] inLO[8] mc ilc[i] latchZ10@0_out[T] -+latchZ10 -XringB@0 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB -XringB@1 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB -XringB@2 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB -Xwire90@6 net@269 load[T] wire90-1350_3-layer_1-width_3 -Xwire90@7 net@271 count[T] wire90-985_7-layer_1-width_3 -Xwire90@8 net@273 count[F] wire90-1915_8-layer_1-width_3 -Xwire90@9 net@275 load[F] wire90-1810_4-layer_1-width_3 -.ENDS ilcEvenZoo - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1278-R_34_667m a b -Ccap@0 gnd net@14 4.686f -Ccap@1 gnd net@8 4.686f -Ccap@2 gnd net@11 4.686f -Rres@0 net@14 a 7.384 -Rres@1 net@11 net@14 14.768 -Rres@2 b net@8 7.384 -Rres@3 net@8 net@11 14.768 -.ENDS wire-C_0_011f-1278-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1278-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1278-R_34_667m -.ENDS wire90-1278-layer_1-width_3 +.SUBCKT wire90-143_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-143_2-R_34_667m +.ENDS wire90-143_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-2344-R_34_667m a b -Ccap@0 gnd net@14 8.595f -Ccap@1 gnd net@8 8.595f -Ccap@2 gnd net@11 8.595f -Rres@0 net@14 a 13.543 -Rres@1 net@11 net@14 27.086 -Rres@2 b net@8 13.543 -Rres@3 net@8 net@11 27.086 -.ENDS wire-C_0_011f-2344-R_34_667m +.SUBCKT wire-C_0_011f-368-R_34_667m a b +Ccap@0 gnd net@14 1.349f +Ccap@1 gnd net@8 1.349f +Ccap@2 gnd net@11 1.349f +Rres@0 net@14 a 2.126 +Rres@1 net@11 net@14 4.252 +Rres@2 b net@8 2.126 +Rres@3 net@8 net@11 4.252 +.ENDS wire-C_0_011f-368-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-2344-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-2344-R_34_667m -.ENDS wire90-2344-layer_1-width_3 +.SUBCKT wire90-368-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-368-R_34_667m +.ENDS wire90-368-layer_1-width_3 -*** CELL: loopCountL:ilcOddZoo{sch} -.SUBCKT ilcOddZoo bit[1] bit[3] bit[5] count dLO do[3] do[5] force0 inLO[1] -+inLO[3] inLO[5] inLO[7] kill load mc zLO -Xinv@3 load[F] net@269 inv-X_30 -Xinv@4 count[F] net@271 inv-X_30 -Xinv@5 count net@273 inv-X_30 -Xinv@6 load net@275 inv-X_30 -XlatchZ10@0 kill force0 load[F] load[T] inLO[7] mc zLO latchZ10@0_out[T] -+latchZ10 -XlatchZ10@1 kill force0 load[F] load[T] gnd mc dLO latchZ10@1_out[T] latchZ10 -XringB@0 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB -XringB@1 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB -XringB@2 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB -Xwire90@2 net@269 load[T] wire90-1350_3-layer_1-width_3 -Xwire90@3 net@271 count[T] wire90-1278-layer_1-width_3 -Xwire90@4 net@273 count[F] wire90-2344-layer_1-width_3 -Xwire90@5 net@275 load[F] wire90-1810_4-layer_1-width_3 -.ENDS ilcOddZoo +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-208_9-R_34_667m a b +Ccap@0 gnd net@14 0.766f +Ccap@1 gnd net@8 0.766f +Ccap@2 gnd net@11 0.766f +Rres@0 net@14 a 1.207 +Rres@1 net@11 net@14 2.414 +Rres@2 b net@8 1.207 +Rres@3 net@8 net@11 2.414 +.ENDS wire-C_0_011f-208_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-208_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-208_9-R_34_667m +.ENDS wire90-208_9-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-127_4-R_34_667m a b +Ccap@0 gnd net@14 0.467f +Ccap@1 gnd net@8 0.467f +Ccap@2 gnd net@11 0.467f +Rres@0 net@14 a 0.736 +Rres@1 net@11 net@14 1.472 +Rres@2 b net@8 0.736 +Rres@3 net@8 net@11 1.472 +.ENDS wire-C_0_011f-127_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-127_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-127_4-R_34_667m +.ENDS wire90-127_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-137_1-R_34_667m a b +Ccap@0 gnd net@14 0.503f +Ccap@1 gnd net@8 0.503f +Ccap@2 gnd net@11 0.503f +Rres@0 net@14 a 0.792 +Rres@1 net@11 net@14 1.584 +Rres@2 b net@8 0.792 +Rres@3 net@8 net@11 1.584 +.ENDS wire-C_0_011f-137_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-137_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-137_1-R_34_667m +.ENDS wire90-137_1-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1921_5-R_34_667m a b +Ccap@0 gnd net@14 7.046f +Ccap@1 gnd net@8 7.046f +Ccap@2 gnd net@11 7.046f +Rres@0 net@14 a 11.102 +Rres@1 net@11 net@14 22.204 +Rres@2 b net@8 11.102 +Rres@3 net@8 net@11 22.204 +.ENDS wire-C_0_011f-1921_5-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1921_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1921_5-R_34_667m +.ENDS wire90-1921_5-layer_1-width_3 + +*** CELL: loopCountM:olcControl{sch} +.SUBCKT olcControl Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] ++ilc[load] mc olc[dec] olc[load] olc[zero] olc[zoo] s[1] s[2] s[3] +XctrAND1i@0 net@527 net@165 ctrAND1in30 +XctrAND1i@3 net@519 ilc[load] ctrAND1in100 +XctrAND1i@4 net@547 net@162 ctrAND1in30 +XctrAND2i@3 do[2] net@339 olc[load] ctrAND2in100LT +XctrAND2i@5 olc[zero] net@547 olc[dec] ctrAND2in100 +Xinv@6 olc[zoo] net@180 inv-X_5 +Xinv@7 olc[zero] net@184 inv-X_5 +Xinv@14 do[Co] net@386 inv-X_10 +Xinv@16 Dvoid net@451 inv-X_5 +Xinv@18 flag[D][set] net@535 inv-X_5 +Xinv@19 flag[D][clr] net@539 inv-X_5 +XinvI@1 do[Ld] s[1] inv-X_10 +XinvI@2 net@538 s[3] inv-X_10 +XinvI@3 net@534 s[2] inv-X_10 +Xnand2@0 net@288 net@162 net@286 nand2-X_5 +Xnand2@1 net@289 net@165 net@284 nand2-X_5 +Xnand2@2 olc[zoo] net@162 net@279 nand2-X_5 +Xnand2@3 olc[zero] net@165 net@281 nand2-X_5 +Xnand2@4 Dvoid do[Ld] net@471 nand2-X_5 +Xnand2@5 net@455 do[Ld] net@438 nand2-X_5 +Xnor2_sy@1 do[reD] do[2] net@556 nor2_sy-X_5 +XpredDri2@0 net@358 mc do[2] predDri20wMC +XpredDri2@2 net@162 mc do[Co] predDri20wMC +XpredDri2@3 net@165 mc do[reD] predDri20wMC +XpredORdr@0 ilc[load] olc[load] mc do[Ld] predORdri20wMC +XsucDri20@0 olc[load] net@278 sucDri20 +XsucDri20@3 net@428 net@424 flag[D][clr] sucDri20or +XsucDri20@4 net@426 net@422 flag[D][set] sucDri20or +Xwire90@6 net@358 net@165 wire90-629_6-layer_1-width_3 +Xwire90@8 net@278 do[2] wire90-867_8-layer_1-width_3 +Xwire90@9 net@281 net@422 wire90-406_2-layer_1-width_3 +Xwire90@10 net@279 net@426 wire90-488_9-layer_1-width_3 +Xwire90@11 net@286 net@428 wire90-348_7-layer_1-width_3 +Xwire90@12 net@284 net@424 wire90-411_6-layer_1-width_3 +Xwire90@13 net@180 net@288 wire90-147_3-layer_1-width_3 +Xwire90@14 net@184 net@289 wire90-143_2-layer_1-width_3 +Xwire90@17 net@471 net@339 wire90-368-layer_1-width_3 +Xwire90@19 net@386 net@547 wire90-142_6-layer_1-width_3 +Xwire90@20 net@438 net@519 wire90-208_9-layer_1-width_3 +Xwire90@21 net@455 net@451 wire90-127_4-layer_1-width_3 +Xwire90@22 net@556 net@527 wire90-137_1-layer_1-width_3 +Xwire90@23 net@535 net@534 wire90-1921_5-layer_1-width_3 +Xwire90@24 net@539 net@538 wire90-1921_5-layer_1-width_3 +.ENDS olcControl + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-4231-R_34_667m a b +Ccap@0 gnd net@14 15.514f +Ccap@1 gnd net@8 15.514f +Ccap@2 gnd net@11 15.514f +Rres@0 net@14 a 24.446 +Rres@1 net@11 net@14 48.892 +Rres@2 b net@8 24.446 +Rres@3 net@8 net@11 48.892 +.ENDS wire-C_0_011f-4231-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-4231-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-4231-R_34_667m +.ENDS wire90-4231-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3133-R_34_667m a b +Ccap@0 gnd net@14 11.488f +Ccap@1 gnd net@8 11.488f +Ccap@2 gnd net@11 11.488f +Rres@0 net@14 a 18.102 +Rres@1 net@11 net@14 36.204 +Rres@2 b net@8 18.102 +Rres@3 net@8 net@11 36.204 +.ENDS wire-C_0_011f-3133-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3133-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3133-R_34_667m +.ENDS wire90-3133-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1028-R_34_667m a b +Ccap@0 gnd net@14 3.769f +Ccap@1 gnd net@8 3.769f +Ccap@2 gnd net@11 3.769f +Rres@0 net@14 a 5.94 +Rres@1 net@11 net@14 11.879 +Rres@2 b net@8 5.94 +Rres@3 net@8 net@11 11.879 +.ENDS wire-C_0_011f-1028-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1028-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1028-R_34_667m +.ENDS wire90-1028-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-852-R_34_667m a b +Ccap@0 gnd net@14 3.124f +Ccap@1 gnd net@8 3.124f +Ccap@2 gnd net@11 3.124f +Rres@0 net@14 a 4.923 +Rres@1 net@11 net@14 9.845 +Rres@2 b net@8 4.923 +Rres@3 net@8 net@11 9.845 +.ENDS wire-C_0_011f-852-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-852-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-852-R_34_667m +.ENDS wire90-852-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3750-R_34_667m a b +Ccap@0 gnd net@14 13.75f +Ccap@1 gnd net@8 13.75f +Ccap@2 gnd net@11 13.75f +Rres@0 net@14 a 21.667 +Rres@1 net@11 net@14 43.333 +Rres@2 b net@8 21.667 +Rres@3 net@8 net@11 43.333 +.ENDS wire-C_0_011f-3750-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3750-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3750-R_34_667m +.ENDS wire90-3750-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3560-R_34_667m a b +Ccap@0 gnd net@14 13.053f +Ccap@1 gnd net@8 13.053f +Ccap@2 gnd net@11 13.053f +Rres@0 net@14 a 20.569 +Rres@1 net@11 net@14 41.138 +Rres@2 b net@8 20.569 +Rres@3 net@8 net@11 41.138 +.ENDS wire-C_0_011f-3560-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3560-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3560-R_34_667m +.ENDS wire90-3560-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-374_2-R_34_667m a b -Ccap@0 gnd net@14 1.372f -Ccap@1 gnd net@8 1.372f -Ccap@2 gnd net@11 1.372f -Rres@0 net@14 a 2.162 -Rres@1 net@11 net@14 4.324 -Rres@2 b net@8 2.162 -Rres@3 net@8 net@11 4.324 -.ENDS wire-C_0_011f-374_2-R_34_667m +.SUBCKT wire-C_0_011f-3611-R_34_667m a b +Ccap@0 gnd net@14 13.24f +Ccap@1 gnd net@8 13.24f +Ccap@2 gnd net@11 13.24f +Rres@0 net@14 a 20.864 +Rres@1 net@11 net@14 41.727 +Rres@2 b net@8 20.864 +Rres@3 net@8 net@11 41.727 +.ENDS wire-C_0_011f-3611-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-374_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-374_2-R_34_667m -.ENDS wire90-374_2-layer_1-width_3 +.SUBCKT wire90-3611-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3611-R_34_667m +.ENDS wire90-3611-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-464_8-R_34_667m a b -Ccap@0 gnd net@14 1.704f -Ccap@1 gnd net@8 1.704f -Ccap@2 gnd net@11 1.704f -Rres@0 net@14 a 2.686 -Rres@1 net@11 net@14 5.371 -Rres@2 b net@8 2.686 -Rres@3 net@8 net@11 5.371 -.ENDS wire-C_0_011f-464_8-R_34_667m +.SUBCKT wire-C_0_011f-1850-R_34_667m a b +Ccap@0 gnd net@14 6.783f +Ccap@1 gnd net@8 6.783f +Ccap@2 gnd net@11 6.783f +Rres@0 net@14 a 10.689 +Rres@1 net@11 net@14 21.378 +Rres@2 b net@8 10.689 +Rres@3 net@8 net@11 21.378 +.ENDS wire-C_0_011f-1850-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-464_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-464_8-R_34_667m -.ENDS wire90-464_8-layer_1-width_3 +.SUBCKT wire90-1850-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1850-R_34_667m +.ENDS wire90-1850-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-398_8-R_34_667m a b -Ccap@0 gnd net@14 1.462f -Ccap@1 gnd net@8 1.462f -Ccap@2 gnd net@11 1.462f -Rres@0 net@14 a 2.304 -Rres@1 net@11 net@14 4.608 -Rres@2 b net@8 2.304 -Rres@3 net@8 net@11 4.608 -.ENDS wire-C_0_011f-398_8-R_34_667m +.SUBCKT wire-C_0_011f-1852-R_34_667m a b +Ccap@0 gnd net@14 6.791f +Ccap@1 gnd net@8 6.791f +Ccap@2 gnd net@11 6.791f +Rres@0 net@14 a 10.7 +Rres@1 net@11 net@14 21.401 +Rres@2 b net@8 10.7 +Rres@3 net@8 net@11 21.401 +.ENDS wire-C_0_011f-1852-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-398_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-398_8-R_34_667m -.ENDS wire90-398_8-layer_1-width_3 +.SUBCKT wire90-1852-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1852-R_34_667m +.ENDS wire90-1852-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-474_8-R_34_667m a b -Ccap@0 gnd net@14 1.741f -Ccap@1 gnd net@8 1.741f -Ccap@2 gnd net@11 1.741f -Rres@0 net@14 a 2.743 -Rres@1 net@11 net@14 5.487 -Rres@2 b net@8 2.743 -Rres@3 net@8 net@11 5.487 -.ENDS wire-C_0_011f-474_8-R_34_667m +.SUBCKT wire-C_0_011f-1616-R_34_667m a b +Ccap@0 gnd net@14 5.925f +Ccap@1 gnd net@8 5.925f +Ccap@2 gnd net@11 5.925f +Rres@0 net@14 a 9.337 +Rres@1 net@11 net@14 18.674 +Rres@2 b net@8 9.337 +Rres@3 net@8 net@11 18.674 +.ENDS wire-C_0_011f-1616-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-474_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-474_8-R_34_667m -.ENDS wire90-474_8-layer_1-width_3 +.SUBCKT wire90-1616-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1616-R_34_667m +.ENDS wire90-1616-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-399_8-R_34_667m a b -Ccap@0 gnd net@14 1.466f -Ccap@1 gnd net@8 1.466f -Ccap@2 gnd net@11 1.466f -Rres@0 net@14 a 2.31 -Rres@1 net@11 net@14 4.62 -Rres@2 b net@8 2.31 -Rres@3 net@8 net@11 4.62 -.ENDS wire-C_0_011f-399_8-R_34_667m +.SUBCKT wire-C_0_011f-809-R_34_667m a b +Ccap@0 gnd net@14 2.966f +Ccap@1 gnd net@8 2.966f +Ccap@2 gnd net@11 2.966f +Rres@0 net@14 a 4.674 +Rres@1 net@11 net@14 9.348 +Rres@2 b net@8 4.674 +Rres@3 net@8 net@11 9.348 +.ENDS wire-C_0_011f-809-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-399_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-399_8-R_34_667m -.ENDS wire90-399_8-layer_1-width_3 +.SUBCKT wire90-809-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-809-R_34_667m +.ENDS wire90-809-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-975_7-R_34_667m a b -Ccap@0 gnd net@14 3.578f -Ccap@1 gnd net@8 3.578f -Ccap@2 gnd net@11 3.578f -Rres@0 net@14 a 5.637 -Rres@1 net@11 net@14 11.275 -Rres@2 b net@8 5.637 -Rres@3 net@8 net@11 11.275 -.ENDS wire-C_0_011f-975_7-R_34_667m +.SUBCKT wire-C_0_011f-678-R_34_667m a b +Ccap@0 gnd net@14 2.486f +Ccap@1 gnd net@8 2.486f +Ccap@2 gnd net@11 2.486f +Rres@0 net@14 a 3.917 +Rres@1 net@11 net@14 7.835 +Rres@2 b net@8 3.917 +Rres@3 net@8 net@11 7.835 +.ENDS wire-C_0_011f-678-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-975_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-975_7-R_34_667m -.ENDS wire90-975_7-layer_1-width_3 +.SUBCKT wire90-678-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-678-R_34_667m +.ENDS wire90-678-layer_1-width_3 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1009_4-R_34_667m a b -Ccap@0 gnd net@14 3.701f -Ccap@1 gnd net@8 3.701f -Ccap@2 gnd net@11 3.701f -Rres@0 net@14 a 5.832 -Rres@1 net@11 net@14 11.664 -Rres@2 b net@8 5.832 -Rres@3 net@8 net@11 11.664 -.ENDS wire-C_0_011f-1009_4-R_34_667m +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3855-R_34_667m a b +Ccap@0 gnd net@14 14.135f +Ccap@1 gnd net@8 14.135f +Ccap@2 gnd net@11 14.135f +Rres@0 net@14 a 22.273 +Rres@1 net@11 net@14 44.547 +Rres@2 b net@8 22.273 +Rres@3 net@8 net@11 44.547 +.ENDS wire-C_0_011f-3855-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3855-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3855-R_34_667m +.ENDS wire90-3855-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3794-R_34_667m a b +Ccap@0 gnd net@14 13.911f +Ccap@1 gnd net@8 13.911f +Ccap@2 gnd net@11 13.911f +Rres@0 net@14 a 21.921 +Rres@1 net@11 net@14 43.842 +Rres@2 b net@8 21.921 +Rres@3 net@8 net@11 43.842 +.ENDS wire-C_0_011f-3794-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3794-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3794-R_34_667m +.ENDS wire90-3794-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3514-R_34_667m a b +Ccap@0 gnd net@14 12.885f +Ccap@1 gnd net@8 12.885f +Ccap@2 gnd net@11 12.885f +Rres@0 net@14 a 20.303 +Rres@1 net@11 net@14 40.606 +Rres@2 b net@8 20.303 +Rres@3 net@8 net@11 40.606 +.ENDS wire-C_0_011f-3514-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3514-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3514-R_34_667m +.ENDS wire90-3514-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3529-R_34_667m a b +Ccap@0 gnd net@14 12.94f +Ccap@1 gnd net@8 12.94f +Ccap@2 gnd net@11 12.94f +Rres@0 net@14 a 20.39 +Rres@1 net@11 net@14 40.78 +Rres@2 b net@8 20.39 +Rres@3 net@8 net@11 40.78 +.ENDS wire-C_0_011f-3529-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3529-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3529-R_34_667m +.ENDS wire90-3529-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3203-R_34_667m a b +Ccap@0 gnd net@14 11.744f +Ccap@1 gnd net@8 11.744f +Ccap@2 gnd net@11 11.744f +Rres@0 net@14 a 18.506 +Rres@1 net@11 net@14 37.012 +Rres@2 b net@8 18.506 +Rres@3 net@8 net@11 37.012 +.ENDS wire-C_0_011f-3203-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3203-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3203-R_34_667m +.ENDS wire90-3203-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3265-R_34_667m a b +Ccap@0 gnd net@14 11.972f +Ccap@1 gnd net@8 11.972f +Ccap@2 gnd net@11 11.972f +Rres@0 net@14 a 18.864 +Rres@1 net@11 net@14 37.729 +Rres@2 b net@8 18.864 +Rres@3 net@8 net@11 37.729 +.ENDS wire-C_0_011f-3265-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3265-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3265-R_34_667m +.ENDS wire90-3265-layer_1-width_3 + +*** CELL: dockPartsM:dockCenterTry2{sch} +.SUBCKT dockCenterTry2 Dvoid bit[Di] bit[Ti] bitt[10] bitt[11] bitt[12] ++bitt[13] bitt[14] bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] ++bitt[8] bitt[9] do[Co] do[Ld] fire[M] flag[A][clr] flag[A][set] flag[B][clr] ++flag[B][set] flag[C][F] flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] ++inLO[3] inLO[4] inLO[5] inLO[6] inLO[7] m1[10] m1[11] m1[12] m1[1] m1[2] ++m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc pred[D] pred[T] ready s[10] s[1] ++s[2] s[3] s[4] s[5] s[6] s[7] s[8] s[9] torp +Xflags@0 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][F] ++flag[C][T] m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] ++m1[8] m1[9] mc flags +Xilc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8] ++ilc[ck] ilc[decLO] ilc[do] ilc[ho] ilc[load] ilc[mo] inLO[1] inLO[2] inLO[3] ++inLO[4] inLO[5] inLO[6] inLO[7] ilc +XmoveAll@0 bit[Di] bit[Ti] do[Mv] do[Tp] moveAll@0_do[reD] fire[M] ++flag[D][set] net@89 net@93 ilc[do] ilc[ho] ilc[mo] mc pred[D] pred[T] ready ++s[1] s[2] s[3] s[4] s[5] torp moveAll +Xolc@0 bitt[9] bitt[10] bitt[11] bitt[12] bitt[13] bitt[14] inLO[1] inLO[2] ++inLO[3] inLO[4] inLO[5] inLO[6] olc[dec] olc[load] olc[zero] olc[zoo] olc +XolcContr@0 Dvoid do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] net@81 mc ++olc[dec] olc[load] olc[zero] olc[zoo] s[8] s[9] s[10] olcControl +Xwire90@1 wire90@1_a olc[load] wire90-4231-layer_1-width_3 +Xwire90@2 wire90@2_a olc[dec] wire90-3133-layer_1-width_3 +Xwire90@3 wire90@3_a olc[zero] wire90-1028-layer_1-width_3 +Xwire90@4 wire90@4_a olc[zoo] wire90-852-layer_1-width_3 +Xwire90@5 wire90@5_a flag[A][set] wire90-3750-layer_1-width_3 +Xwire90@6 wire90@6_a flag[A][clr] wire90-3560-layer_1-width_3 +Xwire90@7 wire90@7_a flag[B][set] wire90-3750-layer_1-width_3 +Xwire90@8 wire90@8_a flag[B][clr] wire90-3611-layer_1-width_3 +Xwire90@9 wire90@9_a flag[D][set] wire90-1850-layer_1-width_3 +Xwire90@10 wire90@10_a flag[D][clr] wire90-1852-layer_1-width_3 +Xwire90@11 wire90@11_a ilc[mo] wire90-1616-layer_1-width_3 +Xwire90@12 wire90@12_a ilc[do] wire90-809-layer_1-width_3 +Xwire90@13 wire90@13_a ilc[ho] wire90-678-layer_1-width_3 +Xwire90@15 wire90@15_a inLO[1] wire90-3855-layer_1-width_3 +Xwire90@16 wire90@16_a inLO[2] wire90-3794-layer_1-width_3 +Xwire90@17 wire90@17_a inLO[3] wire90-3514-layer_1-width_3 +Xwire90@18 wire90@18_a inLO[4] wire90-3529-layer_1-width_3 +Xwire90@19 wire90@19_a inLO[5] wire90-3203-layer_1-width_3 +Xwire90@20 wire90@20_a inLO[6] wire90-3265-layer_1-width_3 +Xwire90@21 ilc[load] net@81 wire90-867_8-layer_1-width_3 +Xwire90@22 net@89 ilc[ck] wire90-867_8-layer_1-width_3 +Xwire90@23 net@93 ilc[decLO] wire90-867_8-layer_1-width_3 +.ENDS dockCenterTry2 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1009_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1009_4-R_34_667m -.ENDS wire90-1009_4-layer_1-width_3 +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_2 d g s +MNMOSf@0 d g s gnd nch W='6*(1+ABN/sqrt(6*2))' L='2' DELVTO='AVT0N/sqrt(6*2)' +.ENDS NMOSx-X_2 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-905_8-R_34_667m a b -Ccap@0 gnd net@14 3.321f -Ccap@1 gnd net@8 3.321f -Ccap@2 gnd net@11 3.321f -Rres@0 net@14 a 5.234 -Rres@1 net@11 net@14 10.467 -Rres@2 b net@8 5.234 -Rres@3 net@8 net@11 10.467 -.ENDS wire-C_0_011f-905_8-R_34_667m +*** CELL: redFive:pms2_sy{sch} +.SUBCKT pms2_sy-X_4 d g g2 +Xpms2@0 d g g2 pms2-X_2 +Xpms2@1 d g2 g pms2-X_2 +.ENDS pms2_sy-X_4 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-905_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-905_8-R_34_667m -.ENDS wire90-905_8-layer_1-width_3 +*** CELL: redFive:nor2HT_sy{sch} +.SUBCKT nor2HT_sy-X_4 ina inb out +XNMOS@0 out inb gnd NMOSx-X_2 +XNMOS@1 out ina gnd NMOSx-X_2 +Xpms2_sy@0 out ina inb pms2_sy-X_4 +.ENDS nor2HT_sy-X_4 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-758_3-R_34_667m a b -Ccap@0 gnd net@14 2.78f -Ccap@1 gnd net@8 2.78f -Ccap@2 gnd net@11 2.78f -Rres@0 net@14 a 4.381 -Rres@1 net@11 net@14 8.763 -Rres@2 b net@8 4.381 -Rres@3 net@8 net@11 8.763 -.ENDS wire-C_0_011f-758_3-R_34_667m +.SUBCKT wire-C_0_011f-238_2-R_34_667m a b +Ccap@0 gnd net@14 0.873f +Ccap@1 gnd net@8 0.873f +Ccap@2 gnd net@11 0.873f +Rres@0 net@14 a 1.376 +Rres@1 net@11 net@14 2.753 +Rres@2 b net@8 1.376 +Rres@3 net@8 net@11 2.753 +.ENDS wire-C_0_011f-238_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-758_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-758_3-R_34_667m -.ENDS wire90-758_3-layer_1-width_3 +.SUBCKT wire90-238_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-238_2-R_34_667m +.ENDS wire90-238_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-643_7-R_34_667m a b -Ccap@0 gnd net@14 2.36f -Ccap@1 gnd net@8 2.36f -Ccap@2 gnd net@11 2.36f -Rres@0 net@14 a 3.719 -Rres@1 net@11 net@14 7.438 -Rres@2 b net@8 3.719 -Rres@3 net@8 net@11 7.438 -.ENDS wire-C_0_011f-643_7-R_34_667m +.SUBCKT wire-C_0_011f-520-R_34_667m a b +Ccap@0 gnd net@14 1.907f +Ccap@1 gnd net@8 1.907f +Ccap@2 gnd net@11 1.907f +Rres@0 net@14 a 3.004 +Rres@1 net@11 net@14 6.009 +Rres@2 b net@8 3.004 +Rres@3 net@8 net@11 6.009 +.ENDS wire-C_0_011f-520-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-643_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-643_7-R_34_667m -.ENDS wire90-643_7-layer_1-width_3 +.SUBCKT wire90-520-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-520-R_34_667m +.ENDS wire90-520-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-561_7-R_34_667m a b -Ccap@0 gnd net@14 2.06f -Ccap@1 gnd net@8 2.06f -Ccap@2 gnd net@11 2.06f -Rres@0 net@14 a 3.245 -Rres@1 net@11 net@14 6.491 -Rres@2 b net@8 3.245 -Rres@3 net@8 net@11 6.491 -.ENDS wire-C_0_011f-561_7-R_34_667m +.SUBCKT wire-C_0_011f-222_3-R_34_667m a b +Ccap@0 gnd net@14 0.815f +Ccap@1 gnd net@8 0.815f +Ccap@2 gnd net@11 0.815f +Rres@0 net@14 a 1.284 +Rres@1 net@11 net@14 2.569 +Rres@2 b net@8 1.284 +Rres@3 net@8 net@11 2.569 +.ENDS wire-C_0_011f-222_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-561_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-561_7-R_34_667m -.ENDS wire90-561_7-layer_1-width_3 +.SUBCKT wire90-222_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-222_3-R_34_667m +.ENDS wire90-222_3-layer_1-width_3 + +*** CELL: centersJ:ctrAND4in30{sch} +.SUBCKT ctrAND4in30 inA inB inC inD out +Xinv@1 net@3 out inv-X_30 +Xnand2@1 net@43 net@58 net@67 nand2-X_10 +Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4 +Xnor2n@0 inD inC net@64 nor2n-X_5 +Xwire90@0 net@64 net@43 wire90-238_2-layer_1-width_3 +Xwire90@1 net@67 net@3 wire90-520-layer_1-width_3 +Xwire90@2 net@61 net@58 wire90-222_3-layer_1-width_3 +.ENDS ctrAND4in30 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-898_9-R_34_667m a b -Ccap@0 gnd net@14 3.296f -Ccap@1 gnd net@8 3.296f -Ccap@2 gnd net@11 3.296f -Rres@0 net@14 a 5.194 -Rres@1 net@11 net@14 10.387 -Rres@2 b net@8 5.194 -Rres@3 net@8 net@11 10.387 -.ENDS wire-C_0_011f-898_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-898_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-898_9-R_34_667m -.ENDS wire90-898_9-layer_1-width_3 - -*** CELL: loopCountL:ilcZoo{sch} -.SUBCKT ilcZoo bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] ilc[cnt] -+ilc[dLO] ilc[i] ilc[load] ilc[zLO] ilc[zoo] inLO[1] inLO[2] inLO[3] inLO[4] -+inLO[5] inLO[6] inLO[7] inLO[8] kill mc -XcountLog@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] ilc[cnt] do[2] -+do[3] do[4] do[5] do[6] force0 ilc[zoo] countLogicZoo -XilcEvenZ@0 bitt[2] bitt[4] bitt[6] ilc[cnt] do[2] do[4] do[6] ilc[i] inLO[2] -+inLO[4] inLO[6] inLO[8] kill net@109 mc ilcEvenZoo -XilcOddZo@0 bitt[1] bitt[3] bitt[5] ilc[cnt] ilc[dLO] do[3] do[5] force0 -+inLO[1] inLO[3] inLO[5] inLO[7] kill net@109 mc ilc[zLO] ilcOddZoo -Xinv@4 ilc[load] net@304 inv-X_30 -Xwire90@1 wire90@1_a do[2] wire90-374_2-layer_1-width_3 -Xwire90@2 wire90@2_a do[3] wire90-464_8-layer_1-width_3 -Xwire90@3 wire90@3_a do[4] wire90-398_8-layer_1-width_3 -Xwire90@4 wire90@4_a do[5] wire90-474_8-layer_1-width_3 -Xwire90@5 wire90@5_a do[6] wire90-383_8-layer_1-width_3 -Xwire90@6 wire90@6_a force0 wire90-399_8-layer_1-width_3 -Xwire90@7 wire90@7_a bitt[1] wire90-975_7-layer_1-width_3 -Xwire90@8 wire90@8_a bitt[2] wire90-1009_4-layer_1-width_3 -Xwire90@9 wire90@9_a bitt[3] wire90-905_8-layer_1-width_3 -Xwire90@10 wire90@10_a bitt[4] wire90-758_3-layer_1-width_3 -Xwire90@11 wire90@11_a bitt[5] wire90-643_7-layer_1-width_3 -Xwire90@12 wire90@12_a bitt[6] wire90-561_7-layer_1-width_3 -Xwire90@35 net@109 net@304 wire90-898_9-layer_1-width_3 -.ENDS ilcZoo +.SUBCKT wire-C_0_011f-162_4-R_34_667m a b +Ccap@0 gnd net@14 0.595f +Ccap@1 gnd net@8 0.595f +Ccap@2 gnd net@11 0.595f +Rres@0 net@14 a 0.938 +Rres@1 net@11 net@14 1.877 +Rres@2 b net@8 0.938 +Rres@3 net@8 net@11 1.877 +.ENDS wire-C_0_011f-162_4-R_34_667m -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_9_999 d g s -MNMOSf@0 d g s gnd nch W='29.997*(1+ABN/sqrt(29.997*2))' L='2' -+DELVTO='AVT0N/sqrt(29.997*2)' -.ENDS NMOSx-X_9_999 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-162_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-162_4-R_34_667m +.ENDS wire90-162_4-layer_1-width_3 -*** CELL: redFour:nms3{sch} -.SUBCKT nms3-X_3_333 d g g2 g3 -XNMOS@0 d g3 net@6 NMOSx-X_9_999 -XNMOS@1 net@7 g gnd NMOSx-X_9_999 -XNMOS@2 net@6 g2 net@7 NMOSx-X_9_999 -.ENDS nms3-X_3_333 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-228_5-R_34_667m a b +Ccap@0 gnd net@14 0.838f +Ccap@1 gnd net@8 0.838f +Ccap@2 gnd net@11 0.838f +Rres@0 net@14 a 1.32 +Rres@1 net@11 net@14 2.64 +Rres@2 b net@8 1.32 +Rres@3 net@8 net@11 2.64 +.ENDS wire-C_0_011f-228_5-R_34_667m -*** CELL: gatesK:nand3in6.6sym{sch} -.SUBCKT nand3in6_6sym inA inB inC out -XPMOSx@1 out inA vdd PMOSx-X_10 -XPMOSx@3 out inC vdd PMOSx-X_10 -XPMOSx@4 out inB vdd PMOSx-X_10 -Xnms3@0 out inA inB inC nms3-X_3_333 -Xnms3@2 out inC inB inA nms3-X_3_333 -.ENDS nand3in6_6sym +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-228_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-228_5-R_34_667m +.ENDS wire90-228_5-layer_1-width_3 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-279_2-R_34_667m a b -Ccap@0 gnd net@14 1.024f -Ccap@1 gnd net@8 1.024f -Ccap@2 gnd net@11 1.024f -Rres@0 net@14 a 1.613 -Rres@1 net@11 net@14 3.226 -Rres@2 b net@8 1.613 -Rres@3 net@8 net@11 3.226 -.ENDS wire-C_0_011f-279_2-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-279_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-279_2-R_34_667m -.ENDS wire90-279_2-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-262_2-R_34_667m a b -Ccap@0 gnd net@14 0.961f -Ccap@1 gnd net@8 0.961f -Ccap@2 gnd net@11 0.961f -Rres@0 net@14 a 1.515 -Rres@1 net@11 net@14 3.03 -Rres@2 b net@8 1.515 -Rres@3 net@8 net@11 3.03 -.ENDS wire-C_0_011f-262_2-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-262_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-262_2-R_34_667m -.ENDS wire90-262_2-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-423_2-R_34_667m a b -Ccap@0 gnd net@14 1.552f -Ccap@1 gnd net@8 1.552f -Ccap@2 gnd net@11 1.552f -Rres@0 net@14 a 2.445 -Rres@1 net@11 net@14 4.89 -Rres@2 b net@8 2.445 -Rres@3 net@8 net@11 4.89 -.ENDS wire-C_0_011f-423_2-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-423_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-423_2-R_34_667m -.ENDS wire90-423_2-layer_1-width_3 - -*** CELL: loopCountL:extZeroB{sch} -.SUBCKT extZeroB in[1] in[2] in[3] in[4] in[5] in[6] out -Xnand3in6@4 net@2 net@21 net@4 out nand3in6_6sym -Xnor2n_sy@2 in[5] in[4] net@27 nor2n_sy-X_5 -Xnor2n_sy@4 in[2] in[6] net@19 nor2n_sy-X_5 -Xnor2n_sy@5 in[1] in[3] net@29 nor2n_sy-X_5 -Xwire90@0 net@27 net@2 wire90-279_2-layer_1-width_3 -Xwire90@1 net@4 net@29 wire90-262_2-layer_1-width_3 -Xwire90@2 net@19 net@21 wire90-423_2-layer_1-width_3 -.ENDS extZeroB - -*** CELL: redFour:triInv{sch} -.SUBCKT triInv-X_10 en enB in out -Xnms2@0 out in en nms2-X_10 -Xpms2@0 out in enB pms2-X_10 -.ENDS triInv-X_10 - -*** CELL: loopCountL:mux10/2by8zero{sch} -.SUBCKT mux10/2by8zero in[1] in[2] in[3] in[4] in[5] in[6] in[8] out[1] -+out[2] out[3] out[4] out[5] out[6] out[7] out[8] s[F] s[T] -XextZeroB@1 in[1] in[2] in[3] in[4] in[5] in[6] in[x] extZeroB -Xmux[1] s[T] s[F] in[1] out[1] triInv-X_10 -Xmux[2] s[T] s[F] in[2] out[2] triInv-X_10 -Xmux[3] s[T] s[F] in[3] out[3] triInv-X_10 -Xmux[4] s[T] s[F] in[4] out[4] triInv-X_10 -Xmux[5] s[T] s[F] in[5] out[5] triInv-X_10 -Xmux[6] s[T] s[F] in[6] out[6] triInv-X_10 -Xmux[7] s[T] s[F] in[x] out[7] triInv-X_10 -Xmux[8] s[T] s[F] in[8] out[8] triInv-X_10 -.ENDS mux10/2by8zero +*** CELL: latchesK:rsLatchA{sch} +.SUBCKT rsLatchA mc out outBar reset set +XNMOSx@0 net@193 reset gnd NMOSx-X_10 +XNMOSx@1 net@188 mc gnd NMOSx-X_4 +XPMOSx@3 net@188 net@177 vdd PMOSx-X_10 +Xinv@0 net@193 outBar inv-X_10 +Xinv@1 set net@213 inv-X_4 +Xinv@2 outBar out inv-X_10 +Xnms2@0 net@188 outBar net@177 nms2-X_2 +Xpms3@0 net@193 mc outBar reset pms3-X_1 +Xwire90@0 net@213 net@177 wire90-162_4-layer_1-width_3 +Xwire90@1 net@188 net@193 wire90-228_5-layer_1-width_3 +.ENDS rsLatchA *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-2740_3-R_34_667m a b -Ccap@0 gnd net@14 10.048f -Ccap@1 gnd net@8 10.048f -Ccap@2 gnd net@11 10.048f -Rres@0 net@14 a 15.833 -Rres@1 net@11 net@14 31.666 -Rres@2 b net@8 15.833 -Rres@3 net@8 net@11 31.666 -.ENDS wire-C_0_011f-2740_3-R_34_667m +.SUBCKT wire-C_0_011f-468-R_34_667m a b +Ccap@0 gnd net@14 1.716f +Ccap@1 gnd net@8 1.716f +Ccap@2 gnd net@11 1.716f +Rres@0 net@14 a 2.704 +Rres@1 net@11 net@14 5.408 +Rres@2 b net@8 2.704 +Rres@3 net@8 net@11 5.408 +.ENDS wire-C_0_011f-468-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-2740_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-2740_3-R_34_667m -.ENDS wire90-2740_3-layer_1-width_3 +.SUBCKT wire90-468-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-468-R_34_667m +.ENDS wire90-468-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-2463-R_34_667m a b -Ccap@0 gnd net@14 9.031f -Ccap@1 gnd net@8 9.031f -Ccap@2 gnd net@11 9.031f -Rres@0 net@14 a 14.231 -Rres@1 net@11 net@14 28.461 -Rres@2 b net@8 14.231 -Rres@3 net@8 net@11 28.461 -.ENDS wire-C_0_011f-2463-R_34_667m +.SUBCKT wire-C_0_011f-347_9-R_34_667m a b +Ccap@0 gnd net@14 1.276f +Ccap@1 gnd net@8 1.276f +Ccap@2 gnd net@11 1.276f +Rres@0 net@14 a 2.01 +Rres@1 net@11 net@14 4.02 +Rres@2 b net@8 2.01 +Rres@3 net@8 net@11 4.02 +.ENDS wire-C_0_011f-347_9-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-2463-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-2463-R_34_667m -.ENDS wire90-2463-layer_1-width_3 - -*** CELL: loopCountL:inMux{sch} -.SUBCKT inMux inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inB[1] inB[2] inB[3] -+inB[4] inB[5] inB[6] inB[8] out[1] out[2] out[3] out[4] out[5] out[6] out[7] -+out[8] sel[A] -Xinv@0 sel[A] net@10 inv-X_20 -Xinv@1 s[F] net@12 inv-X_20 -Xmux10/2b@0 inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] gnd out[1] out[2] -+out[3] out[4] out[5] out[6] out[7] out[8] s[F] s[T] mux10/2by8zero -Xmux10/2b@1 inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[8] out[1] out[2] -+out[3] out[4] out[5] out[6] out[7] out[8] s[T] s[F] mux10/2by8zero -Xwire90@0 net@10 s[F] wire90-2740_3-layer_1-width_3 -Xwire90@1 net@12 s[T] wire90-2463-layer_1-width_3 -.ENDS inMux - -*** CELL: loopCountL:countLogic{sch} -.SUBCKT countLogic bit[1] bit[2] bit[3] bit[4] bit[5] bit[6] do[2] do[3] -+do[4] do[5] do[6] zoo -Xinv@0 net@257 do[2] inv-X_10 -Xinv@1 bit[2] net@128 inv-X_10 -Xinv@2 bit[1] net@257 inv-X_10 -Xnand2@0 bit[3] bit[1] net@145 nand2-X_10 -Xnand2@1 bit[4] bit[2] net@195 nand2-X_10 -Xnand2@2 bit[3] bit[5] net@315 nand2-X_10 -Xnand3@0 bit[5] bit[3] bit[1] net@264 nand3-X_6_667 -Xnand3@1 bit[6] bit[4] bit[2] net@198 nand3-X_6_667 -Xnor2n@1 net@128 net@257 do[3] nor2n-X_10 -Xnor2n@2 net@145 net@146 do[4] nor2n-X_10 -Xnor2n@3 net@195 net@58 do[5] nor2n-X_10 -Xnor2n@4 net@221 net@56 do[6] nor2n-X_10 -Xnor2n@5 net@289 net@267 zoo nor2n-X_10 -Xwire90@0 net@264 net@221 wire90-549_2-layer_1-width_3 -Xwire90@1 net@58 net@145 wire90-703_8-layer_1-width_3 -Xwire90@3 net@56 net@195 wire90-703_8-layer_1-width_3 -Xwire90@5 net@198 net@289 wire90-543_6-layer_1-width_3 -Xwire90@6 net@146 net@128 wire90-645_3-layer_1-width_3 -Xwire90@8 net@267 net@315 wire90-378_8-layer_1-width_3 -.ENDS countLogic +.SUBCKT wire90-347_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-347_9-R_34_667m +.ENDS wire90-347_9-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-836_8-R_34_667m a b -Ccap@0 gnd net@14 3.068f -Ccap@1 gnd net@8 3.068f -Ccap@2 gnd net@11 3.068f -Rres@0 net@14 a 4.835 -Rres@1 net@11 net@14 9.67 -Rres@2 b net@8 4.835 -Rres@3 net@8 net@11 9.67 -.ENDS wire-C_0_011f-836_8-R_34_667m +.SUBCKT wire-C_0_011f-450_6-R_34_667m a b +Ccap@0 gnd net@14 1.652f +Ccap@1 gnd net@8 1.652f +Ccap@2 gnd net@11 1.652f +Rres@0 net@14 a 2.603 +Rres@1 net@11 net@14 5.207 +Rres@2 b net@8 2.603 +Rres@3 net@8 net@11 5.207 +.ENDS wire-C_0_011f-450_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-836_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-836_8-R_34_667m -.ENDS wire90-836_8-layer_1-width_3 +.SUBCKT wire90-450_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-450_6-R_34_667m +.ENDS wire90-450_6-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1053_4-R_34_667m a b -Ccap@0 gnd net@14 3.862f -Ccap@1 gnd net@8 3.862f -Ccap@2 gnd net@11 3.862f -Rres@0 net@14 a 6.086 -Rres@1 net@11 net@14 12.173 -Rres@2 b net@8 6.086 -Rres@3 net@8 net@11 12.173 -.ENDS wire-C_0_011f-1053_4-R_34_667m +.SUBCKT wire-C_0_011f-603_6-R_34_667m a b +Ccap@0 gnd net@14 2.213f +Ccap@1 gnd net@8 2.213f +Ccap@2 gnd net@11 2.213f +Rres@0 net@14 a 3.487 +Rres@1 net@11 net@14 6.975 +Rres@2 b net@8 3.487 +Rres@3 net@8 net@11 6.975 +.ENDS wire-C_0_011f-603_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1053_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1053_4-R_34_667m -.ENDS wire90-1053_4-layer_1-width_3 +.SUBCKT wire90-603_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-603_6-R_34_667m +.ENDS wire90-603_6-layer_1-width_3 + +*** CELL: gaspM:anAltEnd{sch} +.SUBCKT anAltEnd fire[A] fire[B] mc predA predB s[1] s[2] s[3] succ +XctrAND4i@2 net@1013 succ net@1133 fire[B] fire[A] ctrAND4in30 +XctrAND4i@3 net@1007 succ fire[A] net@1155 fire[B] ctrAND4in30 +Xinv@3 net@822 s[1] inv-X_10 +Xinv@4 net@824 s[3] inv-X_10 +Xinv@5 predA net@822 inv-X_5 +Xinv@6 predB net@824 inv-X_5 +Xinv@7 net@1133 s[2] inv-X_10 +XpredDri2@0 fire[A] mc predA predDri20wMC +XpredDri2@1 fire[B] mc predB predDri20wMC +XrsLatchA@1 mc net@1040 net@1082 fire[B] fire[A] rsLatchA +XsucORdri@0 fire[A] fire[B] succ sucORdri20 +Xwire90@34 net@824 net@1007 wire90-468-layer_1-width_3 +Xwire90@35 net@822 net@1013 wire90-347_9-layer_1-width_3 +Xwire90@36 net@1155 net@1082 wire90-450_6-layer_1-width_3 +Xwire90@37 net@1133 net@1040 wire90-603_6-layer_1-width_3 +.ENDS anAltEnd + +*** CELL: scanM:scanEx3{sch} +.SUBCKT scanEx3 dIn[1] dIn[2] dIn[3] mc sir[1] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sor[1] +XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanM__scanCellE +XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanM__scanCellE +XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sor[1] scanM__scanCellE +Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3 +Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3 +.ENDS scanEx3 + +*** CELL: stagesM:altEndDockStage{sch} +.SUBCKT altEndDockStage inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] ++inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] ++inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] ++inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7] ++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17] ++inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25] ++inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33] ++inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9] ++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] ++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] ++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] ++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] predA predB ++sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ +XanAltEnd@1 fire[A] fire[B] sir[9] predA predB s[1] s[2] s[3] succ anAltEnd +Xins2in20@0 take[A] take[B] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] ++inA[16] inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] ++inA[24] inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] ++inA[32] inA[33] inA[34] inA[35] inA[36] inA[3] inA[4] inA[5] inA[6] inA[7] ++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17] ++inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25] ++inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33] ++inB[34] inB[35] inB[36] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9] ++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] ++out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] ++out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] ++out[35] out[36] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ins2in20Ax36 +XlatchDri@0 net@3 net@27 latchDriver60 +XlatchDri@1 net@7 net@23 latchDriver60 +XscanEx3@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sor[1] scanEx3 +Xwire90@0 net@7 fire[B] wire90-1336_2-layer_1-width_3 +Xwire90@1 net@3 fire[A] wire90-1307-layer_1-width_3 +Xwire90@2 net@23 take[B] wire90-1336_2-layer_1-width_3 +Xwire90@3 net@27 take[A] wire90-1307-layer_1-width_3 +.ENDS altEndDockStage *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1764_4-R_34_667m a b -Ccap@0 gnd net@14 6.469f -Ccap@1 gnd net@8 6.469f -Ccap@2 gnd net@11 6.469f -Rres@0 net@14 a 10.194 -Rres@1 net@11 net@14 20.389 -Rres@2 b net@8 10.194 -Rres@3 net@8 net@11 20.389 -.ENDS wire-C_0_011f-1764_4-R_34_667m +.SUBCKT wire-C_0_011f-237_2-R_34_667m a b +Ccap@0 gnd net@14 0.87f +Ccap@1 gnd net@8 0.87f +Ccap@2 gnd net@11 0.87f +Rres@0 net@14 a 1.37 +Rres@1 net@11 net@14 2.741 +Rres@2 b net@8 1.37 +Rres@3 net@8 net@11 2.741 +.ENDS wire-C_0_011f-237_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1764_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1764_4-R_34_667m -.ENDS wire90-1764_4-layer_1-width_3 +.SUBCKT wire90-237_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-237_2-R_34_667m +.ENDS wire90-237_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1373_4-R_34_667m a b -Ccap@0 gnd net@14 5.036f -Ccap@1 gnd net@8 5.036f -Ccap@2 gnd net@11 5.036f -Rres@0 net@14 a 7.935 -Rres@1 net@11 net@14 15.87 -Rres@2 b net@8 7.935 -Rres@3 net@8 net@11 15.87 -.ENDS wire-C_0_011f-1373_4-R_34_667m +.SUBCKT wire-C_0_011f-221_8-R_34_667m a b +Ccap@0 gnd net@14 0.813f +Ccap@1 gnd net@8 0.813f +Ccap@2 gnd net@11 0.813f +Rres@0 net@14 a 1.282 +Rres@1 net@11 net@14 2.563 +Rres@2 b net@8 1.282 +Rres@3 net@8 net@11 2.563 +.ENDS wire-C_0_011f-221_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1373_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1373_4-R_34_667m -.ENDS wire90-1373_4-layer_1-width_3 +.SUBCKT wire90-221_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-221_8-R_34_667m +.ENDS wire90-221_8-layer_1-width_3 -*** CELL: loopCountL:olcEven{sch} -.SUBCKT olcEven bit[2] bit[4] bit[6] count[2] do[2] do[4] do[6] inLO[2] -+inLO[4] inLO[6] load[2] -Xinv@0 count[F] net@196 inv-X_20 -Xinv@1 load[F] net@207 inv-X_20 -Xinv@2 count[2] net@210 inv-X_30 -Xinv@3 load[2] net@211 inv-X_30 -XringB@0 bit[4] count[F] count[T] do[4] inLO[4] load[F] load[T] ringB -XringB@1 bit[2] count[F] count[T] do[2] inLO[2] load[F] load[T] ringB -XringB@2 bit[6] count[F] count[T] do[6] inLO[6] load[F] load[T] ringB -Xwire90@1 net@196 count[T] wire90-836_8-layer_1-width_3 -Xwire90@2 net@207 load[T] wire90-1053_4-layer_1-width_3 -Xwire90@3 net@210 count[F] wire90-1764_4-layer_1-width_3 -Xwire90@4 net@211 load[F] wire90-1373_4-layer_1-width_3 -.ENDS olcEven +*** CELL: centersJ:ctrAND4in30M{sch} +.SUBCKT ctrAND4in30M inA inB inC inD out outM +Xinv@1 outM out inv-X_30 +Xnand2@1 net@43 net@58 outM nand2-X_10 +Xnor2HT_s@1 inA inB net@61 nor2HT_sy-X_4 +Xnor2n@0 inD inC net@64 nor2n-X_5 +Xwire90@0 net@64 net@43 wire90-237_2-layer_1-width_3 +Xwire90@2 net@61 net@58 wire90-221_8-layer_1-width_3 +.ENDS ctrAND4in30M -*** CELL: loopCountL:olcOdd{sch} -.SUBCKT olcOdd bit[1] bit[3] bit[5] count[1] do[3] do[5] inLO[1] inLO[3] -+inLO[5] load[1] -Xinv@0 count[F] net@299 inv-X_20 -Xinv@1 load[F] net@300 inv-X_20 -Xinv@2 load[1] net@307 inv-X_30 -Xinv@3 count[1] net@310 inv-X_30 -XringB@0 bit[5] count[F] count[T] do[5] inLO[5] load[F] load[T] ringB -XringB@1 bit[3] count[F] count[T] do[3] inLO[3] load[F] load[T] ringB -XringB@2 bit[1] count[F] count[T] vdd inLO[1] load[F] load[T] ringB -Xwire90@0 net@299 count[T] wire90-836_8-layer_1-width_3 -Xwire90@1 net@300 load[T] wire90-1053_4-layer_1-width_3 -Xwire90@2 net@307 load[F] wire90-1373_4-layer_1-width_3 -Xwire90@3 net@310 count[F] wire90-1764_4-layer_1-width_3 -.ENDS olcOdd +*** CELL: redFive:nand2n_sy{sch} +.SUBCKT nand2n_sy-X_10 ina inb out +Xnand2_sy@0 ina inb out nand2_sy-X_10 +.ENDS nand2n_sy-X_10 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-538_8-R_34_667m a b -Ccap@0 gnd net@14 1.976f -Ccap@1 gnd net@8 1.976f -Ccap@2 gnd net@11 1.976f -Rres@0 net@14 a 3.113 -Rres@1 net@11 net@14 6.226 -Rres@2 b net@8 3.113 -Rres@3 net@8 net@11 6.226 -.ENDS wire-C_0_011f-538_8-R_34_667m +.SUBCKT wire-C_0_011f-700-R_34_667m a b +Ccap@0 gnd net@14 2.567f +Ccap@1 gnd net@8 2.567f +Ccap@2 gnd net@11 2.567f +Rres@0 net@14 a 4.044 +Rres@1 net@11 net@14 8.089 +Rres@2 b net@8 4.044 +Rres@3 net@8 net@11 8.089 +.ENDS wire-C_0_011f-700-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-538_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-538_8-R_34_667m -.ENDS wire90-538_8-layer_1-width_3 +.SUBCKT wire90-700-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-700-R_34_667m +.ENDS wire90-700-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-472_8-R_34_667m a b -Ccap@0 gnd net@14 1.734f -Ccap@1 gnd net@8 1.734f -Ccap@2 gnd net@11 1.734f -Rres@0 net@14 a 2.732 -Rres@1 net@11 net@14 5.463 -Rres@2 b net@8 2.732 -Rres@3 net@8 net@11 5.463 -.ENDS wire-C_0_011f-472_8-R_34_667m +.SUBCKT wire-C_0_011f-839_6-R_34_667m a b +Ccap@0 gnd net@14 3.079f +Ccap@1 gnd net@8 3.079f +Ccap@2 gnd net@11 3.079f +Rres@0 net@14 a 4.851 +Rres@1 net@11 net@14 9.702 +Rres@2 b net@8 4.851 +Rres@3 net@8 net@11 9.702 +.ENDS wire-C_0_011f-839_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-472_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-472_8-R_34_667m -.ENDS wire90-472_8-layer_1-width_3 +.SUBCKT wire90-839_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-839_6-R_34_667m +.ENDS wire90-839_6-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-548_8-R_34_667m a b -Ccap@0 gnd net@14 2.012f -Ccap@1 gnd net@8 2.012f -Ccap@2 gnd net@11 2.012f -Rres@0 net@14 a 3.171 -Rres@1 net@11 net@14 6.342 -Rres@2 b net@8 3.171 -Rres@3 net@8 net@11 6.342 -.ENDS wire-C_0_011f-548_8-R_34_667m +.SUBCKT wire-C_0_011f-438_2-R_34_667m a b +Ccap@0 gnd net@14 1.607f +Ccap@1 gnd net@8 1.607f +Ccap@2 gnd net@11 1.607f +Rres@0 net@14 a 2.532 +Rres@1 net@11 net@14 5.064 +Rres@2 b net@8 2.532 +Rres@3 net@8 net@11 5.064 +.ENDS wire-C_0_011f-438_2-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-548_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-548_8-R_34_667m -.ENDS wire90-548_8-layer_1-width_3 +.SUBCKT wire90-438_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-438_2-R_34_667m +.ENDS wire90-438_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-457_8-R_34_667m a b -Ccap@0 gnd net@14 1.679f -Ccap@1 gnd net@8 1.679f -Ccap@2 gnd net@11 1.679f -Rres@0 net@14 a 2.645 -Rres@1 net@11 net@14 5.29 -Rres@2 b net@8 2.645 -Rres@3 net@8 net@11 5.29 -.ENDS wire-C_0_011f-457_8-R_34_667m +.SUBCKT wire-C_0_011f-257_4-R_34_667m a b +Ccap@0 gnd net@14 0.944f +Ccap@1 gnd net@8 0.944f +Ccap@2 gnd net@11 0.944f +Rres@0 net@14 a 1.487 +Rres@1 net@11 net@14 2.974 +Rres@2 b net@8 1.487 +Rres@3 net@8 net@11 2.974 +.ENDS wire-C_0_011f-257_4-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-457_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-457_8-R_34_667m -.ENDS wire90-457_8-layer_1-width_3 +.SUBCKT wire90-257_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-257_4-R_34_667m +.ENDS wire90-257_4-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1049_7-R_34_667m a b -Ccap@0 gnd net@14 3.849f -Ccap@1 gnd net@8 3.849f -Ccap@2 gnd net@11 3.849f -Rres@0 net@14 a 6.065 -Rres@1 net@11 net@14 12.13 -Rres@2 b net@8 6.065 -Rres@3 net@8 net@11 12.13 -.ENDS wire-C_0_011f-1049_7-R_34_667m +.SUBCKT wire-C_0_011f-458_8-R_34_667m a b +Ccap@0 gnd net@14 1.682f +Ccap@1 gnd net@8 1.682f +Ccap@2 gnd net@11 1.682f +Rres@0 net@14 a 2.651 +Rres@1 net@11 net@14 5.302 +Rres@2 b net@8 2.651 +Rres@3 net@8 net@11 5.302 +.ENDS wire-C_0_011f-458_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1049_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1049_7-R_34_667m -.ENDS wire90-1049_7-layer_1-width_3 +.SUBCKT wire90-458_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-458_8-R_34_667m +.ENDS wire90-458_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1049_4-R_34_667m a b -Ccap@0 gnd net@14 3.848f -Ccap@1 gnd net@8 3.848f -Ccap@2 gnd net@11 3.848f -Rres@0 net@14 a 6.063 -Rres@1 net@11 net@14 12.126 -Rres@2 b net@8 6.063 -Rres@3 net@8 net@11 12.126 -.ENDS wire-C_0_011f-1049_4-R_34_667m +.SUBCKT wire-C_0_011f-744_5-R_34_667m a b +Ccap@0 gnd net@14 2.73f +Ccap@1 gnd net@8 2.73f +Ccap@2 gnd net@11 2.73f +Rres@0 net@14 a 4.302 +Rres@1 net@11 net@14 8.603 +Rres@2 b net@8 4.302 +Rres@3 net@8 net@11 8.603 +.ENDS wire-C_0_011f-744_5-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1049_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1049_4-R_34_667m -.ENDS wire90-1049_4-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-979_8-R_34_667m a b -Ccap@0 gnd net@14 3.593f -Ccap@1 gnd net@8 3.593f -Ccap@2 gnd net@11 3.593f -Rres@0 net@14 a 5.661 -Rres@1 net@11 net@14 11.322 -Rres@2 b net@8 5.661 -Rres@3 net@8 net@11 11.322 -.ENDS wire-C_0_011f-979_8-R_34_667m +.SUBCKT wire90-744_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-744_5-R_34_667m +.ENDS wire90-744_5-layer_1-width_3 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-979_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-979_8-R_34_667m -.ENDS wire90-979_8-layer_1-width_3 +*** CELL: gaspL:anAltStart{sch} +.SUBCKT anAltStart fire[A] fire[B] mc pred s[1] s[2] succA succB +XctrAND4i@1 net@634 succA fire[B] net@912 fire[A] net@866 ctrAND4in30M +XctrAND4i@3 net@634 succB net@909 fire[A] fire[B] net@885 ctrAND4in30M +Xinv@3 net@634 s[1] inv-X_10 +Xinv@4 pred net@787 inv-X_10 +Xinv@5 net@912 s[2] inv-X_10 +Xnand2n_s@0 net@143 net@410 net@422 nand2n_sy-X_10 +XpredDri2@0 net@815 mc pred predDri20wMC +XrsLatchA@1 mc net@905 net@911 fire[B] fire[A] rsLatchA +XsucDri20@0 fire[A] succA sucDri20 +XsucDri20@1 fire[B] succB sucDri20 +Xwire90@16 net@410 net@866 wire90-700-layer_1-width_3 +Xwire90@17 net@143 net@885 wire90-839_6-layer_1-width_3 +Xwire90@19 net@912 net@905 wire90-438_2-layer_1-width_3 +Xwire90@20 net@815 net@422 wire90-257_4-layer_1-width_3 +Xwire90@27 net@909 net@911 wire90-458_8-layer_1-width_3 +Xwire90@28 net@787 net@634 wire90-744_5-layer_1-width_3 +.ENDS anAltStart *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-786_3-R_34_667m a b -Ccap@0 gnd net@14 2.883f -Ccap@1 gnd net@8 2.883f -Ccap@2 gnd net@11 2.883f -Rres@0 net@14 a 4.543 -Rres@1 net@11 net@14 9.086 -Rres@2 b net@8 4.543 -Rres@3 net@8 net@11 9.086 -.ENDS wire-C_0_011f-786_3-R_34_667m +.SUBCKT wire-C_0_011f-1300-R_34_667m a b +Ccap@0 gnd net@14 4.767f +Ccap@1 gnd net@8 4.767f +Ccap@2 gnd net@11 4.767f +Rres@0 net@14 a 7.511 +Rres@1 net@11 net@14 15.022 +Rres@2 b net@8 7.511 +Rres@3 net@8 net@11 15.022 +.ENDS wire-C_0_011f-1300-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-786_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-786_3-R_34_667m -.ENDS wire90-786_3-layer_1-width_3 +.SUBCKT wire90-1300-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1300-R_34_667m +.ENDS wire90-1300-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-717_7-R_34_667m a b -Ccap@0 gnd net@14 2.632f -Ccap@1 gnd net@8 2.632f -Ccap@2 gnd net@11 2.632f -Rres@0 net@14 a 4.147 -Rres@1 net@11 net@14 8.293 -Rres@2 b net@8 4.147 -Rres@3 net@8 net@11 8.293 -.ENDS wire-C_0_011f-717_7-R_34_667m +.SUBCKT wire-C_0_011f-1301_9-R_34_667m a b +Ccap@0 gnd net@14 4.774f +Ccap@1 gnd net@8 4.774f +Ccap@2 gnd net@11 4.774f +Rres@0 net@14 a 7.522 +Rres@1 net@11 net@14 15.044 +Rres@2 b net@8 7.522 +Rres@3 net@8 net@11 15.044 +.ENDS wire-C_0_011f-1301_9-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-717_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-717_7-R_34_667m -.ENDS wire90-717_7-layer_1-width_3 +.SUBCKT wire90-1301_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1301_9-R_34_667m +.ENDS wire90-1301_9-layer_1-width_3 + +*** CELL: stagesM:altStartDockStage{sch} +.SUBCKT altStartDockStage in[10] in[11] in[12] in[13] in[14] in[15] in[16] ++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] ++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] ++in[3] in[4] in[5] in[6] in[7] in[8] in[9] outA[10] outA[11] outA[12] outA[13] ++outA[14] outA[15] outA[16] outA[17] outA[18] outA[19] outA[1] outA[20] ++outA[21] outA[22] outA[23] outA[24] outA[25] outA[26] outA[27] outA[28] ++outA[29] outA[2] outA[30] outA[31] outA[32] outA[33] outA[34] outA[35] ++outA[36] outA[3] outA[4] outA[5] outA[6] outA[7] outA[8] outA[9] outB[10] ++outB[11] outB[12] outB[13] outB[14] outB[15] outB[16] outB[17] outB[18] ++outB[19] outB[1] outB[20] outB[21] outB[22] outB[23] outB[24] outB[25] ++outB[26] outB[27] outB[28] outB[29] outB[2] outB[30] outB[31] outB[32] ++outB[33] outB[34] outB[35] outB[36] outB[3] outB[4] outB[5] outB[6] outB[7] ++outB[8] outB[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] ++sir[9] sor[1] succA succB +XanAltSta@0 fire[A] fire[B] sir[9] pred net@48[1] net@48[0] succA succB ++anAltStart +Xins1in20@0 net@23 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] ++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] ++in[4] in[5] in[6] in[7] in[8] in[9] outA[10] outA[11] outA[12] outA[13] ++outA[14] outA[15] outA[16] outA[17] outA[18] outA[19] outA[1] outA[20] ++outA[21] outA[22] outA[23] outA[24] outA[25] outA[26] outA[27] outA[28] ++outA[29] outA[2] outA[30] outA[31] outA[32] outA[33] outA[34] outA[35] ++outA[36] outA[3] outA[4] outA[5] outA[6] outA[7] outA[8] outA[9] ins1in20Bx36 +Xins1in20@1 net@25 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] ++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] ++in[4] in[5] in[6] in[7] in[8] in[9] outB[10] outB[11] outB[12] outB[13] ++outB[14] outB[15] outB[16] outB[17] outB[18] outB[19] outB[1] outB[20] ++outB[21] outB[22] outB[23] outB[24] outB[25] outB[26] outB[27] outB[28] ++outB[29] outB[2] outB[30] outB[31] outB[32] outB[33] outB[34] outB[35] ++outB[36] outB[3] outB[4] outB[5] outB[6] outB[7] outB[8] outB[9] ins1in20Bx36 +XlatchDri@0 net@5 net@20 latchDriver60 +XlatchDri@1 net@6 net@22 latchDriver60 +XscanEx2v@1 net@48[1] net@48[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sor[1] scanEx2 +Xwire90@0 fire[A] net@5 wire90-1300-layer_1-width_3 +Xwire90@1 fire[B] net@6 wire90-1301_9-layer_1-width_3 +Xwire90@2 net@20 net@23 wire90-1300-layer_1-width_3 +Xwire90@3 net@22 net@25 wire90-1300-layer_1-width_3 +.ENDS altStartDockStage *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-487_7-R_34_667m a b -Ccap@0 gnd net@14 1.788f -Ccap@1 gnd net@8 1.788f -Ccap@2 gnd net@11 1.788f -Rres@0 net@14 a 2.818 -Rres@1 net@11 net@14 5.636 -Rres@2 b net@8 2.818 -Rres@3 net@8 net@11 5.636 -.ENDS wire-C_0_011f-487_7-R_34_667m +.SUBCKT wire-C_0_011f-249_5-R_34_667m a b +Ccap@0 gnd net@14 0.915f +Ccap@1 gnd net@8 0.915f +Ccap@2 gnd net@11 0.915f +Rres@0 net@14 a 1.442 +Rres@1 net@11 net@14 2.883 +Rres@2 b net@8 1.442 +Rres@3 net@8 net@11 2.883 +.ENDS wire-C_0_011f-249_5-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-487_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-487_7-R_34_667m -.ENDS wire90-487_7-layer_1-width_3 +.SUBCKT wire90-249_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-249_5-R_34_667m +.ENDS wire90-249_5-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-426-R_34_667m a b -Ccap@0 gnd net@14 1.562f -Ccap@1 gnd net@8 1.562f -Ccap@2 gnd net@11 1.562f -Rres@0 net@14 a 2.461 -Rres@1 net@11 net@14 4.923 -Rres@2 b net@8 2.461 -Rres@3 net@8 net@11 4.923 -.ENDS wire-C_0_011f-426-R_34_667m +.SUBCKT wire-C_0_011f-355_8-R_34_667m a b +Ccap@0 gnd net@14 1.305f +Ccap@1 gnd net@8 1.305f +Ccap@2 gnd net@11 1.305f +Rres@0 net@14 a 2.056 +Rres@1 net@11 net@14 4.111 +Rres@2 b net@8 2.056 +Rres@3 net@8 net@11 4.111 +.ENDS wire-C_0_011f-355_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-426-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-426-R_34_667m -.ENDS wire90-426-layer_1-width_3 - -*** CELL: loopCountL:olc{sch} -.SUBCKT olc bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2] -+inLO[3] inLO[4] inLO[5] inLO[6] olc[dec][1] olc[dec][2] olc[load][1] -+olc[load][2] zooLO -Xinv@6 net@270 zooLO inv-X_20 -XolcCente@1 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] do[2] do[3] do[4] -+do[5] do[6] net@271 countLogic -XolcEven@0 bitt[2] bitt[4] bitt[6] olc[dec][2] do[2] do[4] do[6] inLO[2] -+inLO[4] inLO[6] olc[load][2] olcEven -XolcOdd@1 bitt[1] bitt[3] bitt[5] olc[dec][1] do[3] do[5] inLO[1] inLO[3] -+inLO[5] olc[load][1] olcOdd -Xwire90@1 wire90@1_a do[2] wire90-374_2-layer_1-width_3 -Xwire90@2 wire90@2_a do[3] wire90-538_8-layer_1-width_3 -Xwire90@3 wire90@3_a do[4] wire90-472_8-layer_1-width_3 -Xwire90@4 wire90@4_a do[5] wire90-548_8-layer_1-width_3 -Xwire90@5 wire90@5_a do[6] wire90-457_8-layer_1-width_3 -Xwire90@7 wire90@7_a bitt[1] wire90-1049_7-layer_1-width_3 -Xwire90@8 wire90@8_a bitt[2] wire90-1049_4-layer_1-width_3 -Xwire90@9 wire90@9_a bitt[3] wire90-979_8-layer_1-width_3 -Xwire90@10 wire90@10_a bitt[4] wire90-786_3-layer_1-width_3 -Xwire90@11 wire90@11_a bitt[5] wire90-717_7-layer_1-width_3 -Xwire90@12 wire90@12_a bitt[6] wire90-487_7-layer_1-width_3 -Xwire90@29 net@270 net@271 wire90-426-layer_1-width_3 -.ENDS olc +.SUBCKT wire90-355_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-355_8-R_34_667m +.ENDS wire90-355_8-layer_1-width_3 -*** CELL: scanK:scanKx2{sch} -.SUBCKT scanKx2 clS[F] clS[T] cl[F] cl[T] din[1] din[2] mc rd[F] rd[T] sin -+sout -XscanCell@4 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin net@18 -+scanCellKh -XscanCell@5 clS[F] clS[T] cl[F] cl[T] din[2] rd[F] rd[T] net@31 sout -+scanCellKh -Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3 -.ENDS scanKx2 - -*** CELL: scanK:scanKx6{sch} -.SUBCKT scanKx6 clS[F] clS[T] cl[F] cl[T] din[1] din[2] din[3] din[4] din[5] -+din[6] mc rd[F] rd[T] sin sout -XscanCell@4 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin net@18 -+scanCellKh -XscanCell@5 clS[F] clS[T] cl[F] cl[T] din[2] rd[F] rd[T] net@31 net@20 -+scanCellKh -XscanCell@6 clS[F] clS[T] cl[F] cl[T] din[3] rd[F] rd[T] net@32 net@24 -+scanCellKh -XscanCell@7 clS[F] clS[T] cl[F] cl[T] din[4] rd[F] rd[T] net@33 net@51 -+scanCellKh -XscanCell@8 clS[F] clS[T] cl[F] cl[T] din[5] rd[F] rd[T] net@50 net@56 -+scanCellKh -XscanCell@9 clS[F] clS[T] cl[F] cl[T] din[6] rd[F] rd[T] net@55 sout -+scanCellKh -Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3 -Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3 -Xwire90@2 net@24 net@33 wire90-297_9-layer_1-width_3 -Xwire90@3 net@51 net@50 wire90-297_9-layer_1-width_3 -Xwire90@4 net@56 net@55 wire90-297_9-layer_1-width_3 -.ENDS scanKx6 - -*** CELL: scanK:scanKx9{sch} -.SUBCKT scanKx9 clS[F] clS[T] cl[F] cl[T] din[1] din[2] din[3] din[4] din[5] -+din[6] din[7] din[8] din[9] mc rd[F] rd[T] sin sout -XscanCell@4 clS[F] clS[T] cl[F] cl[T] din[1] rd[F] rd[T] sin net@18 -+scanCellKh -XscanCell@5 clS[F] clS[T] cl[F] cl[T] din[2] rd[F] rd[T] net@31 net@20 -+scanCellKh -XscanCell@6 clS[F] clS[T] cl[F] cl[T] din[3] rd[F] rd[T] net@32 net@24 -+scanCellKh -XscanCell@7 clS[F] clS[T] cl[F] cl[T] din[4] rd[F] rd[T] net@33 net@51 -+scanCellKh -XscanCell@8 clS[F] clS[T] cl[F] cl[T] din[5] rd[F] rd[T] net@50 net@56 -+scanCellKh -XscanCell@9 clS[F] clS[T] cl[F] cl[T] din[6] rd[F] rd[T] net@55 net@63 -+scanCellKh -XscanCell@10 clS[F] clS[T] cl[F] cl[T] din[7] rd[F] rd[T] net@61 net@72 -+scanCellKh -XscanCell@11 clS[F] clS[T] cl[F] cl[T] din[8] rd[F] rd[T] net@67 net@73 -+scanCellKh -XscanCell@12 clS[F] clS[T] cl[F] cl[T] din[9] rd[F] rd[T] net@70 sout -+scanCellKh -Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3 -Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3 -Xwire90@2 net@24 net@33 wire90-297_9-layer_1-width_3 -Xwire90@3 net@51 net@50 wire90-297_9-layer_1-width_3 -Xwire90@4 net@56 net@55 wire90-297_9-layer_1-width_3 -Xwire90@5 net@63 net@61 wire90-297_9-layer_1-width_3 -Xwire90@6 net@72 net@67 wire90-297_9-layer_1-width_3 -Xwire90@7 net@73 net@70 wire90-297_9-layer_1-width_3 -.ENDS scanKx9 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-99_3-R_34_667m a b -Ccap@0 gnd net@14 0.364f -Ccap@1 gnd net@8 0.364f -Ccap@2 gnd net@11 0.364f -Rres@0 net@14 a 0.574 -Rres@1 net@11 net@14 1.147 -Rres@2 b net@8 0.574 -Rres@3 net@8 net@11 1.147 -.ENDS wire-C_0_011f-99_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-99_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-99_3-R_34_667m -.ENDS wire90-99_3-layer_1-width_3 - -*** CELL: skipL:latchA20{sch} -.SUBCKT latchA20 cl[F] cl[T] in[1] mc out[1] -MNMOSf@1 out[1] net@186 gnd gnd nch W='12*(1+ABN/sqrt(12*3))' L='3' -+DELVTO='AVT0N/sqrt(12*3)' -XNMOSx@2 out[1] mc gnd NMOSx-X_10 -XPMOSx@2 out[1] net@193 vdd PMOSx-X_2 -XinvLT@0 out[1] net@186 invLT-X_2 -Xnms2@0 out[1] in[1] cl[T] nms2-X_20 -Xpms2@0 out[1] in[1] cl[F] pms2-X_20 -Xwire90@0 net@186 net@193 wire90-99_3-layer_1-width_3 -.ENDS latchA20 - -*** CELL: skipL:flagDrivers{sch} -.SUBCKT flagDrivers flag[A] flag[B] in[A] in[B] loadFlags[F] mc -Xinv@0 loadFlags[F] net@511 inv-X_20 -XlatchA20@0 loadFlags[F] loadFlags[T] in[A] mc flag[A] latchA20 -XlatchA20@1 loadFlags[F] loadFlags[T] in[B] mc flag[B] latchA20 -Xwire90@0 net@511 loadFlags[T] wire90-99_3-layer_1-width_3 -.ENDS flagDrivers - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-183-R_34_667m a b -Ccap@0 gnd net@14 0.671f -Ccap@1 gnd net@8 0.671f -Ccap@2 gnd net@11 0.671f -Rres@0 net@14 a 1.057 -Rres@1 net@11 net@14 2.115 -Rres@2 b net@8 1.057 -Rres@3 net@8 net@11 2.115 -.ENDS wire-C_0_011f-183-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-183-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-183-R_34_667m -.ENDS wire90-183-layer_1-width_3 - -*** CELL: skipL:muxInv{sch} -.SUBCKT muxInv flag in[1][F] in[1][T] out -Xinv@3 flag net@119 inv-X_5 -XtriInv@0 net@123 flag in[1][F] out triInv-X_5 -XtriInv@1 flag net@123 in[1][T] out triInv-X_5 -Xwire90@3 net@119 net@123 wire90-183-layer_1-width_3 -.ENDS muxInv - -*** CELL: redFour:nms2_sy{sch} -.SUBCKT nms2_sy-X_6 d g g2 -Xnms2@0 d g g2 nms2-X_3 -Xnms2@1 d g2 g nms2-X_3 -.ENDS nms2_sy-X_6 +*** CELL: centersJ:ctrAND2in30{sch} +.SUBCKT ctrAND2in30 inA inB out +Xinv@0 net@7 net@8 inv-X_10 +Xinv@1 net@9 out inv-X_30 +Xnor2HT_s@1 inA inB net@6 nor2HT_sy-X_4 +Xwire90@0 net@6 net@7 wire90-249_5-layer_1-width_3 +Xwire90@1 net@8 net@9 wire90-355_8-layer_1-width_3 +.ENDS ctrAND2in30 -*** CELL: redFour:nand2_sy{sch} -.SUBCKT nand2_sy-X_6 ina inb out -XPMOS@0 out inb vdd PMOSx-X_6 -XPMOS@1 out ina vdd PMOSx-X_6 -Xnms2_sy@0 out ina inb nms2_sy-X_6 -.ENDS nand2_sy-X_6 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-291_8-R_34_667m a b +Ccap@0 gnd net@14 1.07f +Ccap@1 gnd net@8 1.07f +Ccap@2 gnd net@11 1.07f +Rres@0 net@14 a 1.686 +Rres@1 net@11 net@14 3.372 +Rres@2 b net@8 1.686 +Rres@3 net@8 net@11 3.372 +.ENDS wire-C_0_011f-291_8-R_34_667m -*** CELL: redFour:nand2n_sy{sch} -.SUBCKT nand2n_sy-X_6 ina inb out -Xnand2_sy@0 ina inb out nand2_sy-X_6 -.ENDS nand2n_sy-X_6 +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-291_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-291_8-R_34_667m +.ENDS wire90-291_8-layer_1-width_3 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-239_6-R_34_667m a b -Ccap@0 gnd net@14 0.879f -Ccap@1 gnd net@8 0.879f -Ccap@2 gnd net@11 0.879f -Rres@0 net@14 a 1.384 -Rres@1 net@11 net@14 2.769 -Rres@2 b net@8 1.384 -Rres@3 net@8 net@11 2.769 -.ENDS wire-C_0_011f-239_6-R_34_667m +*** CELL: gaspM:aStage{sch} +.SUBCKT gaspM__aStage fire mc pred s[1] succ +XctrAND2i@4 net@494 succ fire ctrAND2in30 +Xinv@4 net@987 s[1] inv-X_10 +Xinv@5 pred net@987 inv-X_5 +XpredDri2@1 fire mc pred predDri20wMC +XsucDri20@1 fire succ sucDri20 +Xwire90@0 net@987 net@494 wire90-291_8-layer_1-width_3 +.ENDS gaspM__aStage -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-239_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-239_6-R_34_667m -.ENDS wire90-239_6-layer_1-width_3 +*** CELL: stagesM:plainDockStage{sch} +.SUBCKT plainDockStage in[10] in[11] in[12] in[13] in[14] in[15] in[16] ++in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] ++in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] ++in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] ++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] ++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] ++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] ++out[6] out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sir[9] sor[1] succ take[1] +XaStage@1 net@1 sir[9] pred net@41 succ gaspM__aStage +Xins1in20@0 take[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] ++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] ++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] ++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] ++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] ++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] ++out[7] out[8] out[9] ins1in20Bx36 +XlatchDri@0 fire[1] take[1] latchDriver60 +XscanEx1v@0 net@41 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx1vertA +Xwire90@1 net@1 fire[1] wire90-791_7-layer_1-width_3 +.ENDS plainDockStage + +*** CELL: stageGroupsM:dockWagNine{sch} +.SUBCKT dockWagNine in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] ++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] ++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] ++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] ++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] ++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] ++out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sir[9] sor[1] succ take[1] take[2] take[3] take[4] take[5] take[6] +XaltEndDo@0 net@16[26] net@16[25] net@16[24] net@16[23] net@16[22] net@16[21] ++net@16[20] net@16[19] net@16[18] net@16[17] net@16[35] net@16[16] net@16[15] ++net@16[14] net@16[13] net@16[12] net@16[11] net@16[10] net@16[9] net@16[8] ++net@16[7] net@16[34] net@16[6] net@16[5] net@16[4] net@16[3] net@16[2] ++net@16[1] net@16[0] net@16[33] net@16[32] net@16[31] net@16[30] net@16[29] ++net@16[28] net@16[27] net@19[26] net@19[25] net@19[24] net@19[23] net@19[22] ++net@19[21] net@19[20] net@19[19] net@19[18] net@19[17] net@19[35] net@19[16] ++net@19[15] net@19[14] net@19[13] net@19[12] net@19[11] net@19[10] net@19[9] ++net@19[8] net@19[7] net@19[34] net@19[6] net@19[5] net@19[4] net@19[3] ++net@19[2] net@19[1] net@19[0] net@19[33] net@19[32] net@19[31] net@19[30] ++net@19[29] net@19[28] net@19[27] out[10] out[11] out[12] out[13] out[14] ++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] ++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] ++out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] ++out[7] out[8] out[9] net@69 net@58 net@134[8] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sir[9] sor[1] succ altEndDockStage +XaltStart@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] ++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] ++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] ++in[5] in[6] in[7] in[8] in[9] net@21[26] net@21[25] net@21[24] net@21[23] ++net@21[22] net@21[21] net@21[20] net@21[19] net@21[18] net@21[17] net@21[35] ++net@21[16] net@21[15] net@21[14] net@21[13] net@21[12] net@21[11] net@21[10] ++net@21[9] net@21[8] net@21[7] net@21[34] net@21[6] net@21[5] net@21[4] ++net@21[3] net@21[2] net@21[1] net@21[0] net@21[33] net@21[32] net@21[31] ++net@21[30] net@21[29] net@21[28] net@21[27] net@20[26] net@20[25] net@20[24] ++net@20[23] net@20[22] net@20[21] net@20[20] net@20[19] net@20[18] net@20[17] ++net@20[35] net@20[16] net@20[15] net@20[14] net@20[13] net@20[12] net@20[11] ++net@20[10] net@20[9] net@20[8] net@20[7] net@20[34] net@20[6] net@20[5] ++net@20[4] net@20[3] net@20[2] net@20[1] net@20[0] net@20[33] net@20[32] ++net@20[31] net@20[30] net@20[29] net@20[28] net@20[27] pred sir[1] sir[2] ++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@116[8] net@97 net@100 ++altStartDockStage +XplainDoc@0 net@2[26] net@2[25] net@2[24] net@2[23] net@2[22] net@2[21] ++net@2[20] net@2[19] net@2[18] net@2[17] net@2[35] net@2[16] net@2[15] ++net@2[14] net@2[13] net@2[12] net@2[11] net@2[10] net@2[9] net@2[8] net@2[7] ++net@2[34] net@2[6] net@2[5] net@2[4] net@2[3] net@2[2] net@2[1] net@2[0] ++net@2[33] net@2[32] net@2[31] net@2[30] net@2[29] net@2[28] net@2[27] ++net@3[26] net@3[25] net@3[24] net@3[23] net@3[22] net@3[21] net@3[20] ++net@3[19] net@3[18] net@3[17] net@3[35] net@3[16] net@3[15] net@3[14] ++net@3[13] net@3[12] net@3[11] net@3[10] net@3[9] net@3[8] net@3[7] net@3[34] ++net@3[6] net@3[5] net@3[4] net@3[3] net@3[2] net@3[1] net@3[0] net@3[33] ++net@3[32] net@3[31] net@3[30] net@3[29] net@3[28] net@3[27] net@107 ++net@131[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@130[8] ++net@106 take[5] plainDockStage +XplainDoc@1 net@20[26] net@20[25] net@20[24] net@20[23] net@20[22] net@20[21] ++net@20[20] net@20[19] net@20[18] net@20[17] net@20[35] net@20[16] net@20[15] ++net@20[14] net@20[13] net@20[12] net@20[11] net@20[10] net@20[9] net@20[8] ++net@20[7] net@20[34] net@20[6] net@20[5] net@20[4] net@20[3] net@20[2] ++net@20[1] net@20[0] net@20[33] net@20[32] net@20[31] net@20[30] net@20[29] ++net@20[28] net@20[27] net@2[26] net@2[25] net@2[24] net@2[23] net@2[22] ++net@2[21] net@2[20] net@2[19] net@2[18] net@2[17] net@2[35] net@2[16] ++net@2[15] net@2[14] net@2[13] net@2[12] net@2[11] net@2[10] net@2[9] net@2[8] ++net@2[7] net@2[34] net@2[6] net@2[5] net@2[4] net@2[3] net@2[2] net@2[1] ++net@2[0] net@2[33] net@2[32] net@2[31] net@2[30] net@2[29] net@2[28] ++net@2[27] net@60 net@125[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] ++sir[9] net@131[8] net@108 take[4] plainDockStage +XplainDoc@2 net@3[26] net@3[25] net@3[24] net@3[23] net@3[22] net@3[21] ++net@3[20] net@3[19] net@3[18] net@3[17] net@3[35] net@3[16] net@3[15] ++net@3[14] net@3[13] net@3[12] net@3[11] net@3[10] net@3[9] net@3[8] net@3[7] ++net@3[34] net@3[6] net@3[5] net@3[4] net@3[3] net@3[2] net@3[1] net@3[0] ++net@3[33] net@3[32] net@3[31] net@3[30] net@3[29] net@3[28] net@3[27] ++net@19[26] net@19[25] net@19[24] net@19[23] net@19[22] net@19[21] net@19[20] ++net@19[19] net@19[18] net@19[17] net@19[35] net@19[16] net@19[15] net@19[14] ++net@19[13] net@19[12] net@19[11] net@19[10] net@19[9] net@19[8] net@19[7] ++net@19[34] net@19[6] net@19[5] net@19[4] net@19[3] net@19[2] net@19[1] ++net@19[0] net@19[33] net@19[32] net@19[31] net@19[30] net@19[29] net@19[28] ++net@19[27] net@105 net@130[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sir[9] net@134[8] net@104 take[6] plainDockStage +XplainDoc@3 net@0[26] net@0[25] net@0[24] net@0[23] net@0[22] net@0[21] ++net@0[20] net@0[19] net@0[18] net@0[17] net@0[35] net@0[16] net@0[15] ++net@0[14] net@0[13] net@0[12] net@0[11] net@0[10] net@0[9] net@0[8] net@0[7] ++net@0[34] net@0[6] net@0[5] net@0[4] net@0[3] net@0[2] net@0[1] net@0[0] ++net@0[33] net@0[32] net@0[31] net@0[30] net@0[29] net@0[28] net@0[27] ++net@1[26] net@1[25] net@1[24] net@1[23] net@1[22] net@1[21] net@1[20] ++net@1[19] net@1[18] net@1[17] net@1[35] net@1[16] net@1[15] net@1[14] ++net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] net@1[7] net@1[34] ++net@1[6] net@1[5] net@1[4] net@1[3] net@1[2] net@1[1] net@1[0] net@1[33] ++net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] net@1[27] net@109 ++net@127[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@128[8] ++net@111 take[2] plainDockStage +XplainDoc@4 net@21[26] net@21[25] net@21[24] net@21[23] net@21[22] net@21[21] ++net@21[20] net@21[19] net@21[18] net@21[17] net@21[35] net@21[16] net@21[15] ++net@21[14] net@21[13] net@21[12] net@21[11] net@21[10] net@21[9] net@21[8] ++net@21[7] net@21[34] net@21[6] net@21[5] net@21[4] net@21[3] net@21[2] ++net@21[1] net@21[0] net@21[33] net@21[32] net@21[31] net@21[30] net@21[29] ++net@21[28] net@21[27] net@0[26] net@0[25] net@0[24] net@0[23] net@0[22] ++net@0[21] net@0[20] net@0[19] net@0[18] net@0[17] net@0[35] net@0[16] ++net@0[15] net@0[14] net@0[13] net@0[12] net@0[11] net@0[10] net@0[9] net@0[8] ++net@0[7] net@0[34] net@0[6] net@0[5] net@0[4] net@0[3] net@0[2] net@0[1] ++net@0[0] net@0[33] net@0[32] net@0[31] net@0[30] net@0[29] net@0[28] ++net@0[27] net@64 net@116[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] ++sir[9] net@127[8] net@110 take[1] plainDockStage +XplainDoc@5 net@1[26] net@1[25] net@1[24] net@1[23] net@1[22] net@1[21] ++net@1[20] net@1[19] net@1[18] net@1[17] net@1[35] net@1[16] net@1[15] ++net@1[14] net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] net@1[7] ++net@1[34] net@1[6] net@1[5] net@1[4] net@1[3] net@1[2] net@1[1] net@1[0] ++net@1[33] net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] net@1[27] ++net@16[26] net@16[25] net@16[24] net@16[23] net@16[22] net@16[21] net@16[20] ++net@16[19] net@16[18] net@16[17] net@16[35] net@16[16] net@16[15] net@16[14] ++net@16[13] net@16[12] net@16[11] net@16[10] net@16[9] net@16[8] net@16[7] ++net@16[34] net@16[6] net@16[5] net@16[4] net@16[3] net@16[2] net@16[1] ++net@16[0] net@16[33] net@16[32] net@16[31] net@16[30] net@16[29] net@16[28] ++net@16[27] net@112 net@128[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sir[9] net@125[8] net@102 take[3] plainDockStage +Xwire90@0 net@97 net@64 wire90-414-layer_1-width_3 +Xwire90@1 net@100 net@60 wire90-414-layer_1-width_3 +Xwire90@2 net@110 net@109 wire90-414-layer_1-width_3 +Xwire90@3 net@106 net@105 wire90-414-layer_1-width_3 +Xwire90@4 net@111 net@112 wire90-414-layer_1-width_3 +Xwire90@5 net@104 net@58 wire90-414-layer_1-width_3 +Xwire90@6 net@108 net@107 wire90-414-layer_1-width_3 +Xwire90@7 net@102 net@69 wire90-414-layer_1-width_3 +.ENDS dockWagNine + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-161_8-R_34_667m a b +Ccap@0 gnd net@14 0.593f +Ccap@1 gnd net@8 0.593f +Ccap@2 gnd net@11 0.593f +Rres@0 net@14 a 0.935 +Rres@1 net@11 net@14 1.87 +Rres@2 b net@8 0.935 +Rres@3 net@8 net@11 1.87 +.ENDS wire-C_0_011f-161_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-161_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-161_8-R_34_667m +.ENDS wire90-161_8-layer_1-width_3 + +*** CELL: centersJ:ctrAND2in30A{sch} +.SUBCKT ctrAND2in30A inA inB out +Xinv@1 net@9 out inv-X_30 +Xinv@2 inA net@27 inv-X_5 +Xnand2LT_@0 net@32 inB net@24 nand2LT_sy-X_10 +Xwire90@0 net@27 net@32 wire90-161_8-layer_1-width_3 +Xwire90@1 net@24 net@9 wire90-372_8-layer_1-width_3 +.ENDS ctrAND2in30A + +*** CELL: gaspM:gaspLit{sch} +.SUBCKT gaspLit do[L] fire[L] mc ready s[1] +XctrAND2i@0 net@189 ready fire[L] ctrAND2in30A +Xinv@1 do[L] net@190 inv-X_5 +XinvI@0 net@189 s[1] inv-X_10 +XpredDri2@1 fire[L] mc do[L] predDri20wMC +Xwire90@1 net@190 net@189 wire90-414-layer_1-width_3 +.ENDS gaspLit *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-321_6-R_34_667m a b -Ccap@0 gnd net@14 1.179f -Ccap@1 gnd net@8 1.179f -Ccap@2 gnd net@11 1.179f -Rres@0 net@14 a 1.858 -Rres@1 net@11 net@14 3.716 -Rres@2 b net@8 1.858 -Rres@3 net@8 net@11 3.716 -.ENDS wire-C_0_011f-321_6-R_34_667m +.SUBCKT wire-C_0_011f-295_8-R_34_667m a b +Ccap@0 gnd net@14 1.085f +Ccap@1 gnd net@8 1.085f +Ccap@2 gnd net@11 1.085f +Rres@0 net@14 a 1.709 +Rres@1 net@11 net@14 3.418 +Rres@2 b net@8 1.709 +Rres@3 net@8 net@11 3.418 +.ENDS wire-C_0_011f-295_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-321_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-321_6-R_34_667m -.ENDS wire90-321_6-layer_1-width_3 +.SUBCKT wire90-295_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-295_8-R_34_667m +.ENDS wire90-295_8-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-345-R_34_667m a b -Ccap@0 gnd net@14 1.265f -Ccap@1 gnd net@8 1.265f -Ccap@2 gnd net@11 1.265f -Rres@0 net@14 a 1.993 -Rres@1 net@11 net@14 3.987 -Rres@2 b net@8 1.993 -Rres@3 net@8 net@11 3.987 -.ENDS wire-C_0_011f-345-R_34_667m +.SUBCKT wire-C_0_011f-555_8-R_34_667m a b +Ccap@0 gnd net@14 2.038f +Ccap@1 gnd net@8 2.038f +Ccap@2 gnd net@11 2.038f +Rres@0 net@14 a 3.211 +Rres@1 net@11 net@14 6.423 +Rres@2 b net@8 3.211 +Rres@3 net@8 net@11 6.423 +.ENDS wire-C_0_011f-555_8-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-345-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-345-R_34_667m -.ENDS wire90-345-layer_1-width_3 +.SUBCKT wire90-555_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-555_8-R_34_667m +.ENDS wire90-555_8-layer_1-width_3 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-883_7-R_34_667m a b -Ccap@0 gnd net@14 3.24f -Ccap@1 gnd net@8 3.24f -Ccap@2 gnd net@11 3.24f -Rres@0 net@14 a 5.106 -Rres@1 net@11 net@14 10.212 -Rres@2 b net@8 5.106 -Rres@3 net@8 net@11 10.212 -.ENDS wire-C_0_011f-883_7-R_34_667m +*** CELL: latchesK:latch2in60C{sch} +.SUBCKT latch2in60C hcl[A] hcl[B] inA[1] inB[1] outS[1] +Xhi2inLat@0 hcl[A] hcl[B] inA[1] inB[1] net@14 raw2inLatchF +XinvLT@0 net@15 net@18 invLT-X_5 +XinvLT@1 net@16 net@19 inv-X_20 +XinvLT@2 net@17 outS[1] inv-X_60 +Xwire90@0 net@14 net@15 wire90-295_8-layer_1-width_3 +Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3 +Xwire90@2 net@19 net@17 wire90-555_8-layer_1-width_3 +.ENDS latch2in60C -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-883_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-883_7-R_34_667m -.ENDS wire90-883_7-layer_1-width_3 +*** CELL: driversJ:latchAndDriver60{sch} +.SUBCKT latchAndDriver60 inA inB out +Xinv@0 net@8 out inv-X_60 +Xnand2@0 inA inB net@26 nand2-X_20 +Xwire90@0 net@26 net@8 wire90-544_2-layer_1-width_3 +.ENDS latchAndDriver60 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1192-R_34_667m a b -Ccap@0 gnd net@14 4.371f -Ccap@1 gnd net@8 4.371f -Ccap@2 gnd net@11 4.371f -Rres@0 net@14 a 6.887 -Rres@1 net@11 net@14 13.774 -Rres@2 b net@8 6.887 -Rres@3 net@8 net@11 13.774 -.ENDS wire-C_0_011f-1192-R_34_667m +.SUBCKT wire-C_0_011f-387_3-R_34_667m a b +Ccap@0 gnd net@14 1.42f +Ccap@1 gnd net@8 1.42f +Ccap@2 gnd net@11 1.42f +Rres@0 net@14 a 2.238 +Rres@1 net@11 net@14 4.475 +Rres@2 b net@8 2.238 +Rres@3 net@8 net@11 4.475 +.ENDS wire-C_0_011f-387_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1192-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1192-R_34_667m -.ENDS wire90-1192-layer_1-width_3 +.SUBCKT wire90-387_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-387_3-R_34_667m +.ENDS wire90-387_3-layer_1-width_3 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1256-R_34_667m a b -Ccap@0 gnd net@14 4.605f -Ccap@1 gnd net@8 4.605f -Ccap@2 gnd net@11 4.605f -Rres@0 net@14 a 7.257 -Rres@1 net@11 net@14 14.514 -Rres@2 b net@8 7.257 -Rres@3 net@8 net@11 14.514 -.ENDS wire-C_0_011f-1256-R_34_667m +*** CELL: driversJ:latchAndDriver30{sch} +.SUBCKT latchAndDriver30 inA inB out +Xinv@0 net@8 out inv-X_30 +Xnand2@0 inA inB net@26 nand2-X_10 +Xwire90@0 net@26 net@8 wire90-387_3-layer_1-width_3 +.ENDS latchAndDriver30 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1256-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1256-R_34_667m -.ENDS wire90-1256-layer_1-width_3 +*** CELL: loopCountM:mux10/2{sch} +.SUBCKT mux10/2 in[1] out[1] sF sT +Xnms2b@0 out[1] sT in[1] nms2-X_10 +Xpms2@0 out[1] sF in[1] pms2-X_10 +.ENDS mux10/2 + +*** CELL: loopCountM:mux10{sch} +.SUBCKT mux10 inA[1] inB[1] out[1] sA sB +Xmux10/2@0 inA[1] out[1] sB sA mux10/2 +Xmux10/2@1 inB[1] out[1] sA sB mux10/2 +.ENDS mux10 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-839_7-R_34_667m a b -Ccap@0 gnd net@14 3.079f -Ccap@1 gnd net@8 3.079f -Ccap@2 gnd net@11 3.079f -Rres@0 net@14 a 4.852 -Rres@1 net@11 net@14 9.703 -Rres@2 b net@8 4.852 -Rres@3 net@8 net@11 9.703 -.ENDS wire-C_0_011f-839_7-R_34_667m +.SUBCKT wire-C_0_011f-2740_3-R_34_667m a b +Ccap@0 gnd net@14 10.048f +Ccap@1 gnd net@8 10.048f +Ccap@2 gnd net@11 10.048f +Rres@0 net@14 a 15.833 +Rres@1 net@11 net@14 31.666 +Rres@2 b net@8 15.833 +Rres@3 net@8 net@11 31.666 +.ENDS wire-C_0_011f-2740_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-839_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-839_7-R_34_667m -.ENDS wire90-839_7-layer_1-width_3 +.SUBCKT wire90-2740_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-2740_3-R_34_667m +.ENDS wire90-2740_3-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-247_7-R_34_667m a b -Ccap@0 gnd net@14 0.908f -Ccap@1 gnd net@8 0.908f -Ccap@2 gnd net@11 0.908f -Rres@0 net@14 a 1.431 -Rres@1 net@11 net@14 2.862 -Rres@2 b net@8 1.431 -Rres@3 net@8 net@11 2.862 -.ENDS wire-C_0_011f-247_7-R_34_667m +.SUBCKT wire-C_0_011f-2463-R_34_667m a b +Ccap@0 gnd net@14 9.031f +Ccap@1 gnd net@8 9.031f +Ccap@2 gnd net@11 9.031f +Rres@0 net@14 a 14.231 +Rres@1 net@11 net@14 28.461 +Rres@2 b net@8 14.231 +Rres@3 net@8 net@11 28.461 +.ENDS wire-C_0_011f-2463-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-247_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-247_7-R_34_667m -.ENDS wire90-247_7-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-245_7-R_34_667m a b -Ccap@0 gnd net@14 0.901f -Ccap@1 gnd net@8 0.901f -Ccap@2 gnd net@11 0.901f -Rres@0 net@14 a 1.42 -Rres@1 net@11 net@14 2.839 -Rres@2 b net@8 1.42 -Rres@3 net@8 net@11 2.839 -.ENDS wire-C_0_011f-245_7-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-245_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-245_7-R_34_667m -.ENDS wire90-245_7-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-216_4-R_37_143m a b -Ccap@0 gnd net@14 0.793f -Ccap@1 gnd net@8 0.793f -Ccap@2 gnd net@11 0.793f -Rres@0 net@14 a 1.34 -Rres@1 net@11 net@14 2.679 -Rres@2 b net@8 1.34 -Rres@3 net@8 net@11 2.679 -.ENDS wire-C_0_011f-216_4-R_37_143m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-216_4-layer_1-width_2_8 a b -Xwire@0 a b wire-C_0_011f-216_4-R_37_143m -.ENDS wire90-216_4-layer_1-width_2_8 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-505_7-R_34_667m a b -Ccap@0 gnd net@14 1.854f -Ccap@1 gnd net@8 1.854f -Ccap@2 gnd net@11 1.854f -Rres@0 net@14 a 2.922 -Rres@1 net@11 net@14 5.844 -Rres@2 b net@8 2.922 -Rres@3 net@8 net@11 5.844 -.ENDS wire-C_0_011f-505_7-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-505_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-505_7-R_34_667m -.ENDS wire90-505_7-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-353_6-R_34_667m a b -Ccap@0 gnd net@14 1.297f -Ccap@1 gnd net@8 1.297f -Ccap@2 gnd net@11 1.297f -Rres@0 net@14 a 2.043 -Rres@1 net@11 net@14 4.086 -Rres@2 b net@8 2.043 -Rres@3 net@8 net@11 4.086 -.ENDS wire-C_0_011f-353_6-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-353_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-353_6-R_34_667m -.ENDS wire90-353_6-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-313_9-R_34_667m a b -Ccap@0 gnd net@14 1.151f -Ccap@1 gnd net@8 1.151f -Ccap@2 gnd net@11 1.151f -Rres@0 net@14 a 1.814 -Rres@1 net@11 net@14 3.627 -Rres@2 b net@8 1.814 -Rres@3 net@8 net@11 3.627 -.ENDS wire-C_0_011f-313_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-313_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-313_9-R_34_667m -.ENDS wire90-313_9-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-309_5-R_34_667m a b -Ccap@0 gnd net@14 1.135f -Ccap@1 gnd net@8 1.135f -Ccap@2 gnd net@11 1.135f -Rres@0 net@14 a 1.788 -Rres@1 net@11 net@14 3.576 -Rres@2 b net@8 1.788 -Rres@3 net@8 net@11 3.576 -.ENDS wire-C_0_011f-309_5-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-309_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-309_5-R_34_667m -.ENDS wire90-309_5-layer_1-width_3 - -*** CELL: skipL:array{sch} -.SUBCKT array doit flag[A] flag[B] flag[C] flag[NZ] in[1][F] in[1][T] -+in[2][F] in[2][T] in[3][F] in[3][T] in[4][F] in[4][T] in[5][F] in[5][T] -+in[6][F] in[6][T] in[7][F] in[7][T] in[8][F] in[8][T] in[9][F] in[9][T] -+loadFlags[F] m1[F] m1[T] mc -XflagDriv@1 net@1022 net@1015 net@1012 net@1009 loadFlags[F] mc flagDrivers -Xinv@3 net@57 net@344 inv-X_10 -Xinv@9 net@352 net@350 inv-X_10 -Xinv@13 net@876 doit inv-X_20 -Xinv@14 net@924 net@925 inv-X_5 -Xinv@15 net@978 net@948 inv-X_5 -Xinv@16 net@977 net@963 inv-X_5 -Xmlat1in5@2 m1[F] m1[T] net@906 net@45 mlat1in5i -Xmlat1in5@4 m1[F] m1[T] net@927 net@912 mlat1in5i -Xmlat1in5@5 m1[F] m1[T] net@938 net@937 mlat1in5i -Xmlat1in5@6 m1[F] m1[T] net@949 net@940 mlat1in5i -Xmlat1in5@7 m1[F] m1[T] net@953 net@952 mlat1in5i -Xmlat1in5@8 m1[F] m1[T] net@964 net@955 mlat1in5i -XmuxInv@24 flag[A] in[1][F] in[1][T] net@711 muxInv -XmuxInv@25 flag[B] in[2][F] in[2][T] net@722 muxInv -XmuxInv@26 flag[C] in[3][F] in[3][T] net@733 muxInv -XmuxInv@27 flag[A] in[4][F] in[4][T] net@744 muxInv -XmuxInv@28 flag[B] in[5][F] in[5][T] net@755 muxInv -XmuxInv@29 flag[C] in[6][F] in[6][T] net@766 muxInv -XmuxInv@30 flag[A] in[7][F] in[7][T] net@777 muxInv -XmuxInv@31 flag[B] in[8][F] in[8][T] net@788 muxInv -XmuxInv@32 flag[NZ] in[9][F] in[9][T] net@799 muxInv -Xnand2n_s@0 net@895 net@896 net@909 nand2n_sy-X_6 -Xnand2n_s@3 net@913 net@916 pFlag[A] nand2n_sy-X_6 -Xnand2n_s@4 net@973 net@974 net@939 nand2n_sy-X_6 -Xnand2n_s@5 net@941 net@944 pFlag[B] nand2n_sy-X_6 -Xnand2n_s@6 net@971 net@972 net@954 nand2n_sy-X_6 -Xnand2n_s@7 net@956 net@959 net@993 nand2n_sy-X_10 -Xwire90@12 net@925 net@906 wire90-239_6-layer_1-width_3 -Xwire90@13 net@45 net@913 wire90-321_6-layer_1-width_3 -Xwire90@15 net@57 pFlag[B] wire90-345-layer_1-width_3 -Xwire90@17 net@344 net@1009 wire90-883_7-layer_1-width_3 -Xwire90@19 flag[A] net@1022 wire90-1192-layer_1-width_3 -Xwire90@42 flag[B] net@1015 wire90-1256-layer_1-width_3 -Xwire90@44 net@352 pFlag[A] wire90-345-layer_1-width_3 -Xwire90@45 net@350 net@1012 wire90-839_7-layer_1-width_3 -Xwire90@47 net@711 net@896 wire90-247_7-layer_1-width_3 -Xwire90@50 net@744 net@974 wire90-247_7-layer_1-width_3 -Xwire90@66 net@777 net@972 wire90-247_7-layer_1-width_3 -Xwire90@68 net@722 net@895 wire90-245_7-layer_1-width_3 -Xwire90@69 net@755 net@973 wire90-245_7-layer_1-width_3 -Xwire90@70 net@788 net@971 wire90-245_7-layer_1-width_3 -Xwire90@71 net@733 net@924 wire90-216_4-layer_1-width_2_8 -Xwire90@72 net@766 net@978 wire90-216_4-layer_1-width_2_8 -Xwire90@73 net@799 net@977 wire90-216_4-layer_1-width_2_8 -Xwire90@74 net@993 net@876 wire90-505_7-layer_1-width_3 -Xwire90@75 net@909 net@927 wire90-353_6-layer_1-width_3 -Xwire90@76 net@912 net@916 wire90-321_6-layer_1-width_3 -Xwire90@77 net@948 net@938 wire90-239_6-layer_1-width_3 -Xwire90@78 net@937 net@941 wire90-321_6-layer_1-width_3 -Xwire90@79 net@939 net@949 wire90-353_6-layer_1-width_3 -Xwire90@80 net@940 net@944 wire90-321_6-layer_1-width_3 -Xwire90@81 net@963 net@953 wire90-239_6-layer_1-width_3 -Xwire90@82 net@952 net@956 wire90-313_9-layer_1-width_3 -Xwire90@83 net@954 net@964 wire90-353_6-layer_1-width_3 -Xwire90@84 net@955 net@959 wire90-309_5-layer_1-width_3 -.ENDS array - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-262_8-R_34_667m a b -Ccap@0 gnd net@14 0.964f -Ccap@1 gnd net@8 0.964f -Ccap@2 gnd net@11 0.964f -Rres@0 net@14 a 1.518 -Rres@1 net@11 net@14 3.037 -Rres@2 b net@8 1.518 -Rres@3 net@8 net@11 3.037 -.ENDS wire-C_0_011f-262_8-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-262_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-262_8-R_34_667m -.ENDS wire90-262_8-layer_1-width_3 - -*** CELL: skipL:proposeZero{sch} -.SUBCKT proposeZero doLO[7] flag[NZ] inLO[7] kill mc olcNZ olc[dec][F] -+olc[load][F] -Xinv@1 olc[load][F] net@39 inv-X_10 -XlatchZ10@1 kill net@14 olc[load][F] olc[load][T] inLO[7] mc olcNZ flag[NZ] -+latchZ10 -Xnor2n_sy@0 olc[dec][F] doLO[7] net@12 nor2n_sy-X_5 -Xwire90@0 olc[load][T] net@39 wire90-262_8-layer_1-width_3 -Xwire90@1 net@12 net@14 wire90-216_3-layer_1-width_3 -.ENDS proposeZero - -*** CELL: skipL:skipReg18{sch} -.SUBCKT skipReg18 c[F] c[T] in[10] in[11] in[12] in[13] in[14] in[15] in[16] -+in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] -+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] -+out[3] out[4] out[5] out[6] out[7] out[8] out[9] -Xinv@0 in[1] xx[1] inv-X_10 -Xinv@15 in[2] xx[2] inv-X_10 -Xinv@16 in[3] xx[3] inv-X_10 -Xinv@17 in[4] xx[4] inv-X_10 -Xinv@18 in[5] xx[5] inv-X_10 -Xinv@19 in[6] xx[6] inv-X_10 -Xinv@20 in[7] xx[7] inv-X_10 -Xinv@21 in[8] xx[8] inv-X_10 -Xinv@22 in[9] xx[9] inv-X_10 -Xinv@23 in[10] xx[10] inv-X_10 -Xinv@24 in[11] xx[11] inv-X_10 -Xinv@25 in[12] xx[12] inv-X_10 -Xlat[1] c[F] c[T] xx[1] out[1] mlat1in5i -Xlat[2] c[F] c[T] xx[2] out[2] mlat1in5i -Xlat[3] c[F] c[T] xx[3] out[3] mlat1in5i -Xlat[4] c[F] c[T] xx[4] out[4] mlat1in5i -Xlat[5] c[F] c[T] xx[5] out[5] mlat1in5i -Xlat[6] c[F] c[T] xx[6] out[6] mlat1in5i -Xlat[7] c[F] c[T] xx[7] out[7] mlat1in5i -Xlat[8] c[F] c[T] xx[8] out[8] mlat1in5i -Xlat[9] c[F] c[T] xx[9] out[9] mlat1in5i -Xlat[10] c[F] c[T] xx[10] out[10] mlat1in5i -Xlat[11] c[F] c[T] xx[11] out[11] mlat1in5i -Xlat[12] c[F] c[T] xx[12] out[12] mlat1in5i -Xlat[13] c[F] c[T] in[13] out[13] mlat1in5i -Xlat[14] c[F] c[T] in[14] out[14] mlat1in5i -Xlat[15] c[F] c[T] in[15] out[15] mlat1in5i -Xlat[16] c[F] c[T] in[16] out[16] mlat1in5i -Xlat[17] c[F] c[T] in[17] out[17] mlat1in5i -Xlat[18] c[F] c[T] in[18] out[18] mlat1in5i -.ENDS skipReg18 - -*** CELL: redFour:invLT{sch} -.SUBCKT invLT-X_30 in out -XNMOS@0 out in gnd NMOSx-X_60 -XPMOS@0 out in vdd PMOSx-X_30 -.ENDS invLT-X_30 +.SUBCKT wire90-2463-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-2463-R_34_667m +.ENDS wire90-2463-layer_1-width_3 -*** CELL: skipL:timeDrive20{sch} -.SUBCKT timeDrive20 inA inB out -XNMOSx@0 out inB inA NMOSx-X_20 -XPMOSx@0 out inB vdd PMOSx-X_10 -.ENDS timeDrive20 +*** CELL: loopCountM:mux10x7{sch} +.SUBCKT mux10x7 inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inB[1] inB[2] ++inB[3] inB[4] inB[5] inB[6] inB[7] outLO[1] outLO[2] outLO[3] outLO[4] ++outLO[5] outLO[6] outLO[7] sel[A] +Xinv@0 sel[A] net@170 inv-X_20 +Xinv@1 sB net@172 inv-X_20 +Xmux10@0 inA[1] inB[1] outLO[1] sA sB mux10 +Xmux10@1 inA[2] inB[2] outLO[2] sA sB mux10 +Xmux10@2 inA[3] inB[3] outLO[3] sA sB mux10 +Xmux10@3 inA[4] inB[4] outLO[4] sA sB mux10 +Xmux10@4 inA[5] inB[5] outLO[5] sA sB mux10 +Xmux10@5 inA[6] inB[6] outLO[6] sA sB mux10 +Xmux10@6 gnd inB[7] outLO[7] sA sB mux10 +Xwire90@0 net@170 sB wire90-2740_3-layer_1-width_3 +Xwire90@1 net@172 sA wire90-2463-layer_1-width_3 +.ENDS mux10x7 + +*** CELL: registersM:data2in60Cx18{sch} +.SUBCKT data2in60Cx18 dcl[A] dcl[B] inA[10] inA[11] inA[12] inA[13] inA[14] ++inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] ++inA[7] inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] ++inB[17] inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] ++inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] ++out[18] out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] +XhiL[1] dcl[A] dcl[B] inA[1] inB[1] out[1] latch2in60C +XhiL[2] dcl[A] dcl[B] inA[2] inB[2] out[2] latch2in60C +XhiL[3] dcl[A] dcl[B] inA[3] inB[3] out[3] latch2in60C +XhiL[4] dcl[A] dcl[B] inA[4] inB[4] out[4] latch2in60C +XhiL[5] dcl[A] dcl[B] inA[5] inB[5] out[5] latch2in60C +XhiL[6] dcl[A] dcl[B] inA[6] inB[6] out[6] latch2in60C +XhiL[7] dcl[A] dcl[B] inA[7] inB[7] out[7] latch2in60C +XhiL[8] dcl[A] dcl[B] inA[8] inB[8] out[8] latch2in60C +XhiL[9] dcl[A] dcl[B] inA[9] inB[9] out[9] latch2in60C +XhiL[10] dcl[A] dcl[B] inA[10] inB[10] out[10] latch2in60C +XhiL[11] dcl[A] dcl[B] inA[11] inB[11] out[11] latch2in60C +XhiL[12] dcl[A] dcl[B] inA[12] inB[12] out[12] latch2in60C +XhiL[13] dcl[A] dcl[B] inA[13] inB[13] out[13] latch2in60C +XhiL[14] dcl[A] dcl[B] inA[14] inB[14] out[14] latch2in60C +XhiL[15] dcl[A] dcl[B] inA[15] inB[15] out[15] latch2in60C +XhiL[16] dcl[A] dcl[B] inA[16] inB[16] out[16] latch2in60C +XhiL[17] dcl[A] dcl[B] inA[17] inB[17] out[17] latch2in60C +XhiL[18] dcl[A] dcl[B] inA[18] inB[18] out[18] latch2in60C +.ENDS data2in60Cx18 + +*** CELL: registersM:data2in60Cx37{sch} +.SUBCKT data2in60Cx37 inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] inA[16] ++inA[17] inA[18] inA[19] inA[1] inA[20] inA[21] inA[22] inA[23] inA[24] ++inA[25] inA[26] inA[27] inA[28] inA[29] inA[2] inA[30] inA[31] inA[32] ++inA[33] inA[34] inA[35] inA[36] inA[37] inA[3] inA[4] inA[5] inA[6] inA[7] ++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17] ++inB[18] inB[19] inB[1] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25] ++inB[26] inB[27] inB[28] inB[29] inB[2] inB[30] inB[31] inB[32] inB[33] ++inB[34] inB[35] inB[36] inB[37] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] ++inB[9] out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] ++out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] out[25] ++out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] out[33] ++out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] ++out[9] take[A] take[B] +Xdata2in6@1 take[A2] take[B2] inA[10] inA[11] inA[12] inA[13] inA[14] inA[15] ++inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inA[7] ++inA[8] inA[9] inB[10] inB[11] inB[12] inB[13] inB[14] inB[15] inB[16] inB[17] ++inB[18] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[7] inB[8] inB[9] ++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] ++out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] data2in60Cx18 +Xdata2in6@2 take[A1] take[B1] inA[29] inA[30] inA[31] inA[32] inA[33] inA[34] ++inA[35] inA[36] inA[37] inA[20] inA[21] inA[22] inA[23] inA[24] inA[25] ++inA[26] inA[27] inA[28] inB[29] inB[30] inB[31] inB[32] inB[33] inB[34] ++inB[35] inB[36] inB[37] inB[20] inB[21] inB[22] inB[23] inB[24] inB[25] ++inB[26] inB[27] inB[28] out[29] out[30] out[31] out[32] out[33] out[34] ++out[35] out[36] out[37] out[20] out[21] out[22] out[23] out[24] out[25] ++out[26] out[27] out[28] data2in60Cx18 +Xlatch2in@4 take[A] take[B] inA[19] inB[19] out[19] latch2in60C +Xwire90@0 take[A] take[A2] wire90-2550-layer_1-width_3 +Xwire90@4 take[B] take[B2] wire90-2550-layer_1-width_3 +Xwire90@5 take[B] take[B1] wire90-2550-layer_1-width_3 +Xwire90@6 take[A] take[A1] wire90-2550-layer_1-width_3 +.ENDS data2in60Cx37 -*** CELL: skipL:timeDrive40{sch} -.SUBCKT timeDrive40 inA inB out -XNMOSx@0 out inB inA NMOSx-X_40 -XPMOSx@0 out inB vdd PMOSx-X_30 -.ENDS timeDrive40 +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_9_6 d g s +MNMOSf@0 d g s gnd nch W='28.8*(1+ABN/sqrt(28.8*2))' L='2' ++DELVTO='AVT0N/sqrt(28.8*2)' +.ENDS NMOSx-X_9_6 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-287_2-R_34_667m a b -Ccap@0 gnd net@14 1.053f -Ccap@1 gnd net@8 1.053f -Ccap@2 gnd net@11 1.053f -Rres@0 net@14 a 1.659 -Rres@1 net@11 net@14 3.319 -Rres@2 b net@8 1.659 -Rres@3 net@8 net@11 3.319 -.ENDS wire-C_0_011f-287_2-R_34_667m +*** CELL: orangeTSMC090nm:PMOSx{sch} +.SUBCKT PMOSx-X_9_6 d g s +MPMOSf@0 d g s vdd pch W='57.6*(1+ABP/sqrt(57.6*2))' L='2' ++DELVTO='AVT0P/sqrt(57.6*2)' +.ENDS PMOSx-X_9_6 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-287_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-287_2-R_34_667m -.ENDS wire90-287_2-layer_1-width_3 +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_9_6 in out +XNMOS@0 out in gnd NMOSx-X_9_6 +XPMOS@0 out in vdd PMOSx-X_9_6 +.ENDS inv-X_9_6 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-284_2-R_34_667m a b -Ccap@0 gnd net@14 1.042f -Ccap@1 gnd net@8 1.042f -Ccap@2 gnd net@11 1.042f -Rres@0 net@14 a 1.642 -Rres@1 net@11 net@14 3.284 -Rres@2 b net@8 1.642 -Rres@3 net@8 net@11 3.284 -.ENDS wire-C_0_011f-284_2-R_34_667m +.SUBCKT wire-C_0_011f-277_3-R_34_667m a b +Ccap@0 gnd net@14 1.017f +Ccap@1 gnd net@8 1.017f +Ccap@2 gnd net@11 1.017f +Rres@0 net@14 a 1.602 +Rres@1 net@11 net@14 3.204 +Rres@2 b net@8 1.602 +Rres@3 net@8 net@11 3.204 +.ENDS wire-C_0_011f-277_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-284_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-284_2-R_34_667m -.ENDS wire90-284_2-layer_1-width_3 +.SUBCKT wire90-277_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-277_3-R_34_667m +.ENDS wire90-277_3-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-391_7-R_34_667m a b -Ccap@0 gnd net@14 1.436f -Ccap@1 gnd net@8 1.436f -Ccap@2 gnd net@11 1.436f -Rres@0 net@14 a 2.263 -Rres@1 net@11 net@14 4.526 -Rres@2 b net@8 2.263 -Rres@3 net@8 net@11 4.526 -.ENDS wire-C_0_011f-391_7-R_34_667m +.SUBCKT wire-C_0_011f-114_7-R_34_667m a b +Ccap@0 gnd net@14 0.421f +Ccap@1 gnd net@8 0.421f +Ccap@2 gnd net@11 0.421f +Rres@0 net@14 a 0.663 +Rres@1 net@11 net@14 1.325 +Rres@2 b net@8 0.663 +Rres@3 net@8 net@11 1.325 +.ENDS wire-C_0_011f-114_7-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-391_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-391_7-R_34_667m -.ENDS wire90-391_7-layer_1-width_3 +.SUBCKT wire90-114_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-114_7-R_34_667m +.ENDS wire90-114_7-layer_1-width_3 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1092_8-R_34_667m a b -Ccap@0 gnd net@14 4.007f -Ccap@1 gnd net@8 4.007f -Ccap@2 gnd net@11 4.007f -Rres@0 net@14 a 6.314 -Rres@1 net@11 net@14 12.628 -Rres@2 b net@8 6.314 -Rres@3 net@8 net@11 12.628 -.ENDS wire-C_0_011f-1092_8-R_34_667m +*** CELL: latchesK:latch1in09.6Bi{sch} +.SUBCKT latch1in09_6Bi hcl in[1] out[1] +Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF +Xinv@0 net@23 out[1] inv-X_9_6 +XinvLT@0 net@18 net@25 inv-X_4 +Xwire90@0 net@19 net@18 wire90-277_3-layer_1-width_3 +Xwire90@1 net@25 net@23 wire90-114_7-layer_1-width_3 +.ENDS latch1in09_6Bi -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1092_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1092_8-R_34_667m -.ENDS wire90-1092_8-layer_1-width_3 +*** CELL: redFive:triInv{sch} +.SUBCKT triInv-X_5 en enB in out +Xnms2@0 out in en nms2-X_5 +Xpms2@0 out in enB pms2-X_5 +.ENDS triInv-X_5 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-296_2-R_34_667m a b -Ccap@0 gnd net@14 1.086f -Ccap@1 gnd net@8 1.086f -Ccap@2 gnd net@11 1.086f -Rres@0 net@14 a 1.711 -Rres@1 net@11 net@14 3.423 -Rres@2 b net@8 1.711 -Rres@3 net@8 net@11 3.423 -.ENDS wire-C_0_011f-296_2-R_34_667m +*** CELL: gates2inM:mux5{sch} +.SUBCKT mux5 inA[1] inB[1] out[1] s[F] s[T] +XtriInv@0 s[T] s[F] inA[1] out[1] triInv-X_5 +XtriInv@1 s[F] s[T] inB[1] out[1] triInv-X_5 +.ENDS mux5 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-296_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-296_2-R_34_667m -.ENDS wire90-296_2-layer_1-width_3 +*** CELL: latchGroupsK:dataMux{sch} +.SUBCKT dataMux hcl inB[1] in[1] out[1] s[F] s[T] +Xlatch1in@1 hcl in[1] net@5 latch1in09_6Bi +Xmux5@0 net@6 inB[1] out[1] s[F] s[T] mux5 +Xwire90@0 net@5 net@6 wire90-277_3-layer_1-width_3 +.ENDS dataMux *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-463_3-R_34_667m a b -Ccap@0 gnd net@14 1.699f -Ccap@1 gnd net@8 1.699f -Ccap@2 gnd net@11 1.699f -Rres@0 net@14 a 2.677 -Rres@1 net@11 net@14 5.354 -Rres@2 b net@8 2.677 -Rres@3 net@8 net@11 5.354 -.ENDS wire-C_0_011f-463_3-R_34_667m +.SUBCKT wire-C_0_011f-251_8-R_34_667m a b +Ccap@0 gnd net@14 0.923f +Ccap@1 gnd net@8 0.923f +Ccap@2 gnd net@11 0.923f +Rres@0 net@14 a 1.455 +Rres@1 net@11 net@14 2.91 +Rres@2 b net@8 1.455 +Rres@3 net@8 net@11 2.91 +.ENDS wire-C_0_011f-251_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-251_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-251_8-R_34_667m +.ENDS wire90-251_8-layer_1-width_3 + +*** CELL: registersM:shadowMux4{sch} +.SUBCKT shadowMux4 in[1] in[2] in[3] in[4] out[1] out[2] out[3] out[4] s[F] ++s[T] sign +Xi[1] in[1] x[1] inv-X_10 +Xi[2] in[2] x[2] inv-X_10 +Xi[3] in[3] x[3] inv-X_10 +Xi[4] in[4] x[4] inv-X_10 +Xm[1] x[1] sign out[1] s[F] s[T] mux5 +Xm[2] x[2] sign out[2] s[F] s[T] mux5 +Xm[3] x[3] sign out[3] s[F] s[T] mux5 +Xm[4] x[4] sign out[4] s[F] s[T] mux5 +Xwire90@0 x[1] wire90@0_b wire90-251_8-layer_1-width_3 +Xwire90@1 x[2] wire90@1_b wire90-251_8-layer_1-width_3 +Xwire90@2 x[3] wire90@2_b wire90-251_8-layer_1-width_3 +Xwire90@3 x[4] wire90@3_b wire90-251_8-layer_1-width_3 +.ENDS shadowMux4 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-463_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-463_3-R_34_667m -.ENDS wire90-463_3-layer_1-width_3 +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_80 d g s +MNMOSf@0 d g s gnd nch W='240*(1+ABN/sqrt(240*2))' L='2' ++DELVTO='AVT0N/sqrt(240*2)' +.ENDS NMOSx-X_80 -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-181-R_34_667m a b -Ccap@0 gnd net@14 0.664f -Ccap@1 gnd net@8 0.664f -Ccap@2 gnd net@11 0.664f -Rres@0 net@14 a 1.046 -Rres@1 net@11 net@14 2.092 -Rres@2 b net@8 1.046 -Rres@3 net@8 net@11 2.092 -.ENDS wire-C_0_011f-181-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-181-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-181-R_34_667m -.ENDS wire90-181-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-184-R_34_667m a b -Ccap@0 gnd net@14 0.675f -Ccap@1 gnd net@8 0.675f -Ccap@2 gnd net@11 0.675f -Rres@0 net@14 a 1.063 -Rres@1 net@11 net@14 2.126 -Rres@2 b net@8 1.063 -Rres@3 net@8 net@11 2.126 -.ENDS wire-C_0_011f-184-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-184-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-184-R_34_667m -.ENDS wire90-184-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-439_3-R_34_667m a b -Ccap@0 gnd net@14 1.611f -Ccap@1 gnd net@8 1.611f -Ccap@2 gnd net@11 1.611f -Rres@0 net@14 a 2.538 -Rres@1 net@11 net@14 5.076 -Rres@2 b net@8 2.538 -Rres@3 net@8 net@11 5.076 -.ENDS wire-C_0_011f-439_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-439_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-439_3-R_34_667m -.ENDS wire90-439_3-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-191-R_34_667m a b -Ccap@0 gnd net@14 0.7f -Ccap@1 gnd net@8 0.7f -Ccap@2 gnd net@11 0.7f -Rres@0 net@14 a 1.104 -Rres@1 net@11 net@14 2.207 -Rres@2 b net@8 1.104 -Rres@3 net@8 net@11 2.207 -.ENDS wire-C_0_011f-191-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-191-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-191-R_34_667m -.ENDS wire90-191-layer_1-width_3 - -*** CELL: skipL:skipTimer{sch} -.SUBCKT skipTimer do[L] do[M] doit fire[ODE] ilc[load][F] loadFlags[F] -+olc[dec][1] olc[dec][2] olc[dec][F] olc[load][1] olc[load][2] olc[load][F] -+selLO[Co] selLO[Dl] selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo] -Xinv@1 fire[ODE] net@68 inv-X_20 -Xinv@2 net@249 olc[dec][1] inv-X_10 -Xinv@4 net@252 olc[dec][2] inv-X_10 -Xinv@5 net@261 olc[load][1] inv-X_10 -Xinv@6 olc[load][F] olc[load][2] inv-X_10 -XinvLT@0 doit net@304 invLT-X_30 -Xnor2n@5 selLO[Lf] fire[ODE] net@18 nor2n-X_10 -Xnor2n@7 selLO[Co] fire[ODE] net@0 nor2n-X_10 -Xnor2n@9 selLO[Li] fire[ODE] net@165 nor2n-X_10 -Xnor2n@10 selLO[Co] fire[ODE] net@206 nor2n-X_10 -Xnor2n@12 selLO[Lo] fire[ODE] net@256 nor2n-X_10 -XsucDri20@0 selLO[Dl] net@334 do[L] sucDri20cond -XsucDri20@1 selLO[Dm] net@334 do[M] sucDri20cond -XtimeDriv@1 net@133 net@144 loadFlags[F] timeDrive20 -XtimeDriv@3 net@133 net@255 olc[load][F] timeDrive20 -XtimeDriv@4 net@133 net@164 ilc[load][F] timeDrive20 -XtimeDriv@5 net@133 net@147 net@331 timeDrive40 -XtimeDriv@8 net@133 net@207 net@248 timeDrive20 -XtimeDriv@9 net@133 net@145 olc[dec][F] timeDrive20 -XtimeDriv@10 net@133 net@207 net@247 timeDrive20 -XtimeDriv@11 net@133 net@255 net@263 timeDrive20 -Xwire90@0 net@18 net@144 wire90-287_2-layer_1-width_3 -Xwire90@1 net@0 net@145 wire90-284_2-layer_1-width_3 -Xwire90@3 net@68 net@147 wire90-391_7-layer_1-width_3 -Xwire90@4 net@304 net@133 wire90-1092_8-layer_1-width_3 -Xwire90@5 net@165 net@164 wire90-296_2-layer_1-width_3 -Xwire90@6 net@206 net@207 wire90-463_3-layer_1-width_3 -Xwire90@8 net@248 net@249 wire90-181-layer_1-width_3 -Xwire90@9 net@247 net@252 wire90-184-layer_1-width_3 -Xwire90@10 net@256 net@255 wire90-439_3-layer_1-width_3 -Xwire90@11 net@263 net@261 wire90-191-layer_1-width_3 -Xwire90@12 net@331 net@334 wire90-391_7-layer_1-width_3 -.ENDS skipTimer - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-657_5-R_34_667m a b -Ccap@0 gnd net@14 2.411f -Ccap@1 gnd net@8 2.411f -Ccap@2 gnd net@11 2.411f -Rres@0 net@14 a 3.799 -Rres@1 net@11 net@14 7.598 -Rres@2 b net@8 3.799 -Rres@3 net@8 net@11 7.598 -.ENDS wire-C_0_011f-657_5-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-657_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-657_5-R_34_667m -.ENDS wire90-657_5-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-439_9-R_34_667m a b -Ccap@0 gnd net@14 1.613f -Ccap@1 gnd net@8 1.613f -Ccap@2 gnd net@11 1.613f -Rres@0 net@14 a 2.542 -Rres@1 net@11 net@14 5.083 -Rres@2 b net@8 2.542 -Rres@3 net@8 net@11 5.083 -.ENDS wire-C_0_011f-439_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-439_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-439_9-R_34_667m -.ENDS wire90-439_9-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1282_5-R_34_667m a b -Ccap@0 gnd net@14 4.703f -Ccap@1 gnd net@8 4.703f -Ccap@2 gnd net@11 4.703f -Rres@0 net@14 a 7.41 -Rres@1 net@11 net@14 14.82 -Rres@2 b net@8 7.41 -Rres@3 net@8 net@11 14.82 -.ENDS wire-C_0_011f-1282_5-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1282_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1282_5-R_34_667m -.ENDS wire90-1282_5-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-3646_5-R_34_667m a b -Ccap@0 gnd net@14 13.371f -Ccap@1 gnd net@8 13.371f -Ccap@2 gnd net@11 13.371f -Rres@0 net@14 a 21.069 -Rres@1 net@11 net@14 42.137 -Rres@2 b net@8 21.069 -Rres@3 net@8 net@11 42.137 -.ENDS wire-C_0_011f-3646_5-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-3646_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-3646_5-R_34_667m -.ENDS wire90-3646_5-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-2967_8-R_34_667m a b -Ccap@0 gnd net@14 10.882f -Ccap@1 gnd net@8 10.882f -Ccap@2 gnd net@11 10.882f -Rres@0 net@14 a 17.147 -Rres@1 net@11 net@14 34.295 -Rres@2 b net@8 17.147 -Rres@3 net@8 net@11 34.295 -.ENDS wire-C_0_011f-2967_8-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-2967_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-2967_8-R_34_667m -.ENDS wire90-2967_8-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1704_4-R_34_667m a b -Ccap@0 gnd net@14 6.249f -Ccap@1 gnd net@8 6.249f -Ccap@2 gnd net@11 6.249f -Rres@0 net@14 a 9.848 -Rres@1 net@11 net@14 19.695 -Rres@2 b net@8 9.848 -Rres@3 net@8 net@11 19.695 -.ENDS wire-C_0_011f-1704_4-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1704_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1704_4-R_34_667m -.ENDS wire90-1704_4-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-649-R_34_667m a b -Ccap@0 gnd net@14 2.38f -Ccap@1 gnd net@8 2.38f -Ccap@2 gnd net@11 2.38f -Rres@0 net@14 a 3.75 -Rres@1 net@11 net@14 7.5 -Rres@2 b net@8 3.75 -Rres@3 net@8 net@11 7.5 -.ENDS wire-C_0_011f-649-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-649-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-649-R_34_667m -.ENDS wire90-649-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-306-R_34_667m a b -Ccap@0 gnd net@14 1.122f -Ccap@1 gnd net@8 1.122f -Ccap@2 gnd net@11 1.122f -Rres@0 net@14 a 1.768 -Rres@1 net@11 net@14 3.536 -Rres@2 b net@8 1.768 -Rres@3 net@8 net@11 3.536 -.ENDS wire-C_0_011f-306-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-306-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-306-R_34_667m -.ENDS wire90-306-layer_1-width_3 - -*** CELL: skipL:skipAll{sch} -.SUBCKT skipAll do[L] do[M] fire[ODE] fire[m1] fire[m2] flagOut[A] flagOut[B] -+flag[C] ilc[load][F] inLO[7] in[10] in[11] in[12] in[13] in[14] in[15] in[16] -+in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] kill mc -+olcZ olc[dec][1] olc[dec][2] olc[load][1] olc[load][2] selLO[Co] selLO[Dl] -+selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo] zooLO -Xarray@0 net@331 flagOut[A] flagOut[B] flag[C] flag[NZ] in[1][F] in[1][T] -+in[2][F] in[2][T] in[3][F] in[3][T] in[4][F] in[4][T] in[5][F] in[5][T] -+in[6][F] in[6][T] in[7][F] in[7][T] in[8][F] in[8][T] in[9][F] in[9][T] -+loadFlags[F] m1[F] m1[T] mc array -Xinv@0 m1[F] net@179 inv-X_20 -Xinv@1 fire[m2] net@302 inv-X_80 -Xinv@2 m2[F] net@304 inv-X_40 -Xinv@3 fire[m1] net@308 inv-X_30 -Xinv@4 net@352 olcZ inv-X_20 -XproposeZ@1 zooLO net@177 inLO[7] kill mc net@110 olc[dec][F] olc[load][F] -+proposeZero -XskipReg1@0 m2[F] m2[T] in[10] in[11] in[12] in[13] in[14] in[15] in[16] -+in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[5][F] -+in[6][T] in[6][F] in[7][T] in[7][F] in[8][T] in[8][F] in[9][T] in[9][F] -+in[1][T] in[1][F] in[2][T] in[2][F] in[3][T] in[3][F] in[4][T] in[4][F] -+in[5][T] skipReg18 -XskipTime@4 do[L] do[M] doIt fire[ODE] ilc[load][F] net@335 olc[dec][1] -+olc[dec][2] olc[dec][F] olc[load][1] olc[load][2] olc[load][F] selLO[Co] -+selLO[Dl] selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo] skipTimer -Xwire90@3 net@177 flag[NZ] wire90-657_5-layer_1-width_3 -Xwire90@5 net@331 doIt wire90-439_9-layer_1-width_3 -Xwire90@13 m1[T] net@179 wire90-1282_5-layer_1-width_3 -Xwire90@14 m2[F] net@302 wire90-3646_5-layer_1-width_3 -Xwire90@15 m2[T] net@304 wire90-2967_8-layer_1-width_3 -Xwire90@16 m1[F] net@308 wire90-1704_4-layer_1-width_3 -Xwire90@17 olc[load][F] wire90@17_b wire90-649-layer_1-width_3 -Xwire90@18 olc[dec][F] wire90@18_b wire90-306-layer_1-width_3 -Xwire90@19 loadFlags[F] net@335 wire90-439_9-layer_1-width_3 -Xwire90@20 net@352 net@110 wire90-657_5-layer_1-width_3 -.ENDS skipAll - -*** CELL: dockPartOD:skipCount{sch} -.SUBCKT skipCount clS[F] clS[T] cl[F] cl[T] do[L] do[M] fire[ODE] fire[m1] -+fire[m2] flag[C] ilc[cnt] ilc[dLO] ilc[i] ilc[zLO] ilc[zoo] inA[1] inA[2] -+inA[3] inA[4] inA[5] inA[6] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[8] -+in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[1] in[2] -+in[3] in[4] in[5] in[6] in[7] in[8] in[9] kill mc olcZ rd[F] rd[T] selLO[Co] -+selLO[Dl] selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo] sel[A] sin sout -XilcZoo@0 net@18[8] net@18[7] net@18[6] net@18[5] net@18[4] net@18[3] -+ilc[cnt] ilc[dLO] ilc[i] net@26 ilc[zLO] ilc[zoo] inLO[1] inLO[2] inLO[3] -+inLO[4] inLO[5] inLO[6] inLO[7] inLO[8] kill mc ilcZoo -XinMux@0 inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inB[1] inB[2] inB[3] -+inB[4] inB[5] inB[6] inB[8] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] -+inLO[7] inLO[8] sel[A] inMux -Xolc@0 net@19[5] net@19[4] net@19[3] net@19[2] net@19[1] net@19[0] inLO[1] -+inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] net@24[1] net@24[0] net@24[3] -+net@24[2] net@30 olc -XscanKx2@0 clS[F] clS[T] cl[F] cl[T] net@51[1] net@51[0] mc rd[F] rd[T] sin -+net@36 scanKx2 -XscanKx6@0 clS[F] clS[T] cl[F] cl[T] net@19[5] net@19[4] net@19[3] net@19[2] -+net@19[1] net@19[0] mc rd[F] rd[T] net@36 net@13 scanKx6 -XscanKx9@0 clS[F] clS[T] cl[F] cl[T] net@18[8] net@18[7] net@18[6] net@18[5] -+net@18[4] net@18[3] ilc[zLO] ilc[i] ilc[dLO] mc rd[F] rd[T] net@13 sout -+scanKx9 -XskipAll@0 do[L] do[M] fire[ODE] fire[m1] fire[m2] net@51[1] net@51[0] -+flag[C] net@26 inLO[7] in[10] in[11] in[12] in[13] in[14] in[15] in[16] -+in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] kill mc -+olcZ net@24[1] net@24[0] net@24[3] net@24[2] selLO[Co] selLO[Dl] selLO[Dm] -+selLO[Lf] selLO[Li] selLO[Lo] net@30 skipAll -.ENDS skipCount - -*** CELL: dockPartOD:skipCountMoveLit{sch} -.SUBCKT skipCountMoveLit clS[F] clS[T] cl[F] cl[T] do[L] do[M] fire[L] -+fire[M] fire[ODE] fire[m1] fire[m2] flag[C] inA[1] inA[2] inA[3] inA[4] -+inA[5] inA[6] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[8] in[10] in[11] -+in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[1] in[2] in[3] in[4] -+in[5] in[6] in[7] in[8] in[9] m1[15] m1[16] m1[18] m1[19] m1[20] mc olcZ -+pred[D] pred[T] rd[F] rd[T] selLO[Co] selLO[Dl] selLO[Dm] selLO[Lf] selLO[Li] -+selLO[Lo] sel[A] sin sout succ[D] succ[T] torp -XmoveLit@0 clS[F] clS[T] cl[F] cl[T] do[L] do[M] fire[L] fire[M] net@22 net@4 -+net@2[0] net@2[3] net@2[1] net@2[2] m1[15] m1[16] m1[18] m1[19] m1[20] mc -+pred[D] pred[T] rd[F] rd[T] net@12 sout succ[D] succ[T] torp moveLit -XskipCoun@0 clS[F] clS[T] cl[F] cl[T] do[L] do[M] fire[ODE] fire[m1] fire[m2] -+flag[C] net@4 net@2[0] net@2[3] net@2[1] net@2[2] inA[1] inA[2] inA[3] inA[4] -+inA[5] inA[6] inB[1] inB[2] inB[3] inB[4] inB[5] inB[6] inB[8] in[10] in[11] -+in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[1] in[2] in[3] in[4] -+in[5] in[6] in[7] in[8] in[9] net@22 mc olcZ rd[F] rd[T] selLO[Co] selLO[Dl] -+selLO[Dm] selLO[Lf] selLO[Li] selLO[Lo] sel[A] sin net@12 skipCount -.ENDS skipCountMoveLit - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-2752_3-R_26m a b -Ccap@0 gnd net@14 10.092f -Ccap@1 gnd net@8 10.092f -Ccap@2 gnd net@11 10.092f -Rres@0 net@14 a 11.927 -Rres@1 net@11 net@14 23.853 -Rres@2 b net@8 11.927 -Rres@3 net@8 net@11 23.853 -.ENDS wire-C_0_011f-2752_3-R_26m +*** CELL: orangeTSMC090nm:PMOSx{sch} +.SUBCKT PMOSx-X_80 d g s +MPMOSf@0 d g s vdd pch W='480*(1+ABP/sqrt(480*2))' L='2' ++DELVTO='AVT0P/sqrt(480*2)' +.ENDS PMOSx-X_80 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-2752_3-layer_1-width_4 a b -Xwire@0 a b wire-C_0_011f-2752_3-R_26m -.ENDS wire90-2752_3-layer_1-width_4 +*** CELL: redFive:inv{sch} +.SUBCKT inv-X_80 in out +XNMOS@0 out in gnd NMOSx-X_80 +XPMOS@0 out in vdd PMOSx-X_80 +.ENDS inv-X_80 -*** CELL: dockPartOD:ringSkipMoveLit{sch} -.SUBCKT ringSkipMoveLit do[epi] fire[L] fire[M] flag[C] freqOut inA[1] inA[2] -+inA[3] inA[4] inA[5] inA[6] inE[10] inE[11] inE[12] inE[13] inE[14] inE[15] -+inE[16] inE[17] inE[18] inE[19] inE[1] inE[20] inE[21] inE[22] inE[23] -+inE[24] inE[25] inE[26] inE[27] inE[28] inE[29] inE[2] inE[30] inE[31] -+inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] inE[4] inE[5] inE[6] inE[7] -+inE[8] inE[9] inE[T] od[10] od[11] od[12] od[13] od[14] od[15] od[16] od[17] -+od[18] od[19] od[1] od[20] od[21] od[22] od[23] od[24] od[25] od[26] od[27] -+od[28] od[29] od[2] od[30] od[31] od[32] od[33] od[34] od[35] od[36] od[3] -+od[4] od[5] od[6] od[7] od[8] od[9] pred[D] pred[T] si[1] si[2] si[3] si[4] -+si[5] si[6] si[7] si[8] si[9] so[1] so[2] so[3] so[5] so[9] succ[D] succ[T] -XscanFrom@0 clS[F] clS[T] cl[F] cl[T] si[9] rd[F] rd[T] net@546[8] net@546[7] -+net@546[6] si[4] net@546[4] si[6] si[7] si[8] net@546[0] net@536 so[1] so[2] -+so[3] so[5] so[9] scanFromDock -XscanToDo@0 clS[F] clS[T] cl[F] cl[T] si[9] rd[F] rd[T] net@534[8] si[2] -+si[3] si[4] si[5] si[6] si[7] si[8] si[9] net@546[8] net@546[7] net@546[6] -+net@546[4] net@546[0] net@535 scanToDock -XshortRin@6 do[L] do[M] fire[ODE] fire[m1] fire[m2] freqOut inE[10] inE[11] -+inE[12] inE[13] inE[14] inE[15] inE[16] inE[17] inE[18] inE[19] inE[1] -+inE[20] inE[21] inE[22] inE[23] inE[24] inE[25] inE[26] inE[27] inE[28] -+inE[29] inE[2] inE[30] inE[31] inE[32] inE[33] inE[34] inE[35] inE[36] inE[3] -+inE[4] inE[5] inE[6] inE[7] inE[8] inE[9] inE[T] m1[10] m1[11] m1[12] m1[13] -+m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] -+m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] -+m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] si[9] od[10] -+od[11] od[12] od[13] od[14] od[15] od[16] od[17] od[18] od[19] od[1] od[20] -+od[21] od[22] od[23] od[24] od[25] od[26] od[27] od[28] od[29] od[2] od[30] -+od[31] od[32] od[33] od[34] od[35] od[36] od[3] od[4] od[5] od[6] od[7] od[8] -+od[9] olcZ pout[10] pout[11] pout[12] pout[13] pout[14] pout[15] pout[16] -+pout[17] pout[18] pout[1] pout[2] pout[3] pout[4] pout[5] pout[6] pout[7] -+pout[8] pout[9] do[epi] si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] -+net@534[8] torp shortRing -XskipCoun@1 clS[F] clS[T] cl[F] cl[T] do[L] do[M] fire[L] fire[M] fire[ODE] -+fire[m1] fire[m2] flag[C] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] m1[1] -+m1[2] m1[3] m1[4] m1[5] m1[6] m1[8] pout[10] pout[11] pout[12] pout[13] -+pout[14] pout[15] pout[16] pout[17] pout[18] pout[1] pout[2] pout[3] pout[4] -+pout[5] pout[6] pout[7] pout[8] pout[9] m1[15] m1[16] m1[18] m1[19] m1[20] -+si[9] olcZ pred[D] pred[T] rd[F] rd[T] m1[24] m1[26] m1[25] m1[22] m1[27] -+m1[23] m1[20] net@535 net@536 succ[D] succ[T] torp skipCountMoveLit -Xwire90@71 do[L] wire90@71_b wire90-2752_3-layer_1-width_4 -Xwire90@72 do[M] wire90@72_b wire90-2752_3-layer_1-width_4 -.ENDS ringSkipMoveLit - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-2229_2-R_26m a b -Ccap@0 gnd net@14 8.174f -Ccap@1 gnd net@8 8.174f -Ccap@2 gnd net@11 8.174f -Rres@0 net@14 a 9.66 -Rres@1 net@11 net@14 19.32 -Rres@2 b net@8 9.66 -Rres@3 net@8 net@11 19.32 -.ENDS wire-C_0_011f-2229_2-R_26m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-2229_2-layer_1-width_4 a b -Xwire@0 a b wire-C_0_011f-2229_2-R_26m -.ENDS wire90-2229_2-layer_1-width_4 - -*** CELL: dockK:dataPath{sch} -.SUBCKT dataPath ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] -+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] aout[10] aout[11] aout[12] aout[13] -+aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] -+aout[9] freqOut inD[10] inD[11] inD[12] inD[13] inD[14] inD[15] inD[16] -+inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22] inD[23] inD[24] -+inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30] inD[31] inD[32] -+inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5] inD[6] inD[7] -+inD[8] inD[9] inD[T] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] -+in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] -+in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] -+in[4] in[5] in[6] in[7] in[8] in[9] in[T] outS[10] outS[11] outS[12] outS[13] -+outS[14] outS[15] outS[16] outS[17] outS[18] outS[19] outS[1] outS[20] -+outS[21] outS[22] outS[23] outS[24] outS[25] outS[26] outS[27] outS[28] -+outS[29] outS[2] outS[30] outS[31] outS[32] outS[33] outS[34] outS[35] -+outS[36] outS[37] outS[3] outS[4] outS[5] outS[6] outS[7] outS[8] outS[9] -+outS[T] pred pred[D] pred[T] si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] -+si[9] sigS so[1] so[2] so[3] so[5] so[9] succ[D] succ[T] -XdataAddr@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] -+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] aout[10] aout[11] aout[12] aout[13] -+aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] -+aout[9] firex[L] firex[M] net@1186 inD[10] inD[11] inD[12] inD[13] inD[14] -+inD[15] inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22] -+inD[23] inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30] -+inD[31] inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5] -+inD[6] inD[7] inD[8] inD[9] od[15] od[19] od[20] od[10] od[11] od[12] od[13] -+od[14] od[15] od[16] od[17] od[18] od[1] od[2] od[3] od[4] od[5] od[6] od[7] -+od[8] od[9] outS[10] outS[11] outS[12] outS[13] outS[14] outS[15] outS[16] -+outS[17] outS[18] outS[19] outS[1] outS[20] outS[21] outS[22] outS[23] -+outS[24] outS[25] outS[26] outS[27] outS[28] outS[29] outS[2] outS[30] -+outS[31] outS[32] outS[33] outS[34] outS[35] outS[36] outS[37] outS[3] -+outS[4] outS[5] outS[6] outS[7] outS[8] outS[9] outS[T] ain[1] sigS -+dataAddrRegAll -XringSkip@1 pred fire[L] fire[M] net@1189 freqOut outS[1] outS[2] outS[3] -+outS[4] outS[5] outS[6] in[10] in[11] in[12] in[13] in[14] in[15] in[16] -+in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] -+in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] -+in[3] in[4] in[5] in[6] in[7] in[8] in[9] in[T] od[10] od[11] od[12] od[13] -+od[14] od[15] od[16] od[17] od[18] od[19] od[1] od[20] od[21] od[22] od[23] -+od[24] od[25] od[26] od[27] od[28] od[29] od[2] od[30] od[31] od[32] od[33] -+od[34] od[35] od[36] od[3] od[4] od[5] od[6] od[7] od[8] od[9] pred[D] -+pred[T] si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] so[1] so[2] -+so[3] so[5] so[9] succ[D] succ[T] ringSkipMoveLit -Xwire90@1 fire[L] firex[L] wire90-2229_2-layer_1-width_4 -Xwire90@2 fire[M] firex[M] wire90-2229_2-layer_1-width_4 -Xwire90@5 net@1189 net@1186 wire90-2229_2-layer_1-width_4 -.ENDS dataPath +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-817_9-R_34_667m a b +Ccap@0 gnd net@14 2.999f +Ccap@1 gnd net@8 2.999f +Ccap@2 gnd net@11 2.999f +Rres@0 net@14 a 4.726 +Rres@1 net@11 net@14 9.451 +Rres@2 b net@8 4.726 +Rres@3 net@8 net@11 9.451 +.ENDS wire-C_0_011f-817_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-817_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-817_9-R_34_667m +.ENDS wire90-817_9-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-1334_3-R_34_667m a b +Ccap@0 gnd net@14 4.892f +Ccap@1 gnd net@8 4.892f +Ccap@2 gnd net@11 4.892f +Rres@0 net@14 a 7.709 +Rres@1 net@11 net@14 15.419 +Rres@2 b net@8 7.709 +Rres@3 net@8 net@11 15.419 +.ENDS wire-C_0_011f-1334_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-1334_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-1334_3-R_34_667m +.ENDS wire90-1334_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-540-R_34_667m a b +Ccap@0 gnd net@14 1.98f +Ccap@1 gnd net@8 1.98f +Ccap@2 gnd net@11 1.98f +Rres@0 net@14 a 3.12 +Rres@1 net@11 net@14 6.24 +Rres@2 b net@8 3.12 +Rres@3 net@8 net@11 6.24 +.ENDS wire-C_0_011f-540-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-540-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-540-R_34_667m +.ENDS wire90-540-layer_1-width_3 + +*** CELL: registersM:signLogic{sch} +.SUBCKT signLogic inB[15] inB[20] s[F] s[T] sign +Xinv@0 net@12 sign inv-X_80 +Xinv@2 inB[20] net@19 inv-X_30 +Xinv@3 net@7 s[T] inv-X_100 +Xinv@4 s[T] s[F] inv-X_80 +Xinv@5 net@14 net@13 inv-X_30 +Xnand2_sy@0 net@7 inB[15] net@21 nand2_sy-X_20 +Xwire90@2 net@13 net@12 wire90-817_9-layer_1-width_3 +Xwire90@4 net@19 net@7 wire90-1334_3-layer_1-width_3 +Xwire90@5 net@21 net@14 wire90-540-layer_1-width_3 +.ENDS signLogic + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-4861_7-R_34_667m a b +Ccap@0 gnd net@14 17.826f +Ccap@1 gnd net@8 17.826f +Ccap@2 gnd net@11 17.826f +Rres@0 net@14 a 28.09 +Rres@1 net@11 net@14 56.18 +Rres@2 b net@8 28.09 +Rres@3 net@8 net@11 56.18 +.ENDS wire-C_0_011f-4861_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-4861_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-4861_7-R_34_667m +.ENDS wire90-4861_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-5555_8-R_34_667m a b +Ccap@0 gnd net@14 20.371f +Ccap@1 gnd net@8 20.371f +Ccap@2 gnd net@11 20.371f +Rres@0 net@14 a 32.1 +Rres@1 net@11 net@14 64.2 +Rres@2 b net@8 32.1 +Rres@3 net@8 net@11 64.2 +.ENDS wire-C_0_011f-5555_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-5555_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-5555_8-R_34_667m +.ENDS wire90-5555_8-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-5262_9-R_34_667m a b +Ccap@0 gnd net@14 19.297f +Ccap@1 gnd net@8 19.297f +Ccap@2 gnd net@11 19.297f +Rres@0 net@14 a 30.408 +Rres@1 net@11 net@14 60.816 +Rres@2 b net@8 30.408 +Rres@3 net@8 net@11 60.816 +.ENDS wire-C_0_011f-5262_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-5262_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-5262_9-R_34_667m +.ENDS wire90-5262_9-layer_1-width_3 + +*** CELL: registersM:shadow{sch} +.SUBCKT shadow hcl inB[15] inB[16] inB[17] inB[18] inB[19] inB[20] inn[10] ++inn[11] inn[12] inn[13] inn[14] inn[15] inn[16] inn[17] inn[18] inn[1] inn[2] ++inn[3] inn[4] inn[5] inn[6] inn[7] inn[8] inn[9] outt[16] outt[17] outt[18] ++outt[19] outt[20] outt[21] outt[22] outt[23] outt[24] outt[25] outt[26] ++outt[27] outt[28] outt[29] outt[30] outt[31] outt[32] outt[33] outt[34] ++outt[35] outt[36] outt[37] +Xdl[1] hcl sign inn[1] outt[20] s[F] s[T] dataMux +Xdl[2] hcl sign inn[2] outt[21] s[F] s[T] dataMux +Xdl[3] hcl sign inn[3] outt[22] s[F] s[T] dataMux +Xdl[4] hcl sign inn[4] outt[23] s[F] s[T] dataMux +Xdl[5] hcl sign inn[5] outt[24] s[F] s[T] dataMux +Xdl[6] hcl sign inn[6] outt[25] s[F] s[T] dataMux +Xdl[7] hcl sign inn[7] outt[26] s[F] s[T] dataMux +Xdl[8] hcl sign inn[8] outt[27] s[F] s[T] dataMux +Xdl[9] hcl sign inn[9] outt[28] s[F] s[T] dataMux +Xdr[1] hcl sign inn[18] outt[37] s[F] s[T] dataMux +Xdr[2] hcl sign inn[17] outt[36] s[F] s[T] dataMux +Xdr[3] hcl sign inn[16] outt[35] s[F] s[T] dataMux +Xdr[4] hcl sign inn[15] outt[34] s[F] s[T] dataMux +Xdr[5] hcl sign inn[14] outt[33] s[F] s[T] dataMux +Xdr[6] hcl sign inn[13] outt[32] s[F] s[T] dataMux +Xdr[7] hcl sign inn[12] outt[31] s[F] s[T] dataMux +Xdr[8] hcl sign inn[11] outt[30] s[F] s[T] dataMux +Xdr[9] hcl sign inn[10] outt[29] s[F] s[T] dataMux +XshadowMu@1 inB[16] inB[17] inB[18] inB[19] outt[16] outt[17] outt[18] ++outt[19] s[F] s[T] sign shadowMux4 +XsignLogi@0 inB[15] inB[20] s[F] s[T] sign signLogic +Xwire90@1 s[F] wire90@1_b wire90-4861_7-layer_1-width_3 +Xwire90@2 s[T] wire90@2_b wire90-5555_8-layer_1-width_3 +Xwire90@3 sign wire90@3_b wire90-5262_9-layer_1-width_3 +.ENDS shadow + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-4175_4-R_34_667m a b +Ccap@0 gnd net@14 15.31f +Ccap@1 gnd net@8 15.31f +Ccap@2 gnd net@11 15.31f +Rres@0 net@14 a 24.125 +Rres@1 net@11 net@14 48.249 +Rres@2 b net@8 24.125 +Rres@3 net@8 net@11 48.249 +.ENDS wire-C_0_011f-4175_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-4175_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-4175_4-R_34_667m +.ENDS wire90-4175_4-layer_1-width_3 + +*** CELL: registersM:newDregister{sch} +.SUBCKT newDregister dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] ++dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] ++dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] ++dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] out[10] out[11] out[12] out[13] ++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] ++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] ++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] ++out[5] out[6] out[7] out[8] out[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ++ps[8] ps[9] take[A] take[B] +Xdata2in6@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18] ++dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28] ++dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3] ++dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ++ss[16] ss[17] ss[18] ss[19] ps[1] ss[20] ss[21] ss[22] ss[23] ss[24] ss[25] ++ss[26] ss[27] ss[28] ss[29] ps[2] ss[30] ss[31] ss[32] ss[33] ss[34] ss[35] ++ss[36] ss[37] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] out[10] out[11] ++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] ++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] ++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] ++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] take[A] take[B] ++data2in60Cx37 +Xinv@0 take[B] net@66 inv-X_40 +Xshadow@0 net@66 ps[15] ps[16] ps[17] ps[18] ps[19] ps[20] out[10] out[11] ++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3] ++out[4] out[5] out[6] out[7] out[8] out[9] ss[16] ss[17] ss[18] ss[19] ss[20] ++ss[21] ss[22] ss[23] ss[24] ss[25] ss[26] ss[27] ss[28] ss[29] ss[30] ss[31] ++ss[32] ss[33] ss[34] ss[35] ss[36] ss[37] shadow +Xwire90@0 net@66 wire90@0_b wire90-4175_4-layer_1-width_3 +.ENDS newDregister + +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_16 d g s +MNMOSf@0 d g s gnd nch W='48*(1+ABN/sqrt(48*2))' L='2' ++DELVTO='AVT0N/sqrt(48*2)' +.ENDS NMOSx-X_16 + +*** CELL: redFive:nms2{sch} +.SUBCKT nms2-X_8 d g g2 +XNMOS@0 d g2 net@0 NMOSx-X_16 +XNMOS@1 net@0 g gnd NMOSx-X_16 +.ENDS nms2-X_8 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-627_9-R_34_667m a b +Ccap@0 gnd net@14 2.302f +Ccap@1 gnd net@8 2.302f +Ccap@2 gnd net@11 2.302f +Rres@0 net@14 a 3.628 +Rres@1 net@11 net@14 7.256 +Rres@2 b net@8 3.628 +Rres@3 net@8 net@11 7.256 +.ENDS wire-C_0_011f-627_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-627_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-627_9-R_34_667m +.ENDS wire90-627_9-layer_1-width_3 + +*** CELL: driversL:sucANDdri60{sch} +.SUBCKT sucANDdri60 inA inB succ +XPMOSx@0 succ net@51 vdd PMOSx-X_60 +Xinv@0 succ net@71 inv-X_5 +Xnand2@0 inA inB net@67 nand2-X_10 +Xnms2@0 succ net@51 net@72 nms2-X_8 +Xwire90@0 net@67 net@51 wire90-627_9-layer_1-width_3 +Xwire90@1 net@72 net@71 wire90-124_7-layer_1-width_3 +.ENDS sucANDdri60 + +*** CELL: stagesM:litDockStage{sch} +.SUBCKT litDockStage do[L] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] ++dp[17] dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] ++dp[27] dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] ++dp[37] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] fire[M] flag[C] ++outLO[1] outLO[2] outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] out[10] ++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] ++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] ++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] ++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] ps[10] ++ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ++ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ready ++signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] +XgaspLit@0 do[L] net@10 sir[9] ready net@27 gaspLit +Xinv@0 ps[17] net@77 inv-X_10 +Xlatch2in@0 take[A] net@81 dp[B] signalBitFromInboundSwitchFabric flag[C] ++latch2in60C +XlatchAnd@1 ps[17] fire[M] take[A] latchAndDriver60 +XlatchAnd@2 net@77 fire[M] net@81 latchAndDriver30 +XlatchDri@0 net@13 take[B] latchDriver60 +Xmux10x7@0 out[1] out[2] out[3] out[4] out[5] out[6] ps[1] ps[2] ps[3] ps[4] ++ps[5] ps[6] ps[7] outLO[1] outLO[2] outLO[3] outLO[4] outLO[5] outLO[6] ++outLO[7] ps[20] mux10x7 +XnewDregi@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18] ++dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28] ++dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3] ++dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] out[10] out[11] out[12] out[13] out[14] ++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] ++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] ++out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] ++out[6] out[7] out[8] out[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ++ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ++ps[9] take[A] take[B] newDregister +Xnor2n_sy@0 succ[T] succ[D] ready nor2n_sy-X_10 +XscanEx1v@0 net@27 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx1vertA +XsucANDdr@0 ps[16] fire[M] succ[D] sucANDdri60 +XsucANDdr@1 ps[15] fire[M] succ[T] sucANDdri60 +Xwire90@0 net@10 net@13 wire90-4175_4-layer_1-width_3 +.ENDS litDockStage + +*** CELL: registersM:addr2in60Cx7{sch} +.SUBCKT addr2in60Cx7 ainA[1] ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7] ++ainB[1] ainB[2] ainB[3] ainB[4] ainB[5] ainB[6] ainB[7] aout[1] aout[2] ++aout[3] aout[4] aout[5] aout[6] aout[7] fire[A] fire[B] +XhiL[1] fire[A] fire[B] ainA[1] ainB[1] aout[1] latch2in60C +XhiL[2] fire[A] fire[B] ainA[2] ainB[2] aout[2] latch2in60C +XhiL[3] fire[A] fire[B] ainA[3] ainB[3] aout[3] latch2in60C +XhiL[4] fire[A] fire[B] ainA[4] ainB[4] aout[4] latch2in60C +XhiL[5] fire[A] fire[B] ainA[5] ainB[5] aout[5] latch2in60C +XhiL[6] fire[A] fire[B] ainA[6] ainB[6] aout[6] latch2in60C +XhiL[7] fire[A] fire[B] ainA[7] ainB[7] aout[7] latch2in60C +.ENDS addr2in60Cx7 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-2330-R_34_667m a b +Ccap@0 gnd net@14 8.543f +Ccap@1 gnd net@8 8.543f +Ccap@2 gnd net@11 8.543f +Rres@0 net@14 a 13.462 +Rres@1 net@11 net@14 26.924 +Rres@2 b net@8 13.462 +Rres@3 net@8 net@11 26.924 +.ENDS wire-C_0_011f-2330-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-2330-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-2330-R_34_667m +.ENDS wire90-2330-layer_1-width_3 + +*** CELL: registersM:addr2in60Cx15{sch} +.SUBCKT addr2in60Cx15 ainA[10] ainA[11] ainA[12] ainA[13] ainA[14] ainA[1] ++ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7] ainA[8] ainA[9] ainA[TT] ++ainB[10] ainB[11] ainB[12] ainB[13] ainB[14] ainB[1] ainB[2] ainB[3] ainB[4] ++ainB[5] ainB[6] ainB[7] ainB[8] ainB[9] ainB[TT] aout[10] aout[11] aout[12] ++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] ++aout[8] aout[9] aout[TT] fire[A] fire[B] +Xaddr2in6@1 ainA[1] ainA[2] ainA[3] ainA[4] ainA[5] ainA[6] ainA[7] ainB[1] ++ainB[2] ainB[3] ainB[4] ainB[5] ainB[6] ainB[7] aout[1] aout[2] aout[3] ++aout[4] aout[5] aout[6] aout[7] fire[A2] fire[B2] addr2in60Cx7 +Xaddr2in6@2 ainA[8] ainA[9] ainA[10] ainA[11] ainA[12] ainA[13] ainA[14] ++ainB[8] ainB[9] ainB[10] ainB[11] ainB[12] ainB[13] ainB[14] aout[8] aout[9] ++aout[10] aout[11] aout[12] aout[13] aout[14] fire[A1] fire[B1] addr2in60Cx7 +Xlatch2in@4 fire[A2] fire[B2] ainA[TT] ainB[TT] aout[TT] latch2in60C +Xwire90@3 fire[A] fire[A1] wire90-2330-layer_1-width_3 +Xwire90@4 fire[B] fire[B1] wire90-2330-layer_1-width_3 +Xwire90@5 fire[B] fire[B2] wire90-2330-layer_1-width_3 +Xwire90@6 fire[A] fire[A2] wire90-2330-layer_1-width_3 +.ENDS addr2in60Cx15 + +*** CELL: gates3inM:nand3in6.6{sch} +.SUBCKT nand3in6_6 inA inB inC out +Xnand3@0 inA inB inC out nand3-X_6_667 +.ENDS nand3in6_6 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3616_3-R_34_667m a b +Ccap@0 gnd net@14 13.26f +Ccap@1 gnd net@8 13.26f +Ccap@2 gnd net@11 13.26f +Rres@0 net@14 a 20.894 +Rres@1 net@11 net@14 41.788 +Rres@2 b net@8 20.894 +Rres@3 net@8 net@11 41.788 +.ENDS wire-C_0_011f-3616_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3616_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3616_3-R_34_667m +.ENDS wire90-3616_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-3495_7-R_34_667m a b +Ccap@0 gnd net@14 12.818f +Ccap@1 gnd net@8 12.818f +Ccap@2 gnd net@11 12.818f +Rres@0 net@14 a 20.197 +Rres@1 net@11 net@14 40.395 +Rres@2 b net@8 20.197 +Rres@3 net@8 net@11 40.395 +.ENDS wire-C_0_011f-3495_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-3495_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-3495_7-R_34_667m +.ENDS wire90-3495_7-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-270-R_34_667m a b +Ccap@0 gnd net@14 0.99f +Ccap@1 gnd net@8 0.99f +Ccap@2 gnd net@11 0.99f +Rres@0 net@14 a 1.56 +Rres@1 net@11 net@14 3.12 +Rres@2 b net@8 1.56 +Rres@3 net@8 net@11 3.12 +.ENDS wire-C_0_011f-270-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-270-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-270-R_34_667m +.ENDS wire90-270-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-358-R_34_667m a b +Ccap@0 gnd net@14 1.313f +Ccap@1 gnd net@8 1.313f +Ccap@2 gnd net@11 1.313f +Rres@0 net@14 a 2.068 +Rres@1 net@11 net@14 4.137 +Rres@2 b net@8 2.068 +Rres@3 net@8 net@11 4.137 +.ENDS wire-C_0_011f-358-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-358-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-358-R_34_667m +.ENDS wire90-358-layer_1-width_3 + +*** CELL: registersM:newPathReg{sch} +.SUBCKT newPathReg aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] ++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] ++dp[10] dp[11] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] ++fire[M] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4] ++ps[5] ps[6] ps[7] ps[8] ps[9] +Xaddr2in6@0 dp[10] dp[11] dp[12] dp[12] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5] ++dp[6] dp[7] dp[8] dp[9] ps[15] ps[9] ps[10] ps[11] ps[12] ps[13] ps[15] ps[1] ++ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[13] aout[10] aout[11] aout[12] ++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] ++aout[8] aout[9] aout[TT] take[dp] take[ps] addr2in60Cx15 +Xinv@1 ps[13] net@46 inv-X_10 +Xinv@2 ps[14] net@47 inv-X_10 +XinvI@0 net@19 net@40 inv-X_30 +XlatchAnd@0 ps[14] fire[M] net@43 latchAndDriver30 +Xnand3in6@1 net@25 net@28 fire[M] net@19 nand3in6_6 +Xwire90@0 net@43 take[dp] wire90-3616_3-layer_1-width_3 +Xwire90@1 net@40 take[ps] wire90-3495_7-layer_1-width_3 +Xwire90@3 net@46 net@28 wire90-270-layer_1-width_3 +Xwire90@4 net@47 net@25 wire90-358-layer_1-width_3 +.ENDS newPathReg + +*** CELL: dockM:inputDock{sch} +.SUBCKT inputDock aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] ++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] ++freqOut inP[10] inP[11] inP[12] inP[13] inP[14] inP[15] inP[16] inP[17] ++inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23] inP[24] inP[25] ++inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31] inP[32] inP[33] ++inP[34] inP[35] inP[36] inP[37] inP[3] inP[4] inP[5] inP[6] inP[7] inP[8] ++inP[9] inP[B] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] ++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] ++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] ++in[5] in[6] in[7] in[8] in[9] in[T] out[10] out[11] out[12] out[13] out[14] ++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] ++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] ++out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] ++out[6] out[7] out[8] out[9] pred pred[D] pred[T] ++signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] +XbitAssig@0 bitAssignments +XcenterFi@0 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] pred epi[TORP] flag[A][clr] ++flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] in[10] ++in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] ++in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] ++in[31] in[32] in[33] in[34] in[35] in[36] in[3] in[4] in[5] in[6] in[7] in[8] ++in[9] in[T] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] ++m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] ++m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] ++m1[5] m1[6] m1[7] m1[8] m1[9] net@2 ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ++ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ++ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] net@8[26] net@8[25] ++net@8[24] net@8[23] net@8[22] net@8[21] net@8[20] net@8[19] net@8[18] ++net@8[17] net@8[35] net@8[16] net@8[15] net@8[14] net@8[13] net@8[12] ++net@8[11] net@8[10] net@8[9] net@8[8] net@8[7] net@8[34] net@8[6] net@8[5] ++net@8[4] net@8[3] net@8[2] net@8[1] net@8[0] net@8[33] net@8[32] net@8[31] ++net@8[30] net@8[29] net@8[28] net@8[27] net@13[26] net@13[25] net@13[24] ++net@13[23] net@13[22] net@13[21] net@13[20] net@13[19] net@13[18] net@13[17] ++net@13[35] net@13[16] net@13[15] net@13[14] net@13[13] net@13[12] net@13[11] ++net@13[10] net@13[9] net@13[8] net@13[7] net@13[34] net@13[6] net@13[5] ++net@13[4] net@13[3] net@13[2] net@13[1] net@13[0] net@13[33] net@13[32] ++net@13[31] net@13[30] net@13[29] net@13[28] net@13[27] net@26[8] sir[2] ++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@122[8] net@61 centerFive +XdockCent@1 ps[21] ps[18] ps[19] dockCent@1_bitt[10] dockCent@1_bitt[11] ++dockCent@1_bitt[12] dockCent@1_bitt[13] dockCent@1_bitt[14] ++dockCent@1_bitt[1] dockCent@1_bitt[2] dockCent@1_bitt[3] dockCent@1_bitt[4] ++dockCent@1_bitt[5] dockCent@1_bitt[6] dockCent@1_bitt[7] dockCent@1_bitt[8] ++dockCent@1_bitt[9] do[Co] do[Ld] fire[M] flag[A][clr] flag[A][set] ++flag[B][clr] flag[B][set] flag[C][F] flag[C][T] flag[D][clr] flag[D][set] ++inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[7] m1[10] m1[11] m1[12] ++m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] sir[9] pred[D] pred[T] ++net@107 dockCent@1_s[10] dockCent@1_s[1] dockCent@1_s[2] dockCent@1_s[3] ++dockCent@1_s[4] dockCent@1_s[5] dockCent@1_s[6] dockCent@1_s[7] ++dockCent@1_s[8] dockCent@1_s[9] epi[TORP] dockCenterTry2 +XdockWagN@0 net@13[26] net@13[25] net@13[24] net@13[23] net@13[22] net@13[21] ++net@13[20] net@13[19] net@13[18] net@13[17] net@13[35] net@13[16] net@13[15] ++net@13[14] net@13[13] net@13[12] net@13[11] net@13[10] net@13[9] net@13[8] ++net@13[7] net@13[34] net@13[6] net@13[5] net@13[4] net@13[3] net@13[2] ++net@13[1] net@13[0] net@13[33] net@13[32] net@13[31] net@13[30] net@13[29] ++net@13[28] net@13[27] net@8[26] net@8[25] net@8[24] net@8[23] net@8[22] ++net@8[21] net@8[20] net@8[19] net@8[18] net@8[17] net@8[35] net@8[16] ++net@8[15] net@8[14] net@8[13] net@8[12] net@8[11] net@8[10] net@8[9] net@8[8] ++net@8[7] net@8[34] net@8[6] net@8[5] net@8[4] net@8[3] net@8[2] net@8[1] ++net@8[0] net@8[33] net@8[32] net@8[31] net@8[30] net@8[29] net@8[28] ++net@8[27] net@20 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] ++sir[9] net@26[8] net@60 take[1] take[2] take[3] freqOut take[5] take[6] ++dockWagNine +Xinv@0 flag[C][T] flag[C][F] inv-X_10 +XlitDockS@1 do[Lt] inP[10] inP[11] inP[12] inP[13] inP[14] inP[15] inP[16] ++inP[17] inP[18] inP[19] inP[1] inP[20] inP[21] inP[22] inP[23] inP[24] ++inP[25] inP[26] inP[27] inP[28] inP[29] inP[2] inP[30] inP[31] inP[32] ++inP[33] inP[34] inP[35] inP[36] inP[37] inP[3] inP[4] inP[5] inP[6] inP[7] ++inP[8] inP[9] inP[B] fire[M] flag[C][T] inLO[1] inLO[2] inLO[3] inLO[4] ++inLO[5] inLO[6] inLO[7] out[10] out[11] out[12] out[13] out[14] out[15] ++out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] ++out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] ++out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] ++out[7] out[8] out[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] ++ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ++net@107 signalBitFromInboundSwitchFabric net@122[8] sir[2] sir[3] sir[4] ++sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] litDockStage +XnewPathR@0 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] ++aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] in[10] ++in[11] in[12] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] fire[M] ++ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ++ps[7] ps[8] ps[9] newPathReg +Xwire90@0 net@60 net@2 wire90-414-layer_1-width_3 +Xwire90@1 net@61 net@20 wire90-414-layer_1-width_3 +.ENDS inputDock *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-506_4-R_34_667m a b @@ -6127,13 +6652,6 @@ Xwire90@9 net@98 net@97 wire90-506_4-layer_1-width_3 Xwire90@10 net@100 net@99 wire90-506_4-layer_1-width_3 .ENDS cntShift -*** CELL: redFour:nand2{sch} -.SUBCKT nand2-X_5 ina inb out -XPMOS@0 out ina vdd PMOSx-X_5 -XPMOS@1 out inb vdd PMOSx-X_5 -Xnms2@0 out ina inb nms2-X_5 -.ENDS nand2-X_5 - *** CELL: countersL:cntFreq{sch} .SUBCKT cntFreq count ctgLO fin fout myFin Xinv@0 ctgLO net@17 inv-X_10 @@ -6170,6 +6688,22 @@ Xwire@0 a b wire-C_0_011f-214_2-R_34_667m .ENDS wire90-214_2-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-413_4-R_34_667m a b +Ccap@0 gnd net@14 1.516f +Ccap@1 gnd net@8 1.516f +Ccap@2 gnd net@11 1.516f +Rres@0 net@14 a 2.389 +Rres@1 net@11 net@14 4.777 +Rres@2 b net@8 2.389 +Rres@3 net@8 net@11 4.777 +.ENDS wire-C_0_011f-413_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-413_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-413_4-R_34_667m +.ENDS wire90-413_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-231_2-R_34_667m a b Ccap@0 gnd net@14 0.848f Ccap@1 gnd net@8 0.848f @@ -6230,24 +6764,6 @@ Rres@3 net@8 net@11 7.864 Xwire@0 a b wire-C_0_011f-680_5-R_34_667m .ENDS wire90-680_5-layer_1-width_3 -*** CELL: countersL:cntScnThree{sch} -.SUBCKT cntScnThree cin ctgLO out p1p p2p sin -XcntScnOn@0 net@88 ctgLO out p1p p2p net@88 cntScnOne -XcntScnOn@1 cin ctgLO net@43 p1p p2p sin cntScnOne -XcntScnOn@2 net@83 ctgLO net@46 p1p p2p net@83 cntScnOne -Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3 -Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3 -.ENDS cntScnThree - -*** CELL: countersL:cntScnNine{sch} -.SUBCKT cntScnNine cin ctgLO out p1p p2p sin -XcntScnTh@0 net@60 ctgLO out p1p p2p net@60 cntScnThree -XcntScnTh@1 cin ctgLO net@43 p1p p2p sin cntScnThree -XcntScnTh@2 net@61 ctgLO net@46 p1p p2p net@61 cntScnThree -Xwire90@5 net@43 net@61 wire90-668_5-layer_1-width_3 -Xwire90@6 net@46 net@60 wire90-668_5-layer_1-width_3 -.ENDS cntScnNine - *** CELL: countersL:cntScnFour{sch} .SUBCKT cntScnFour cin ctgLO out p1p p2p sin XcntScnOn@0 net@88 ctgLO net@40 p1p p2p net@88 cntScnOne @@ -6259,6 +6775,15 @@ Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3 Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3 .ENDS cntScnFour +*** CELL: countersL:cntScnThree{sch} +.SUBCKT cntScnThree cin ctgLO out p1p p2p sin +XcntScnOn@0 net@88 ctgLO out p1p p2p net@88 cntScnOne +XcntScnOn@1 cin ctgLO net@43 p1p p2p sin cntScnOne +XcntScnOn@2 net@83 ctgLO net@46 p1p p2p net@83 cntScnOne +Xwire90@5 net@43 net@83 wire90-668_5-layer_1-width_3 +Xwire90@6 net@46 net@88 wire90-680_5-layer_1-width_3 +.ENDS cntScnThree + *** CELL: countersL:cntScnTwelve{sch} .SUBCKT cntScnTwelve cin ctgLO out p1p p2p sin XcntScnFo@0 net@60 ctgLO out p1p p2p net@60 cntScnFour @@ -6273,170 +6798,320 @@ Xwire90@6 net@46 net@60 wire90-668_5-layer_1-width_3 +sid[5] sid[6] sid[7] sid[8] sid[9] sod[1] XcntContr@0 ctgLO myp1p myp2p sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] +sid[7] sid[8] sid[9] sod[1] cntShift -XcntFreq@0 count ctgLO fin fout net@54 cntFreq -XcntScnNi@2 net@42 ctgLO sod[1] myp1p myp2p net@42 cntScnNine -XcntScnOn@2 cin ctgLO net@1 myp1p myp2p sid[1] cntScnOne -XcntScnTw@3 net@2 ctgLO net@3 myp1p myp2p net@2 cntScnTwelve -XcntScnTw@4 net@54 ctgLO net@78 myp1p myp2p net@54 cntScnTwelve +XcntFreq@0 count ctgLO fin fout net@77 cntFreq +XcntScnFo@1 cin ctgLO net@1 myp1p myp2p sid[1] cntScnFour +XcntScnTh@0 net@77 ctgLO net@78 myp1p myp2p net@77 cntScnThree +XcntScnTw@3 net@2 ctgLO net@124 myp1p myp2p net@2 cntScnTwelve +XcntScnTw@5 net@136 ctgLO net@144 myp1p myp2p net@136 cntScnTwelve Xwire90@0 net@1 net@2 wire90-506_4-layer_1-width_3 -Xwire90@1 net@3 net@54 wire90-506_4-layer_1-width_3 -Xwire90@2 net@78 net@42 wire90-506_4-layer_1-width_3 +Xwire90@1 net@124 net@77 wire90-506_4-layer_1-width_3 +Xwire90@2 net@78 net@136 wire90-506_4-layer_1-width_3 +Xwire90@3 net@144 sod[1] wire90-506_4-layer_1-width_3 .ENDS instructionCount -*** CELL: orangeTSMC090nm:NMOSx{sch} -.SUBCKT NMOSx-X_70 d g s -MNMOSf@0 d g s gnd nch W='210*(1+ABN/sqrt(210*2))' L='2' -+DELVTO='AVT0N/sqrt(210*2)' -.ENDS NMOSx-X_70 +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-546_2-R_34_667m a b +Ccap@0 gnd net@14 2.003f +Ccap@1 gnd net@8 2.003f +Ccap@2 gnd net@11 2.003f +Rres@0 net@14 a 3.156 +Rres@1 net@11 net@14 6.312 +Rres@2 b net@8 3.156 +Rres@3 net@8 net@11 6.312 +.ENDS wire-C_0_011f-546_2-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-546_2-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-546_2-R_34_667m +.ENDS wire90-546_2-layer_1-width_3 + +*** CELL: latchesK:latch1in60C{sch} +.SUBCKT latch1in60C hcl inS[1] outS[1] +Xhi2inLat@0 hcl inS[1] net@14 raw1inLatchF +XinvLT@0 net@15 net@18 invLT-X_5 +XinvLT@1 net@16 net@19 inv-X_20 +XinvLT@2 net@17 outS[1] inv-X_60 +Xwire90@0 net@14 net@15 wire90-294_8-layer_1-width_3 +Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3 +Xwire90@2 net@19 net@17 wire90-546_2-layer_1-width_3 +.ENDS latch1in60C + +*** CELL: registersM:addr1in60Cx7{sch} +.SUBCKT addr1in60Cx7 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] ++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire +Xlat[1] fire ain[1] aout[1] latch1in60C +Xlat[2] fire ain[2] aout[2] latch1in60C +Xlat[3] fire ain[3] aout[3] latch1in60C +Xlat[4] fire ain[4] aout[4] latch1in60C +Xlat[5] fire ain[5] aout[5] latch1in60C +Xlat[6] fire ain[6] aout[6] latch1in60C +Xlat[7] fire ain[7] aout[7] latch1in60C +.ENDS addr1in60Cx7 + +*** CELL: registersM:addr1in60Cx15{sch} +.SUBCKT addr1in60Cx15 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] ++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] ++aout[7] aout[8] aout[9] aout[TT] fire +Xaddr1in6@0 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8] ++aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@17 addr1in60Cx7 +Xaddr1in6@1 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2] ++aout[3] aout[4] aout[5] aout[6] aout[7] net@19 addr1in60Cx7 +Xlatch1in@0 fire ain[TT] aout[TT] latch1in60C +Xwire90@0 net@19 fire wire90-2330-layer_1-width_3 +Xwire90@1 fire net@17 wire90-2330-layer_1-width_3 +.ENDS addr1in60Cx15 + +*** CELL: registersM:data1in60Cx18{sch} +.SUBCKT data1in60Cx18 dcl in[10] in[11] in[12] in[13] in[14] in[15] in[16] ++in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] ++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] ++out[3] out[4] out[5] out[6] out[7] out[8] out[9] +Xlat[1] dcl in[1] out[1] latch1in60C +Xlat[2] dcl in[2] out[2] latch1in60C +Xlat[3] dcl in[3] out[3] latch1in60C +Xlat[4] dcl in[4] out[4] latch1in60C +Xlat[5] dcl in[5] out[5] latch1in60C +Xlat[6] dcl in[6] out[6] latch1in60C +Xlat[7] dcl in[7] out[7] latch1in60C +Xlat[8] dcl in[8] out[8] latch1in60C +Xlat[9] dcl in[9] out[9] latch1in60C +Xlat[10] dcl in[10] out[10] latch1in60C +Xlat[11] dcl in[11] out[11] latch1in60C +Xlat[12] dcl in[12] out[12] latch1in60C +Xlat[13] dcl in[13] out[13] latch1in60C +Xlat[14] dcl in[14] out[14] latch1in60C +Xlat[15] dcl in[15] out[15] latch1in60C +Xlat[16] dcl in[16] out[16] latch1in60C +Xlat[17] dcl in[17] out[17] latch1in60C +Xlat[18] dcl in[18] out[18] latch1in60C +.ENDS data1in60Cx18 + +*** CELL: registersM:data1in60Cx37{sch} +.SUBCKT data1in60Cx37 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] ++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] ++in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] ++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] ++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] ++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] ++out[5] out[6] out[7] out[8] out[9] take +Xdata1in6@1 net@19 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] ++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3] ++out[4] out[5] out[6] out[7] out[8] out[9] data1in60Cx18 +Xdata1in6@2 net@17 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36] ++in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29] ++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20] ++out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] data1in60Cx18 +Xlatch1in@0 take in[19] out[19] latch1in60C +Xwire90@2 take net@17 wire90-2550-layer_1-width_3 +Xwire90@3 net@19 take wire90-2550-layer_1-width_3 +.ENDS data1in60Cx37 *** CELL: orangeTSMC090nm:PMOSx{sch} -.SUBCKT PMOSx-X_70 d g s -MPMOSf@0 d g s vdd pch W='420*(1+ABP/sqrt(420*2))' L='2' -+DELVTO='AVT0P/sqrt(420*2)' -.ENDS PMOSx-X_70 - -*** CELL: redFour:inv{sch} -.SUBCKT inv-X_70 in out -XNMOS@0 out in gnd NMOSx-X_70 -XPMOS@0 out in vdd PMOSx-X_70 -.ENDS inv-X_70 - -*** CELL: redFour:nand2_sy{sch} -.SUBCKT nand2_sy-X_30 ina inb out -XPMOS@0 out inb vdd PMOSx-X_30 -XPMOS@1 out ina vdd PMOSx-X_30 -Xnms2_sy@0 out ina inb nms2_sy-X_30 -.ENDS nand2_sy-X_30 +.SUBCKT PMOSx-X_25 d g s +MPMOSf@0 d g s vdd pch W='150*(1+ABP/sqrt(150*2))' L='2' ++DELVTO='AVT0P/sqrt(150*2)' +.ENDS PMOSx-X_25 + +*** CELL: orangeTSMC090nm:NMOSx{sch} +.SUBCKT NMOSx-X_50 d g s +MNMOSf@0 d g s gnd nch W='150*(1+ABN/sqrt(150*2))' L='2' ++DELVTO='AVT0N/sqrt(150*2)' +.ENDS NMOSx-X_50 + +*** CELL: redFive:nms2{sch} +.SUBCKT nms2-X_25 d g g2 +XNMOS@0 d g2 net@0 NMOSx-X_50 +XNMOS@1 net@0 g gnd NMOSx-X_50 +.ENDS nms2-X_25 + +*** CELL: redFive:nand2{sch} +.SUBCKT nand2-X_25 ina inb out +XPMOS@0 out ina vdd PMOSx-X_25 +XPMOS@1 out inb vdd PMOSx-X_25 +Xnms2@0 out ina inb nms2-X_25 +.ENDS nand2-X_25 + +*** CELL: arbiterM:half2inArb{sch} +.SUBCKT half2inArb cross grant[B] inA req[B] +XNMOSx@0 vdd req[B] grant[B] PMOSx-X_10 +XPMOSx@0 cross inA grant[B] NMOSx-X_10 +Xnor2n@0 inA req[B] cross nand2-X_25 +.ENDS half2inArb + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-830_7-R_34_667m a b +Ccap@0 gnd net@14 3.046f +Ccap@1 gnd net@8 3.046f +Ccap@2 gnd net@11 3.046f +Rres@0 net@14 a 4.8 +Rres@1 net@11 net@14 9.599 +Rres@2 b net@8 4.8 +Rres@3 net@8 net@11 9.599 +.ENDS wire-C_0_011f-830_7-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-830_7-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-830_7-R_34_667m +.ENDS wire90-830_7-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-947_7-R_34_667m a b -Ccap@0 gnd net@14 3.475f -Ccap@1 gnd net@8 3.475f -Ccap@2 gnd net@11 3.475f -Rres@0 net@14 a 5.476 -Rres@1 net@11 net@14 10.951 -Rres@2 b net@8 5.476 -Rres@3 net@8 net@11 10.951 -.ENDS wire-C_0_011f-947_7-R_34_667m +.SUBCKT wire-C_0_011f-834_6-R_34_667m a b +Ccap@0 gnd net@14 3.06f +Ccap@1 gnd net@8 3.06f +Ccap@2 gnd net@11 3.06f +Rres@0 net@14 a 4.822 +Rres@1 net@11 net@14 9.644 +Rres@2 b net@8 4.822 +Rres@3 net@8 net@11 9.644 +.ENDS wire-C_0_011f-834_6-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-947_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-947_7-R_34_667m -.ENDS wire90-947_7-layer_1-width_3 +.SUBCKT wire90-834_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-834_6-R_34_667m +.ENDS wire90-834_6-layer_1-width_3 -*** CELL: driversJ:dataDriver70{sch} -.SUBCKT dataDriver70 inA inB out -Xinv@0 net@8 out inv-X_70 -Xnand2_sy@0 inA inB net@7 nand2_sy-X_30 -Xwire90@0 net@7 net@8 wire90-947_7-layer_1-width_3 -.ENDS dataDriver70 +*** CELL: arbiterM:arbiter2{sch} +.SUBCKT arbiter2 grant[A] grant[B] req[A] req[B] +XhalfArb@2 net@12 grant[A] net@5 req[A] half2inArb +XhalfArb@3 net@13 grant[B] net@8 req[B] half2inArb +Xwire90@0 net@12 net@8 wire90-830_7-layer_1-width_3 +Xwire90@1 net@5 net@13 wire90-834_6-layer_1-width_3 +.ENDS arbiter2 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-428_5-R_34_667m a b -Ccap@0 gnd net@14 1.571f -Ccap@1 gnd net@8 1.571f -Ccap@2 gnd net@11 1.571f -Rres@0 net@14 a 2.476 -Rres@1 net@11 net@14 4.952 -Rres@2 b net@8 2.476 -Rres@3 net@8 net@11 4.952 -.ENDS wire-C_0_011f-428_5-R_34_667m +.SUBCKT wire-C_0_011f-698_4-R_34_667m a b +Ccap@0 gnd net@14 2.561f +Ccap@1 gnd net@8 2.561f +Ccap@2 gnd net@11 2.561f +Rres@0 net@14 a 4.035 +Rres@1 net@11 net@14 8.07 +Rres@2 b net@8 4.035 +Rres@3 net@8 net@11 8.07 +.ENDS wire-C_0_011f-698_4-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-428_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-428_5-R_34_667m -.ENDS wire90-428_5-layer_1-width_3 +.SUBCKT wire90-698_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-698_4-R_34_667m +.ENDS wire90-698_4-layer_1-width_3 -*** CELL: latchesK:latch1in30A{sch} -.SUBCKT latch1in30A hcl in[1] out[1] -Xhi2inLat@0 hcl in[1] net@19 raw1inLatchF -XinvLT@0 net@18 out[1] inv-X_30 -Xwire90@0 net@19 net@18 wire90-428_5-layer_1-width_3 -.ENDS latch1in30A +*** CELL: driversL:dataDriver60{sch} +.SUBCKT dataDriver60 inA inB out +Xinv@0 net@8 out inv-X_60 +Xnand2@1 inA inB net@7 nand2-X_20 +Xwire90@0 net@7 net@8 wire90-698_4-layer_1-width_3 +.ENDS dataDriver60 + +*** CELL: driversJ:predDri60wMC{sch} +.SUBCKT driversJ__predDri60wMC in mc pred +XNMOSx@0 pred in gnd NMOSx-X_60 +XNMOSx@1 pred mc gnd NMOSx-X_10 +Xinv@0 pred net@145 inv-X_10 +Xpms3@0 pred mc in net@174 pms3-X_3_333 +Xwire90@0 net@174 net@145 wire90-243_6-layer_1-width_3 +.ENDS driversJ__predDri60wMC *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-5118_8-R_34_667m a b -Ccap@0 gnd net@14 18.769f -Ccap@1 gnd net@8 18.769f -Ccap@2 gnd net@11 18.769f -Rres@0 net@14 a 29.575 -Rres@1 net@11 net@14 59.151 -Rres@2 b net@8 29.575 -Rres@3 net@8 net@11 59.151 -.ENDS wire-C_0_011f-5118_8-R_34_667m +.SUBCKT wire-C_0_011f-175-R_34_667m a b +Ccap@0 gnd net@14 0.642f +Ccap@1 gnd net@8 0.642f +Ccap@2 gnd net@11 0.642f +Rres@0 net@14 a 1.011 +Rres@1 net@11 net@14 2.022 +Rres@2 b net@8 1.011 +Rres@3 net@8 net@11 2.022 +.ENDS wire-C_0_011f-175-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-5118_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-5118_8-R_34_667m -.ENDS wire90-5118_8-layer_1-width_3 +.SUBCKT wire90-175-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-175-R_34_667m +.ENDS wire90-175-layer_1-width_3 -*** CELL: registersL:all1in52weak{sch} -.SUBCKT all1in52weak ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] -+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] -+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] -+aout[7] aout[8] aout[9] aout[T] fire in[10] in[11] in[12] in[13] in[14] -+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] -+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] -+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] -+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] -+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] -+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] -+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] -XdataDriv@0 ain[T] fire net@81 dataDriver70 -XhiL[1] net@41 in[1] out[1] latch1in30A -XhiL[2] net@41 in[2] out[2] latch1in30A -XhiL[3] net@41 in[3] out[3] latch1in30A -XhiL[4] net@41 in[4] out[4] latch1in30A -XhiL[5] net@41 in[5] out[5] latch1in30A -XhiL[6] net@41 in[6] out[6] latch1in30A -XhiL[7] net@41 in[7] out[7] latch1in30A -XhiL[8] net@41 in[8] out[8] latch1in30A -XhiL[9] net@41 in[9] out[9] latch1in30A -XhiL[10] net@41 in[10] out[10] latch1in30A -XhiL[11] net@41 in[11] out[11] latch1in30A -XhiL[12] net@41 in[12] out[12] latch1in30A -XhiL[13] net@41 in[13] out[13] latch1in30A -XhiL[14] net@41 in[14] out[14] latch1in30A -XhiL[15] net@41 in[15] out[15] latch1in30A -XhiL[16] net@41 in[16] out[16] latch1in30A -XhiL[17] net@41 in[17] out[17] latch1in30A -XhiL[18] net@41 in[18] out[18] latch1in30A -XhiL[19] net@41 in[19] out[19] latch1in30A -XhiL[20] net@41 in[20] out[20] latch1in30A -XhiL[21] net@41 in[21] out[21] latch1in30A -XhiL[22] net@41 in[22] out[22] latch1in30A -XhiL[23] net@41 in[23] out[23] latch1in30A -XhiL[24] net@41 in[24] out[24] latch1in30A -XhiL[25] net@41 in[25] out[25] latch1in30A -XhiL[26] net@41 in[26] out[26] latch1in30A -XhiL[27] net@41 in[27] out[27] latch1in30A -XhiL[28] net@41 in[28] out[28] latch1in30A -XhiL[29] net@41 in[29] out[29] latch1in30A -XhiL[30] net@41 in[30] out[30] latch1in30A -XhiL[31] net@41 in[31] out[31] latch1in30A -XhiL[32] net@41 in[32] out[32] latch1in30A -XhiL[33] net@41 in[33] out[33] latch1in30A -XhiL[34] net@41 in[34] out[34] latch1in30A -XhiL[35] net@41 in[35] out[35] latch1in30A -XhiL[36] net@41 in[36] out[36] latch1in30A -XhiL[37] net@41 in[37] out[37] latch1in30A -Xlat[1] fire ain[1] aout[1] latch1in30A -Xlat[2] fire ain[2] aout[2] latch1in30A -Xlat[3] fire ain[3] aout[3] latch1in30A -Xlat[4] fire ain[4] aout[4] latch1in30A -Xlat[5] fire ain[5] aout[5] latch1in30A -Xlat[6] fire ain[6] aout[6] latch1in30A -Xlat[7] fire ain[7] aout[7] latch1in30A -Xlat[8] fire ain[8] aout[8] latch1in30A -Xlat[9] fire ain[9] aout[9] latch1in30A -Xlat[10] fire ain[10] aout[10] latch1in30A -Xlat[11] fire ain[11] aout[11] latch1in30A -Xlat[12] fire ain[12] aout[12] latch1in30A -Xlat[13] fire ain[13] aout[13] latch1in30A -Xlat[14] fire ain[14] aout[14] latch1in30A -Xlatch1in@0 fire ain[T] aout[T] latch1in30A -Xwire90@0 net@81 net@41 wire90-5118_8-layer_1-width_3 -.ENDS all1in52weak +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-516_9-R_34_667m a b +Ccap@0 gnd net@14 1.895f +Ccap@1 gnd net@8 1.895f +Ccap@2 gnd net@11 1.895f +Rres@0 net@14 a 2.987 +Rres@1 net@11 net@14 5.973 +Rres@2 b net@8 2.987 +Rres@3 net@8 net@11 5.973 +.ENDS wire-C_0_011f-516_9-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-516_9-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-516_9-R_34_667m +.ENDS wire90-516_9-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-160_4-R_34_667m a b +Ccap@0 gnd net@14 0.588f +Ccap@1 gnd net@8 0.588f +Ccap@2 gnd net@11 0.588f +Rres@0 net@14 a 0.927 +Rres@1 net@11 net@14 1.854 +Rres@2 b net@8 0.927 +Rres@3 net@8 net@11 1.854 +.ENDS wire-C_0_011f-160_4-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-160_4-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-160_4-R_34_667m +.ENDS wire90-160_4-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-130_1-R_34_667m a b +Ccap@0 gnd net@14 0.477f +Ccap@1 gnd net@8 0.477f +Ccap@2 gnd net@11 0.477f +Rres@0 net@14 a 0.752 +Rres@1 net@11 net@14 1.503 +Rres@2 b net@8 0.752 +Rres@3 net@8 net@11 1.503 +.ENDS wire-C_0_011f-130_1-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-130_1-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-130_1-R_34_667m +.ENDS wire90-130_1-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-350_6-R_34_667m a b +Ccap@0 gnd net@14 1.286f +Ccap@1 gnd net@8 1.286f +Ccap@2 gnd net@11 1.286f +Rres@0 net@14 a 2.026 +Rres@1 net@11 net@14 4.051 +Rres@2 b net@8 2.026 +Rres@3 net@8 net@11 4.051 +.ENDS wire-C_0_011f-350_6-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-350_6-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-350_6-R_34_667m +.ENDS wire90-350_6-layer_1-width_3 + +*** CELL: gaspM:gaspDrain{sch} +.SUBCKT gaspDrain clear fire go pred s[1] s[2] silent succ take tok +Xarbiter2@0 net@374 net@353 pred net@375 arbiter2 +XctrAND2i@5 net@241 succ fire ctrAND2in100LT +XdataDriv@0 tok fire take dataDriver60 +Xinv@1 go net@360 inv-X_10 +Xinv@4 pred net@472 inv-X_5 +Xinv@5 silent net@463 inv-X_10 +XinvI@0 net@357 net@409 inv-X_10 +XinvI@1 net@475 s[1] inv-X_10 +XpredDri6@0 fire clear pred driversJ__predDri60wMC +XsucANDdr@4 net@499 fire succ sucANDdri60 +Xwire90@1 net@374 net@241 wire90-175-layer_1-width_3 +Xwire90@7 net@375 net@360 wire90-516_9-layer_1-width_3 +Xwire90@10 net@357 net@353 wire90-160_4-layer_1-width_3 +Xwire90@11 s[2] net@409 wire90-130_1-layer_1-width_3 +Xwire90@15 net@472 net@475 wire90-142_6-layer_1-width_3 +Xwire90@16 net@463 net@499 wire90-350_6-layer_1-width_3 +.ENDS gaspDrain *** CELL: latchPartsK:latchPointFmcHI{sch} .SUBCKT latchPointFmcHI mc x[F] x[T] @@ -6472,306 +7147,139 @@ Xwire@0 a b wire-C_0_011f-283-R_34_667m .SUBCKT latch2in10Alomc hcl inA[1] mc out[1] Xhi2inLat@0 hcl inA[1] mc dataBar raw2inLatchFmc XinvLT@0 net@20 out[1] invLT-X_10 -Xwire90@0 dataBar net@20 wire90-283-layer_1-width_3 -.ENDS latch2in10Alomc - -*** CELL: scanJ:scanCellF{sch} -.SUBCKT scanCellF dout[1] mc p1p p2p rd sin sout wr -Xlatch1in@0 p2p sin net@2 latch1in10A -Xlatch2in@0 p1p rd net@10 dout[1] sout latch2in10Alo -Xlatch2in@1 wr sout mc dout[1] latch2in10Alomc -Xwire90@0 net@2 net@10 wire90-297_6-layer_1-width_3 -.ENDS scanCellF - -*** CELL: scanJ:scanFx1vert{sch} -.SUBCKT scanFx1vert dout[1] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] -+sic[8] sic[9] soc[1] -XscanCell@2 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] soc[1] sic[4] -+scanCellF -.ENDS scanFx1vert - -*** CELL: scanJ:scanFx3hor{sch} -.SUBCKT scanFx3hor dout[1] dout[2] dout[3] sic[1] sic[2] sic[3] sic[4] sic[5] -+sic[6] sic[7] sic[8] sic[9] soc[1] -XscanCell@1 dout[2] sic[9] sic[3] sic[2] sic[5] net@32 net@31 sic[4] -+scanCellF -XscanCell@2 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] net@30 sic[4] -+scanCellF -XscanCell@3 dout[3] sic[9] sic[3] sic[2] sic[5] net@33 soc[1] sic[4] -+scanCellF -Xwire90@0 net@30 net@32 wire90-297_6-layer_1-width_3 -Xwire90@1 net@31 net@33 wire90-297_6-layer_1-width_3 -.ENDS scanFx3hor - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-310_8-R_34_667m a b -Ccap@0 gnd net@14 1.14f -Ccap@1 gnd net@8 1.14f -Ccap@2 gnd net@11 1.14f -Rres@0 net@14 a 1.796 -Rres@1 net@11 net@14 3.591 -Rres@2 b net@8 1.796 -Rres@3 net@8 net@11 3.591 -.ENDS wire-C_0_011f-310_8-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-310_8-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-310_8-R_34_667m -.ENDS wire90-310_8-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-925_7-R_34_667m a b -Ccap@0 gnd net@14 3.394f -Ccap@1 gnd net@8 3.394f -Ccap@2 gnd net@11 3.394f -Rres@0 net@14 a 5.348 -Rres@1 net@11 net@14 10.697 -Rres@2 b net@8 5.348 -Rres@3 net@8 net@11 10.697 -.ENDS wire-C_0_011f-925_7-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-925_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-925_7-R_34_667m -.ENDS wire90-925_7-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-602_3-R_34_667m a b -Ccap@0 gnd net@14 2.208f -Ccap@1 gnd net@8 2.208f -Ccap@2 gnd net@11 2.208f -Rres@0 net@14 a 3.48 -Rres@1 net@11 net@14 6.96 -Rres@2 b net@8 3.48 -Rres@3 net@8 net@11 6.96 -.ENDS wire-C_0_011f-602_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-602_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-602_3-R_34_667m -.ENDS wire90-602_3-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-236-R_34_667m a b -Ccap@0 gnd net@14 0.865f -Ccap@1 gnd net@8 0.865f -Ccap@2 gnd net@11 0.865f -Rres@0 net@14 a 1.364 -Rres@1 net@11 net@14 2.727 -Rres@2 b net@8 1.364 -Rres@3 net@8 net@11 2.727 -.ENDS wire-C_0_011f-236-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-236-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-236-R_34_667m -.ENDS wire90-236-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-169_4-R_34_667m a b -Ccap@0 gnd net@14 0.621f -Ccap@1 gnd net@8 0.621f -Ccap@2 gnd net@11 0.621f -Rres@0 net@14 a 0.979 -Rres@1 net@11 net@14 1.958 -Rres@2 b net@8 0.979 -Rres@3 net@8 net@11 1.958 -.ENDS wire-C_0_011f-169_4-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-169_4-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-169_4-R_34_667m -.ENDS wire90-169_4-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-661_2-R_34_667m a b -Ccap@0 gnd net@14 2.424f -Ccap@1 gnd net@8 2.424f -Ccap@2 gnd net@11 2.424f -Rres@0 net@14 a 3.82 -Rres@1 net@11 net@14 7.641 -Rres@2 b net@8 3.82 -Rres@3 net@8 net@11 7.641 -.ENDS wire-C_0_011f-661_2-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-661_2-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-661_2-R_34_667m -.ENDS wire90-661_2-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-611_7-R_34_667m a b -Ccap@0 gnd net@14 2.243f -Ccap@1 gnd net@8 2.243f -Ccap@2 gnd net@11 2.243f -Rres@0 net@14 a 3.534 -Rres@1 net@11 net@14 7.069 -Rres@2 b net@8 3.534 -Rres@3 net@8 net@11 7.069 -.ENDS wire-C_0_011f-611_7-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-611_7-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-611_7-R_34_667m -.ENDS wire90-611_7-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-706_1-R_34_667m a b -Ccap@0 gnd net@14 2.589f -Ccap@1 gnd net@8 2.589f -Ccap@2 gnd net@11 2.589f -Rres@0 net@14 a 4.08 -Rres@1 net@11 net@14 8.159 -Rres@2 b net@8 4.08 -Rres@3 net@8 net@11 8.159 -.ENDS wire-C_0_011f-706_1-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-706_1-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-706_1-R_34_667m -.ENDS wire90-706_1-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-529_6-R_34_667m a b -Ccap@0 gnd net@14 1.942f -Ccap@1 gnd net@8 1.942f -Ccap@2 gnd net@11 1.942f -Rres@0 net@14 a 3.06 -Rres@1 net@11 net@14 6.12 -Rres@2 b net@8 3.06 -Rres@3 net@8 net@11 6.12 -.ENDS wire-C_0_011f-529_6-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-529_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-529_6-R_34_667m -.ENDS wire90-529_6-layer_1-width_3 - -*** CELL: gaspL:gaspDrain{sch} -.SUBCKT gaspDrain dOut fire[A] pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] -+sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] -+sir[9] soc[1] sor[1] succ -Xarbiter2@0 net@374 net@353 pred net@375 arbiter2 -XctrAND2i@2 net@241 succ fire[A] ctrAND2in100LT -Xinv@0 net@357 net@409 inv-X_10 -Xinv@1 go net@360 inv-X_10 -Xinv@3 silent net@333 inv-X_10 -XpredDri2@0 fire[A] net@364 pred predDri20wMC -XscanEx2v@1 pred stopped sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sor[1] scanEx2vert -XscanFx1v@0 dOut net@468[8] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] -+sic[9] soc[1] scanFx1vert -XscanFx3h@0 net@467 net@447 net@466 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] -+sic[7] sic[8] sic[9] net@468[8] scanFx3hor -XsucANDdr@3 net@338 fire[A] succ sucANDdri20 -Xwire90@1 net@374 net@241 wire90-310_8-layer_1-width_3 -Xwire90@7 net@375 net@360 wire90-925_7-layer_1-width_3 -Xwire90@8 net@364 clear wire90-602_3-layer_1-width_3 -Xwire90@9 net@333 net@338 wire90-236-layer_1-width_3 -Xwire90@10 net@357 net@353 wire90-169_4-layer_1-width_3 -Xwire90@11 stopped net@409 wire90-661_2-layer_1-width_3 -Xwire90@12 net@466 clear wire90-611_7-layer_1-width_3 -Xwire90@13 net@447 silent wire90-706_1-layer_1-width_3 -Xwire90@14 net@467 go wire90-529_6-layer_1-width_3 -.ENDS gaspDrain +Xwire90@0 dataBar net@20 wire90-283-layer_1-width_3 +.ENDS latch2in10Alomc -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-5192-R_34_667m a b -Ccap@0 gnd net@14 19.037f -Ccap@1 gnd net@8 19.037f -Ccap@2 gnd net@11 19.037f -Rres@0 net@14 a 29.998 -Rres@1 net@11 net@14 59.996 -Rres@2 b net@8 29.998 -Rres@3 net@8 net@11 59.996 -.ENDS wire-C_0_011f-5192-R_34_667m +*** CELL: scanM:scanCellF{sch} +.SUBCKT scanCellF dout[1] mc p1p p2p rd sin sout wr +Xlatch1in@0 p2p sin net@2 latch1in10A +Xlatch2in@0 p1p rd net@10 dout[1] sout latch2in10Alo +Xlatch2in@1 wr sout mc dout[1] latch2in10Alomc +Xwire90@0 net@2 net@10 wire90-297_6-layer_1-width_3 +.ENDS scanCellF -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-5192-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-5192-R_34_667m -.ENDS wire90-5192-layer_1-width_3 +*** CELL: scanM:scanFx3{sch} +.SUBCKT scanFx3 dout[1] dout[2] dout[3] sic[1] sic[2] sic[3] sic[4] sic[5] ++sic[6] sic[7] sic[8] sic[9] soc[1] +XscanCell@4 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] net@30 sic[4] ++scanCellF +XscanCell@5 dout[2] sic[9] sic[3] sic[2] sic[5] net@32 net@31 sic[4] ++scanCellF +XscanCell@6 dout[3] sic[9] sic[3] sic[2] sic[5] net@33 soc[1] sic[4] ++scanCellF +Xwire90@0 net@30 net@32 wire90-297_6-layer_1-width_3 +Xwire90@1 net@31 net@33 wire90-297_6-layer_1-width_3 +.ENDS scanFx3 -*** CELL: stagesL:drainStage{sch} +*** CELL: stagesM:drainStage{sch} .SUBCKT drainStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] -+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] ++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] +aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] -+aout[7] aout[8] aout[9] aout[T] dOut fire in[10] in[11] in[12] in[13] in[14] -+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] -+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] -+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] -+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] -+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] -+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] -+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] -+sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] -+sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sor[1] succ -Xall1in52@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] -+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] aout[12] -+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] -+aout[8] aout[9] aout[T] net@2 in[10] in[11] in[12] in[13] in[14] in[15] ++aout[7] aout[8] aout[9] aout[TT] in[10] in[11] in[12] in[13] in[14] in[15] +in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] +in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] +in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] +out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] +out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] +out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] -+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] all1in52weak -XgaspDrai@0 dOut fire pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] -+sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] -+soc[1] sor[1] succ gaspDrain -Xwire90@0 fire net@2 wire90-5192-layer_1-width_3 ++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] sic[2] ++sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] ++sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sor[1] succ +Xaddr1in6@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] ++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12] ++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] ++aout[8] aout[9] aout[TT] net@4 addr1in60Cx15 +Xdata1in6@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] ++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] ++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3] ++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] ++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] ++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] ++out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] ++out[6] out[7] out[8] out[9] net@5 data1in60Cx37 +XgaspDrai@0 clear net@4 go pred net@17[1] net@17[0] silent succ net@5 ain[TT] ++gaspDrain +XscanEx2v@1 net@17[1] net@17[0] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sor[1] scanEx2 +XscanFx3@0 go clear silent sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] ++sic[8] sic[9] soc[1] scanFx3 .ENDS drainStage -*** CELL: latchGroupsK:latchWscan{sch} -.SUBCKT latchWscan hcl in[1] out[1] p1p p2p rd sin sout wr +*** CELL: latchGroupsK:latchWscM2{sch} +.SUBCKT latchWscM2 hcl in[1] out[1] p1p p2p rd sin sout wr Xhi2inLat@1 hcl wr in[1] sout out[1] latch2in60C -XscanCell@2 out[1] p1p p2p rd sin sout scanCellE -.ENDS latchWscan +XscanCell@2 out[1] p1p p2p rd sin sout scanJ__scanCellE +.ENDS latchWscM2 + +*** CELL: registersM:addr1in60Cx7scan{sch} +.SUBCKT addr1in60Cx7scan ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] ++aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire p1p p2p rd sin ++sout wr[A] +Xla[1] fire ain[1] aout[1] p1p p2p rd sin xin[2] wr[A] latchWscM2 +Xla[2] fire ain[2] aout[2] p1p p2p rd xin[2] xin[3] wr[A] latchWscM2 +Xla[3] fire ain[3] aout[3] p1p p2p rd xin[3] xin[4] wr[A] latchWscM2 +Xla[4] fire ain[4] aout[4] p1p p2p rd xin[4] xin[5] wr[A] latchWscM2 +Xla[5] fire ain[5] aout[5] p1p p2p rd xin[5] xin[6] wr[A] latchWscM2 +Xla[6] fire ain[6] aout[6] p1p p2p rd xin[6] xin[7] wr[A] latchWscM2 +Xla[7] fire ain[7] aout[7] p1p p2p rd xin[7] sout wr[A] latchWscM2 +.ENDS addr1in60Cx7scan + +*** CELL: registersM:data1in60Cx18scan{sch} +.SUBCKT data1in60Cx18scan dcl in[10] in[11] in[12] in[13] in[14] in[15] ++in[16] in[17] in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] ++out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] ++out[1] out[2] out[3] out[4] out[5] out[6] out[7] out[8] out[9] p1p p2p rd sin ++sout wr[D] +Xla[1] dcl in[1] out[1] p1p p2p rd sin xin[2] wr[D] latchWscM2 +Xla[2] dcl in[2] out[2] p1p p2p rd xin[2] xin[3] wr[D] latchWscM2 +Xla[3] dcl in[3] out[3] p1p p2p rd xin[3] xin[4] wr[D] latchWscM2 +Xla[4] dcl in[4] out[4] p1p p2p rd xin[4] xin[5] wr[D] latchWscM2 +Xla[5] dcl in[5] out[5] p1p p2p rd xin[5] xin[6] wr[D] latchWscM2 +Xla[6] dcl in[6] out[6] p1p p2p rd xin[6] xin[7] wr[D] latchWscM2 +Xla[7] dcl in[7] out[7] p1p p2p rd xin[7] xin[8] wr[D] latchWscM2 +Xla[8] dcl in[8] out[8] p1p p2p rd xin[8] xin[9] wr[D] latchWscM2 +Xla[9] dcl in[9] out[9] p1p p2p rd xin[9] xin[10] wr[D] latchWscM2 +Xla[10] dcl in[10] out[10] p1p p2p rd xin[10] xin[11] wr[D] latchWscM2 +Xla[11] dcl in[11] out[11] p1p p2p rd xin[11] xin[12] wr[D] latchWscM2 +Xla[12] dcl in[12] out[12] p1p p2p rd xin[12] xin[13] wr[D] latchWscM2 +Xla[13] dcl in[13] out[13] p1p p2p rd xin[13] xin[14] wr[D] latchWscM2 +Xla[14] dcl in[14] out[14] p1p p2p rd xin[14] xin[15] wr[D] latchWscM2 +Xla[15] dcl in[15] out[15] p1p p2p rd xin[15] xin[16] wr[D] latchWscM2 +Xla[16] dcl in[16] out[16] p1p p2p rd xin[16] xin[17] wr[D] latchWscM2 +Xla[17] dcl in[17] out[17] p1p p2p rd xin[17] xin[18] wr[D] latchWscM2 +Xla[18] dcl in[18] out[18] p1p p2p rd xin[18] sout wr[D] latchWscM2 +.ENDS data1in60Cx18scan + +*** CELL: redFive:nms2{sch} +.SUBCKT nms2-X_30 d g g2 +XNMOS@0 d g2 net@0 NMOSx-X_60 +XNMOS@1 net@0 g gnd NMOSx-X_60 +.ENDS nms2-X_30 + +*** CELL: redFive:nand2{sch} +.SUBCKT nand2-X_30 ina inb out +XPMOS@0 out ina vdd PMOSx-X_30 +XPMOS@1 out inb vdd PMOSx-X_30 +Xnms2@0 out ina inb nms2-X_30 +.ENDS nand2-X_30 + +*** CELL: redFive:nor2HT_sy{sch} +.SUBCKT nor2HT_sy-X_10 ina inb out +XNMOS@0 out inb gnd NMOSx-X_5 +XNMOS@1 out ina gnd NMOSx-X_5 +Xpms2_sy@0 out ina inb pms2_sy-X_10 +.ENDS nor2HT_sy-X_10 -*** CELL: registersJ:addr1in14scan{sch} -.SUBCKT addr1in14scan ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] -+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] aout[10] aout[11] aout[12] -+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] -+aout[8] aout[9] fire p1p p2p rd sin sout wrA -Xls[1] fire ain[1] aout[1] p1p p2p rd sin xin[2] wrA latchWscan -Xls[2] fire ain[2] aout[2] p1p p2p rd xin[2] xin[3] wrA latchWscan -Xls[3] fire ain[3] aout[3] p1p p2p rd xin[3] xin[4] wrA latchWscan -Xls[4] fire ain[4] aout[4] p1p p2p rd xin[4] xin[5] wrA latchWscan -Xls[5] fire ain[5] aout[5] p1p p2p rd xin[5] xin[6] wrA latchWscan -Xls[6] fire ain[6] aout[6] p1p p2p rd xin[6] xin[7] wrA latchWscan -Xls[7] fire ain[7] aout[7] p1p p2p rd xin[7] xin[8] wrA latchWscan -Xls[8] fire ain[8] aout[8] p1p p2p rd xin[8] xin[9] wrA latchWscan -Xls[9] fire ain[9] aout[9] p1p p2p rd xin[9] xin[10] wrA latchWscan -Xls[10] fire ain[10] aout[10] p1p p2p rd xin[10] xin[11] wrA latchWscan -Xls[11] fire ain[11] aout[11] p1p p2p rd xin[11] xin[12] wrA latchWscan -Xls[12] fire ain[12] aout[12] p1p p2p rd xin[12] xin[13] wrA latchWscan -Xls[13] fire ain[13] aout[13] p1p p2p rd xin[13] xin[14] wrA latchWscan -Xls[14] fire ain[14] aout[14] p1p p2p rd xin[14] sout wrA latchWscan -.ENDS addr1in14scan - -*** CELL: scanJ:scanTwinAmp{sch} -.SUBCKT scanTwinAmp in[1] outA[1] outB[1] -Xinv@0 net@2 outA[1] inv-X_20 -Xinv@1 in[1] net@1 inv-X_10 -Xinv@2 net@2 outB[1] inv-X_40 -Xwire90@0 net@1 net@2 wire90-947_7-layer_1-width_3 -.ENDS scanTwinAmp - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-2534-R_34_667m a b -Ccap@0 gnd net@14 9.291f -Ccap@1 gnd net@8 9.291f -Ccap@2 gnd net@11 9.291f -Rres@0 net@14 a 14.641 -Rres@1 net@11 net@14 29.282 -Rres@2 b net@8 14.641 -Rres@3 net@8 net@11 29.282 -.ENDS wire-C_0_011f-2534-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-2534-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-2534-R_34_667m -.ENDS wire90-2534-layer_1-width_3 +*** CELL: centersJ:ctrAND3in100A{sch} +.SUBCKT ctrAND3in100A inA inB inC out +Xinv@4 inC net@30 inv-X_10 +Xinv@5 net@9 out inv-X_100 +Xnand2@0 net@19 net@15 net@27 nand2-X_30 +Xnor2HT_s@0 inA inB net@6 nor2HT_sy-X_10 +Xwire90@0 net@6 net@15 wire90-252_6-layer_1-width_3 +Xwire90@1 net@27 net@9 wire90-366_8-layer_1-width_3 +Xwire90@2 net@30 net@19 wire90-176_4-layer_1-width_3 +.ENDS ctrAND3in100A *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-918_6-R_34_667m a b @@ -6805,324 +7313,174 @@ Rres@3 net@8 net@11 13.601 Xwire@0 a b wire-C_0_011f-1177-R_34_667m .ENDS wire90-1177-layer_1-width_3 -*** CELL: registersJ:data1in38scan{sch} -.SUBCKT data1in38scan ain[T] aout[T] fire in[10] in[11] in[12] in[13] in[14] -+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] -+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] -+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] -+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] -+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] -+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] -+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] p1p p2p rd -+scanFromAddress scanToAddr sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] -+sid[8] sid[9] sod[2] sod[3] sod[4] sod[5] wrA -XdataDriv@0 ain[T] fire net@120 dataDriver70 -XdataDriv@1 net@115 net@137 wrD dataDriver70 -XdataDriv@2 xin[1] wrr wrA dataDriver70 -XlatchWsc@1 fire ain[T] aout[T] p1p p2p rd xin[38] scanToAddr wrA latchWscan -Xls[1] net@124 in[1] out[1] p1p p2p rd xin[1] xin[2] wrD latchWscan -Xls[2] net@124 in[2] out[2] p1p p2p rd xin[2] xin[3] wrD latchWscan -Xls[3] net@124 in[3] out[3] p1p p2p rd xin[3] xin[4] wrD latchWscan -Xls[4] net@124 in[4] out[4] p1p p2p rd xin[4] xin[5] wrD latchWscan -Xls[5] net@124 in[5] out[5] p1p p2p rd xin[5] xin[6] wrD latchWscan -Xls[6] net@124 in[6] out[6] p1p p2p rd xin[6] xin[7] wrD latchWscan -Xls[7] net@124 in[7] out[7] p1p p2p rd xin[7] xin[8] wrD latchWscan -Xls[8] net@124 in[8] out[8] p1p p2p rd xin[8] xin[9] wrD latchWscan -Xls[9] net@124 in[9] out[9] p1p p2p rd xin[9] xin[10] wrD latchWscan -Xls[10] net@124 in[10] out[10] p1p p2p rd xin[10] xin[11] wrD latchWscan -Xls[11] net@124 in[11] out[11] p1p p2p rd xin[11] xin[12] wrD latchWscan -Xls[12] net@124 in[12] out[12] p1p p2p rd xin[12] xin[13] wrD latchWscan -Xls[13] net@124 in[13] out[13] p1p p2p rd xin[13] xin[14] wrD latchWscan -Xls[14] net@124 in[14] out[14] p1p p2p rd xin[14] xin[15] wrD latchWscan -Xls[15] net@124 in[15] out[15] p1p p2p rd xin[15] xin[16] wrD latchWscan -Xls[16] net@124 in[16] out[16] p1p p2p rd xin[16] xin[17] wrD latchWscan -Xls[17] net@124 in[17] out[17] p1p p2p rd xin[17] xin[18] wrD latchWscan -Xls[18] net@124 in[18] out[18] p1p p2p rd xin[18] xin[19] wrD latchWscan -Xls[19] net@124 in[19] out[19] p1p p2p rd xin[19] xin[20] wrD latchWscan -Xls[20] net@124 in[20] out[20] p1p p2p rd xin[20] xin[21] wrD latchWscan -Xls[21] net@124 in[21] out[21] p1p p2p rd xin[21] xin[22] wrD latchWscan -Xls[22] net@124 in[22] out[22] p1p p2p rd xin[22] xin[23] wrD latchWscan -Xls[23] net@124 in[23] out[23] p1p p2p rd xin[23] xin[24] wrD latchWscan -Xls[24] net@124 in[24] out[24] p1p p2p rd xin[24] xin[25] wrD latchWscan -Xls[25] net@124 in[25] out[25] p1p p2p rd xin[25] xin[26] wrD latchWscan -Xls[26] net@124 in[26] out[26] p1p p2p rd xin[26] xin[27] wrD latchWscan -Xls[27] net@124 in[27] out[27] p1p p2p rd xin[27] xin[28] wrD latchWscan -Xls[28] net@124 in[28] out[28] p1p p2p rd xin[28] xin[29] wrD latchWscan -Xls[29] net@124 in[29] out[29] p1p p2p rd xin[29] xin[30] wrD latchWscan -Xls[30] net@124 in[30] out[30] p1p p2p rd xin[30] xin[31] wrD latchWscan -Xls[31] net@124 in[31] out[31] p1p p2p rd xin[31] xin[32] wrD latchWscan -Xls[32] net@124 in[32] out[32] p1p p2p rd xin[32] xin[33] wrD latchWscan -Xls[33] net@124 in[33] out[33] p1p p2p rd xin[33] xin[34] wrD latchWscan -Xls[34] net@124 in[34] out[34] p1p p2p rd xin[34] xin[35] wrD latchWscan -Xls[35] net@124 in[35] out[35] p1p p2p rd xin[35] xin[36] wrD latchWscan -Xls[36] net@124 in[36] out[36] p1p p2p rd xin[36] xin[37] wrD latchWscan -Xls[37] net@124 in[37] out[37] p1p p2p rd xin[37] xin[38] wrD latchWscan -Xsa[1] sid[2] sod[2] p2p scanTwinAmp -Xsa[2] sid[3] sod[3] p1p scanTwinAmp -Xsa[3] sid[4] sod[4] wrr scanTwinAmp -Xsa[4] sid[5] sod[5] rd scanTwinAmp -XscanCell@0 scanCell@0_dIn[1] p1p p2p rd sid[1] net@130 scanCellE -XscanCell@1 scanCell@1_dIn[1] p1p p2p rd net@115 xin[1] scanCellE -Xwire90@0 net@124 net@120 wire90-2534-layer_1-width_3 -Xwire90@2 net@124 net@120 wire90-2534-layer_1-width_3 -Xwire90@3 net@130 net@115 wire90-918_6-layer_1-width_3 -Xwire90@5 net@137 wrr wire90-1177-layer_1-width_3 -.ENDS data1in38scan - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-2975_6-R_34_667m a b -Ccap@0 gnd net@14 10.911f -Ccap@1 gnd net@8 10.911f -Ccap@2 gnd net@11 10.911f -Rres@0 net@14 a 17.192 -Rres@1 net@11 net@14 34.385 -Rres@2 b net@8 17.192 -Rres@3 net@8 net@11 34.385 -.ENDS wire-C_0_011f-2975_6-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-2975_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-2975_6-R_34_667m -.ENDS wire90-2975_6-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-2989_9-R_34_667m a b -Ccap@0 gnd net@14 10.963f -Ccap@1 gnd net@8 10.963f -Ccap@2 gnd net@11 10.963f -Rres@0 net@14 a 17.275 -Rres@1 net@11 net@14 34.55 -Rres@2 b net@8 17.275 -Rres@3 net@8 net@11 34.55 -.ENDS wire-C_0_011f-2989_9-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-2989_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-2989_9-R_34_667m -.ENDS wire90-2989_9-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-12168-R_34_667m a b -Ccap@0 gnd net@14 44.616f -Ccap@1 gnd net@8 44.616f -Ccap@2 gnd net@11 44.616f -Rres@0 net@14 a 70.304 -Rres@1 net@11 net@14 140.608 -Rres@2 b net@8 70.304 -Rres@3 net@8 net@11 140.608 -.ENDS wire-C_0_011f-12168-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-12168-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-12168-R_34_667m -.ENDS wire90-12168-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-12492-R_34_667m a b -Ccap@0 gnd net@14 45.804f -Ccap@1 gnd net@8 45.804f -Ccap@2 gnd net@11 45.804f -Rres@0 net@14 a 72.176 -Rres@1 net@11 net@14 144.352 -Rres@2 b net@8 72.176 -Rres@3 net@8 net@11 144.352 -.ENDS wire-C_0_011f-12492-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-12492-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-12492-R_34_667m -.ENDS wire90-12492-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-3927_5-R_34_667m a b -Ccap@0 gnd net@14 14.401f -Ccap@1 gnd net@8 14.401f -Ccap@2 gnd net@11 14.401f -Rres@0 net@14 a 22.692 -Rres@1 net@11 net@14 45.384 -Rres@2 b net@8 22.692 -Rres@3 net@8 net@11 45.384 -.ENDS wire-C_0_011f-3927_5-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-3927_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-3927_5-R_34_667m -.ENDS wire90-3927_5-layer_1-width_3 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-11401_6-R_34_667m a b -Ccap@0 gnd net@14 41.806f -Ccap@1 gnd net@8 41.806f -Ccap@2 gnd net@11 41.806f -Rres@0 net@14 a 65.876 -Rres@1 net@11 net@14 131.752 -Rres@2 b net@8 65.876 -Rres@3 net@8 net@11 131.752 -.ENDS wire-C_0_011f-11401_6-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-11401_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-11401_6-R_34_667m -.ENDS wire90-11401_6-layer_1-width_3 - -*** CELL: registersJ:all1in52scan{sch} -.SUBCKT all1in52scan ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] -+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] -+aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] -+aout[7] aout[8] aout[9] aout[T] fire in[10] in[11] in[12] in[13] in[14] -+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] -+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] -+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] -+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] -+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] -+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] -+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] sid[1] -+sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sod[1] sod[2] sod[3] -+sod[4] sod[5] -Xaddr1in1@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] -+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] aout[10] aout[11] aout[12] aout[13] -+aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] -+aout[9] fire p1p p2p rd net@4 net@26 wrA addr1in14scan -Xdata1in3@0 ain[T] aout[T] fire in[10] in[11] in[12] in[13] in[14] in[15] -+in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] -+in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] -+in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] -+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] -+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] -+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] -+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] p1p p2p rd sod[1] -+net@1 sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sod[2] -+sod[3] sod[4] sod[5] wrA data1in38scan -Xwire90@0 net@26 sod[1] wire90-2975_6-layer_1-width_3 -Xwire90@1 net@4 net@1 wire90-2989_9-layer_1-width_3 -Xwire90@2 wire90@2_a p2p wire90-12168-layer_1-width_3 -Xwire90@3 wire90@3_a p1p wire90-12492-layer_1-width_3 -Xwire90@4 wire90@4_a wrA wire90-3927_5-layer_1-width_3 -Xwire90@5 wire90@5_a rd wire90-11401_6-layer_1-width_3 -.ENDS all1in52scan - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-403-R_34_667m a b -Ccap@0 gnd net@14 1.478f -Ccap@1 gnd net@8 1.478f -Ccap@2 gnd net@11 1.478f -Rres@0 net@14 a 2.328 -Rres@1 net@11 net@14 4.657 -Rres@2 b net@8 2.328 -Rres@3 net@8 net@11 4.657 -.ENDS wire-C_0_011f-403-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-403-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-403-R_34_667m -.ENDS wire90-403-layer_1-width_3 +*** CELL: gaspM:fillScanControl{sch} +.SUBCKT fillScanControl si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] ++so[1] wr[A] wr[D] +XdataDriv@2 so[1] si[4] wr[D] dataDriver60 +XdataDriv@3 net@4 net@21 wr[A] dataDriver60 +XscanCell@0 scanCell@0_dIn[1] si[3] si[2] si[5] si[1] net@7 scanJ__scanCellE +XscanCell@1 scanCell@1_dIn[1] si[3] si[2] si[5] net@4 so[1] scanJ__scanCellE +Xwire90@0 net@7 net@4 wire90-918_6-layer_1-width_3 +Xwire90@1 net@21 si[4] wire90-1177-layer_1-width_3 +.ENDS fillScanControl + +*** CELL: redFive:pms2_sy{sch} +.SUBCKT pms2_sy-X_20 d g g2 +Xpms2@0 d g g2 pms2-X_10 +Xpms2@1 d g2 g pms2-X_10 +.ENDS pms2_sy-X_20 + +*** CELL: redFive:nor2_sy{sch} +.SUBCKT nor2_sy-X_20 ina inb out +XNMOS@0 out inb gnd NMOSx-X_20 +XNMOS@1 out ina gnd NMOSx-X_20 +Xpms2_sy@0 out ina inb pms2_sy-X_20 +.ENDS nor2_sy-X_20 + +*** CELL: driversJ:sucORdri60{sch} +.SUBCKT sucORdri60 inA inB succ +XPMOSx@0 succ net@51 vdd PMOSx-X_60 +Xinv@0 succ net@71 inv-X_5 +Xnms2@0 succ net@51 net@72 nms2-X_8 +Xnor2_sy@0 inA inB net@67 nor2_sy-X_20 +Xwire90@0 net@67 net@51 wire90-1001_8-layer_1-width_3 +Xwire90@1 net@72 net@71 wire90-209-layer_1-width_3 +.ENDS sucORdri60 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-959-R_34_667m a b -Ccap@0 gnd net@14 3.516f -Ccap@1 gnd net@8 3.516f -Ccap@2 gnd net@11 3.516f -Rres@0 net@14 a 5.541 -Rres@1 net@11 net@14 11.082 -Rres@2 b net@8 5.541 -Rres@3 net@8 net@11 11.082 -.ENDS wire-C_0_011f-959-R_34_667m +.SUBCKT wire-C_0_011f-602_3-R_34_667m a b +Ccap@0 gnd net@14 2.208f +Ccap@1 gnd net@8 2.208f +Ccap@2 gnd net@11 2.208f +Rres@0 net@14 a 3.48 +Rres@1 net@11 net@14 6.96 +Rres@2 b net@8 3.48 +Rres@3 net@8 net@11 6.96 +.ENDS wire-C_0_011f-602_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-959-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-959-R_34_667m -.ENDS wire90-959-layer_1-width_3 +.SUBCKT wire90-602_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-602_3-R_34_667m +.ENDS wire90-602_3-layer_1-width_3 -*** CELL: centersJ:ctrAND3in100HT{sch} -.SUBCKT ctrAND3in100HT inA inB inC out -Xinv@3 net@104 out inv-X_100 -Xinv@4 inC net@143 inv-X_10 -Xnand2_sy@0 net@131 net@137 net@134 nand2_sy-X_30 -Xnor2HT_s@0 inA inB net@130 nor2HT_sy-X_10 -Xwire90@0 net@130 net@131 wire90-403-layer_1-width_3 -Xwire90@4 net@134 net@104 wire90-959-layer_1-width_3 -Xwire90@5 net@143 net@137 wire90-403-layer_1-width_3 -.ENDS ctrAND3in100HT - -*** CELL: scanJ:scanFx2vert{sch} -.SUBCKT scanFx2vert dout[1] dout[2] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] -+sic[7] sic[8] sic[9] soc[1] -XscanCell@1 dout[2] sic[9] sic[3] sic[2] sic[5] net@32 soc[1] sic[4] -+scanCellF -XscanCell@2 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] net@30 sic[4] -+scanCellF -Xwire90@0 net@30 net@32 wire90-297_6-layer_1-width_3 -.ENDS scanFx2vert - -*** CELL: gaspL:gaspFill{sch} -.SUBCKT gaspFill fire pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] -+sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] -+soc[1] sor[1] succ -XctrAND3i@0 net@241 succ fire fire[B] ctrAND3in100HT -XctrAND3i@1 net@454 succ net@541 fire ctrAND3in100HT +*** CELL: gaspM:gaspFill{sch} +.SUBCKT gaspFill block fill fire pred s[1] s[2] si[1] si[2] si[3] si[4] si[5] ++si[6] si[7] si[8] si[9] so[1] succ take wr[A] wr[D] +XctrAND3i@1 net@602 succ fire fire[B] ctrAND3in30 +XctrAND3i@3 net@454 succ block fire ctrAND3in100A +XfillScan@1 si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] so[1] wr[A] ++wr[D] fillScanControl Xinv@0 pred net@533 inv-X_5 -Xinv@1 net@465 net@537 inv-X_5 -XpredDri2@0 fire sir[9] pred predDri20wMC -XscanEx2v@2 pred net@465 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sor[1] scanEx2vert -XscanFx2v@0 block fill sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] -+sic[8] sic[9] soc[1] scanFx2vert -XsucORdri@2 fire net@320 succ sucORdri20 -Xwire90@1 net@537 net@241 wire90-602_3-layer_1-width_3 -Xwire90@10 net@465 fill wire90-602_3-layer_1-width_3 +Xinv@1 fill net@537 inv-X_5 +XinvI@0 net@454 s[1] inv-X_10 +XinvI@1 net@602 s[2] inv-X_10 +XlatchDri@0 fire take latchDriver60 +XpredDri6@2 fire si[9] pred driversL__predDri60wMC +XsucORdri@1 fire net@320 succ sucORdri60 +Xwire90@1 net@537 net@602 wire90-602_3-layer_1-width_3 Xwire90@12 net@533 net@454 wire90-602_3-layer_1-width_3 -Xwire90@14 net@541 block wire90-602_3-layer_1-width_3 Xwire90@15 fire[B] net@320 wire90-602_3-layer_1-width_3 .ENDS gaspFill *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-5449_9-R_34_667m a b -Ccap@0 gnd net@14 19.983f -Ccap@1 gnd net@8 19.983f -Ccap@2 gnd net@11 19.983f -Rres@0 net@14 a 31.488 -Rres@1 net@11 net@14 62.977 -Rres@2 b net@8 31.488 -Rres@3 net@8 net@11 62.977 -.ENDS wire-C_0_011f-5449_9-R_34_667m +.SUBCKT wire-C_0_011f-70-R_34_667m a b +Ccap@0 gnd net@14 0.257f +Ccap@1 gnd net@8 0.257f +Ccap@2 gnd net@11 0.257f +Rres@0 net@14 a 0.404 +Rres@1 net@11 net@14 0.809 +Rres@2 b net@8 0.404 +Rres@3 net@8 net@11 0.809 +.ENDS wire-C_0_011f-70-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-5449_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-5449_9-R_34_667m -.ENDS wire90-5449_9-layer_1-width_3 +.SUBCKT wire90-70-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-70-R_34_667m +.ENDS wire90-70-layer_1-width_3 + +*** CELL: scanJ:scanAmp{sch} +.SUBCKT scanAmp in[1] out[1] +Xinv@0 in[1] net@1 inv-X_10 +Xinv@1 net@2 out[1] inv-X_20 +Xwire90@0 net@1 net@2 wire90-70-layer_1-width_3 +.ENDS scanAmp -*** CELL: stagesL:fillStage{sch} +*** CELL: gaspM:scanAMPx5{sch} +.SUBCKT scanAMPx5 si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] so[1] ++so[2] so[3] so[4] so[5] +Xsa[1] si[1] so[1] scanAmp +Xsa[2] si[2] so[2] scanAmp +Xsa[3] si[3] so[3] scanAmp +Xsa[4] si[4] so[4] scanAmp +Xsa[5] si[5] so[5] scanAmp +.ENDS scanAMPx5 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-2500-R_34_667m a b +Ccap@0 gnd net@14 9.167f +Ccap@1 gnd net@8 9.167f +Ccap@2 gnd net@11 9.167f +Rres@0 net@14 a 14.444 +Rres@1 net@11 net@14 28.889 +Rres@2 b net@8 14.444 +Rres@3 net@8 net@11 28.889 +.ENDS wire-C_0_011f-2500-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-2500-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-2500-R_34_667m +.ENDS wire90-2500-layer_1-width_3 + +*** CELL: stagesM:fillStage{sch} .SUBCKT fillStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] -+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] ++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] +aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] -+aout[7] aout[8] aout[9] aout[T] in[10] in[11] in[12] in[13] in[14] in[15] -+in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] -+in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] -+in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] -+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] -+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] -+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] -+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] sic[2] -+sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] -+sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] succ -Xall1in52@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] -+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] aout[12] -+aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] -+aout[8] aout[9] aout[T] net@2 in[10] in[11] in[12] in[13] in[14] in[15] -+in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] -+in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] -+in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] -+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] -+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] -+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] -+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] sid[1] sid[2] sid[3] -+sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sod[1] sod[2] sod[3] sod[4] sod[5] -+all1in52scan -XgaspFill@0 net@0 pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] -+sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] -+soc[1] sor[1] succ gaspFill -Xwire90@0 net@0 net@2 wire90-5449_9-layer_1-width_3 ++aout[7] aout[8] aout[9] aout[TT] extra fire in[10] in[11] in[12] in[13] ++in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] ++in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] ++in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] ++out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] ++out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] ++out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] ++out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] ++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] ++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] ++succ +Xaddr1in6@0 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2] ++aout[3] aout[4] aout[5] aout[6] aout[7] net@13 sx[3] sx[2] sx[5] net@61 ++net@62 sx[A] addr1in60Cx7scan +Xaddr1in6@1 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8] ++aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@16 sx[3] sx[2] sx[5] ++net@62 net@66 sx[A] addr1in60Cx7scan +Xdata1in6@0 net@3 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] ++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3] ++out[4] out[5] out[6] out[7] out[8] out[9] sx[3] sx[2] sx[5] net@66 net@65 ++sx[D] data1in60Cx18scan +Xdata1in6@1 net@0 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36] ++in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29] ++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20] ++out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] sx[3] sx[2] ++sx[5] net@64 sz[1] sx[D] data1in60Cx18scan +XgaspFill@0 block fill fire pred s[1] s[2] sx[1] sx[2] sx[3] sx[4] sx[5] ++sid[6] sid[7] sid[8] sid[9] sy[1] succ net@8 sx[A] sx[D] gaspFill +XlatchWsc@0 net@0 in[19] out[19] sx[3] sx[2] sx[5] net@65 net@64 sx[D] ++latchWscM2 +XlatchWsc@1 net@13 ain[TT] aout[TT] sx[3] sx[2] sx[5] sy[1] net@61 sx[A] ++latchWscM2 +XscanAMPx@0 sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] ++sx[1] sx[2] sx[3] sx[4] sx[5] scanAMPx5 +XscanAMPx@1 sz[1] sx[2] sx[3] sx[4] sx[5] sid[6] sid[7] sid[8] sid[9] sod[1] ++sod[2] sod[3] sod[4] sod[5] scanAMPx5 +XscanEx2@0 s[1] s[2] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx2 +XscanFx3@0 block extra fill sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] ++sic[8] sic[9] soc[1] scanFx3 +Xwire90@1 net@8 net@0 wire90-2550-layer_1-width_3 +Xwire90@3 fire net@16 wire90-2500-layer_1-width_3 +Xwire90@4 net@3 net@8 wire90-2550-layer_1-width_3 +Xwire90@5 net@13 fire wire90-2500-layer_1-width_3 .ENDS fillStage *** CELL: orangeTSMC090nm:wire{sch} @@ -7141,14 +7499,14 @@ Rres@3 net@8 net@11 24.04 Xwire@0 a b wire-C_0_011f-2080_4-R_34_667m .ENDS wire90-2080_4-layer_1-width_3 -*** CELL: stageGroupsL:properStopper{sch} +*** CELL: stageGroupsM:properStopper{sch} .SUBCKT properStopper ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] -+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] ++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] +aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] -+aout[7] aout[8] aout[9] aout[T] dOut fire in[10] in[11] in[12] in[13] in[14] -+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] -+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] -+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] ++aout[7] aout[8] aout[9] aout[TT] extra fire in[10] in[11] in[12] in[13] ++in[14] in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] ++in[24] in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] ++in[34] in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] +out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] +out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] +out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] @@ -7157,46 +7515,47 @@ Xwire@0 a b wire-C_0_011f-2080_4-R_34_667m +sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] +sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] +succ -XdrainSta@0 net@1[4] net@1[3] net@1[2] net@1[1] net@1[0] net@1[13] net@1[12] -+net@1[11] net@1[10] net@1[9] net@1[8] net@1[7] net@1[6] net@1[5] net@1[14] -+aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] -+aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] dOut fire net@1[42] net@1[41] -+net@1[40] net@1[39] net@1[38] net@1[37] net@1[36] net@1[35] net@1[34] -+net@1[33] net@1[51] net@1[32] net@1[31] net@1[30] net@1[29] net@1[28] -+net@1[27] net@1[26] net@1[25] net@1[24] net@1[23] net@1[50] net@1[22] -+net@1[21] net@1[20] net@1[19] net@1[18] net@1[17] net@1[16] net@1[15] -+net@1[49] net@1[48] net@1[47] net@1[46] net@1[45] net@1[44] net@1[43] out[10] -+out[11] out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] -+out[1] out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] -+out[28] out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] -+out[36] out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] net@42 -+net@3[8] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] net@2[8] -+sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sor[1] succ -+drainStage -XfillStag@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] -+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] net@1[4] net@1[3] net@1[2] -+net@1[1] net@1[0] net@1[13] net@1[12] net@1[11] net@1[10] net@1[9] net@1[8] -+net@1[7] net@1[6] net@1[5] net@1[14] in[10] in[11] in[12] in[13] in[14] -+in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] -+in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] -+in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] net@1[42] -+net@1[41] net@1[40] net@1[39] net@1[38] net@1[37] net@1[36] net@1[35] -+net@1[34] net@1[33] net@1[51] net@1[32] net@1[31] net@1[30] net@1[29] -+net@1[28] net@1[27] net@1[26] net@1[25] net@1[24] net@1[23] net@1[50] -+net@1[22] net@1[21] net@1[20] net@1[19] net@1[18] net@1[17] net@1[16] -+net@1[15] net@1[49] net@1[48] net@1[47] net@1[46] net@1[45] net@1[44] -+net@1[43] pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] -+sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] -+sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@3[8] sod[1] sod[2] -+sod[3] sod[4] sod[5] net@2[8] net@41 fillStage +XdrainSta@1 net@65[41] net@65[40] net@65[39] net@65[38] net@65[37] net@65[50] ++net@65[49] net@65[48] net@65[47] net@65[46] net@65[45] net@65[44] net@65[43] ++net@65[42] net@65[51] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] ++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] ++net@65[27] net@65[26] net@65[25] net@65[24] net@65[23] net@65[22] net@65[21] ++net@65[20] net@65[19] net@65[18] net@65[36] net@65[17] net@65[16] net@65[15] ++net@65[14] net@65[13] net@65[12] net@65[11] net@65[10] net@65[9] net@65[8] ++net@65[35] net@65[7] net@65[6] net@65[5] net@65[4] net@65[3] net@65[2] ++net@65[1] net@65[0] net@65[34] net@65[33] net@65[32] net@65[31] net@65[30] ++net@65[29] net@65[28] out[10] out[11] out[12] out[13] out[14] out[15] out[16] ++out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] ++out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] ++out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] ++out[8] out[9] net@42 net@3[8] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] ++sic[8] sic[9] net@2[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] ++sir[9] soc[1] sor[1] succ drainStage +XfillStag@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] ++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] net@65[41] net@65[40] ++net@65[39] net@65[38] net@65[37] net@65[50] net@65[49] net@65[48] net@65[47] ++net@65[46] net@65[45] net@65[44] net@65[43] net@65[42] net@65[51] extra fire ++in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] in[19] in[1] ++in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] in[29] in[2] ++in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3] in[4] in[5] ++in[6] in[7] in[8] in[9] net@65[27] net@65[26] net@65[25] net@65[24] ++net@65[23] net@65[22] net@65[21] net@65[20] net@65[19] net@65[18] net@65[36] ++net@65[17] net@65[16] net@65[15] net@65[14] net@65[13] net@65[12] net@65[11] ++net@65[10] net@65[9] net@65[8] net@65[35] net@65[7] net@65[6] net@65[5] ++net@65[4] net@65[3] net@65[2] net@65[1] net@65[0] net@65[34] net@65[33] ++net@65[32] net@65[31] net@65[30] net@65[29] net@65[28] pred sic[1] sic[2] ++sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] ++sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sir[9] net@3[8] sod[1] sod[2] sod[3] sod[4] sod[5] net@2[8] ++net@41 fillStage Xwire90@0 net@41 net@42 wire90-2080_4-layer_1-width_3 .ENDS properStopper -*** CELL: stageGroupsL:fillDrainCount{sch} +*** CELL: stageGroupsM:fillDrainCount{sch} .SUBCKT fillDrainCount ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] -+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] ++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] +aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] -+aout[7] aout[8] aout[9] aout[T] fin fout in[10] in[11] in[12] in[13] in[14] ++aout[7] aout[8] aout[9] aout[TT] fin fout in[10] in[11] in[12] in[13] in[14] +in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] +in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] +in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] @@ -7210,10 +7569,10 @@ Xwire90@0 net@41 net@42 wire90-2080_4-layer_1-width_3 +succ Xinstruct@0 net@53 net@48 fin fout net@61[8] sod[2] sod[3] sod[4] sod[5] +sid[6] sid[7] sid[8] sid[9] sod[1] instructionCount -XproperSt@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] -+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] aout[12] +XproperSt@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] ++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12] +aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] -+aout[8] aout[9] aout[T] net@75 net@53 in[10] in[11] in[12] in[13] in[14] ++aout[8] aout[9] aout[TT] net@86 net@53 in[10] in[11] in[12] in[13] in[14] +in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] +in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] +in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] @@ -7225,132 +7584,102 @@ XproperSt@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] +sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] +sir[6] sir[7] sir[8] sir[9] soc[1] net@61[8] sod[2] sod[3] sod[4] sod[5] +sor[1] succ properStopper -Xwire90@1 net@75 net@48 wire90-2080_4-layer_1-width_3 +Xwire90@1 net@86 net@48 wire90-2080_4-layer_1-width_3 .ENDS fillDrainCount -*** CELL: scanJ:scanCap{sch} +*** CELL: scanM:scanCap{sch} .SUBCKT scanCap si[1] si[2] si[3] si[4] si[5] si[9] .ENDS scanCap -*** CELL: scanK:scanEx1vertFup{sch} -.SUBCKT scanEx1vertFup dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sor[1] -XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanCellE -.ENDS scanEx1vertFup - -*** CELL: gaspL:gaspWeakUp{sch} -.SUBCKT gaspWeakUp fire pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sir[9] sor[1] succ -XctrAND2i@0 net@16 succ fire ctrAND2in100LT -Xinv@1 pred net@9 inv-X_10 -XpredDri2@0 fire net@25 pred predDri20wMC -XscanEx1v@2 pred sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertFup -XsucDri20@0 fire succ sucDri20 -Xwire90@1 net@9 net@16 wire90-602_3-layer_1-width_3 -Xwire90@2 net@25 sir[9] wire90-602_3-layer_1-width_3 -.ENDS gaspWeakUp - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-5130_5-R_34_667m a b -Ccap@0 gnd net@14 18.812f -Ccap@1 gnd net@8 18.812f -Ccap@2 gnd net@11 18.812f -Rres@0 net@14 a 29.643 -Rres@1 net@11 net@14 59.286 -Rres@2 b net@8 29.643 -Rres@3 net@8 net@11 59.286 -.ENDS wire-C_0_011f-5130_5-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-5130_5-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-5130_5-R_34_667m -.ENDS wire90-5130_5-layer_1-width_3 - -*** CELL: stagesL:weakStageUp{sch} -.SUBCKT weakStageUp ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] -+ainU[2] ainU[3] ainU[4] ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[T] -+aoutU[10] aoutU[11] aoutU[12] aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] -+aoutU[4] aoutU[5] aoutU[6] aoutU[7] aoutU[8] aoutU[9] aoutU[T] inU[10] -+inU[11] inU[12] inU[13] inU[14] inU[15] inU[16] inU[17] inU[18] inU[19] -+inU[1] inU[20] inU[21] inU[22] inU[23] inU[24] inU[25] inU[26] inU[27] -+inU[28] inU[29] inU[2] inU[30] inU[31] inU[32] inU[33] inU[34] inU[35] -+inU[36] inU[37] inU[3] inU[4] inU[5] inU[6] inU[7] inU[8] inU[9] outU[10] -+outU[11] outU[12] outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] -+outU[19] outU[1] outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] -+outU[26] outU[27] outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] -+outU[33] outU[34] outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] -+outU[7] outU[8] outU[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sir[9] sor[1] succ -Xall1in52@2 ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2] -+ainU[3] ainU[4] ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[T] aoutU[10] -+aoutU[11] aoutU[12] aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] -+aoutU[5] aoutU[6] aoutU[7] aoutU[8] aoutU[9] aoutU[T] net@2 inU[10] inU[11] -+inU[12] inU[13] inU[14] inU[15] inU[16] inU[17] inU[18] inU[19] inU[1] -+inU[20] inU[21] inU[22] inU[23] inU[24] inU[25] inU[26] inU[27] inU[28] -+inU[29] inU[2] inU[30] inU[31] inU[32] inU[33] inU[34] inU[35] inU[36] -+inU[37] inU[3] inU[4] inU[5] inU[6] inU[7] inU[8] inU[9] outU[10] outU[11] -+outU[12] outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] outU[19] -+outU[1] outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] outU[26] -+outU[27] outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] outU[33] -+outU[34] outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7] -+outU[8] outU[9] all1in52weak -XgaspPlai@1 net@0 pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sir[9] sor[1] succ gaspWeakUp -Xwire90@0 net@0 net@2 wire90-5130_5-layer_1-width_3 -.ENDS weakStageUp - -*** CELL: scanK:scanEx1vertFdn{sch} -.SUBCKT scanEx1vertFdn dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sor[8] -XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sor[8] sir[8] scanCellE -.ENDS scanEx1vertFdn - -*** CELL: gaspL:gaspWeakDn{sch} -.SUBCKT gaspWeakDn fire pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sir[9] sor[8] succ -XctrAND2i@0 net@16 succ fire ctrAND2in100LT -Xinv@1 pred net@9 inv-X_10 -XpredDri2@0 fire net@25 pred predDri20wMC -XscanEx1v@1 pred sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[8] scanEx1vertFdn +*** CELL: registersM:addr1in20Bx7{sch} +.SUBCKT addr1in20Bx7 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] ++aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] fire +Xlat[1] fire ain[1] aout[1] latch1in20B +Xlat[2] fire ain[2] aout[2] latch1in20B +Xlat[3] fire ain[3] aout[3] latch1in20B +Xlat[4] fire ain[4] aout[4] latch1in20B +Xlat[5] fire ain[5] aout[5] latch1in20B +Xlat[6] fire ain[6] aout[6] latch1in20B +Xlat[7] fire ain[7] aout[7] latch1in20B +.ENDS addr1in20Bx7 + +*** CELL: registersM:addr1in20Bx15{sch} +.SUBCKT addr1in20Bx15 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] ++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] ++aout[7] aout[8] aout[9] aout[TT] fire +Xaddr1in2@1 ain[8] ain[9] ain[10] ain[11] ain[12] ain[13] ain[14] aout[8] ++aout[9] aout[10] aout[11] aout[12] aout[13] aout[14] net@17 addr1in20Bx7 +Xaddr1in2@2 ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] aout[1] aout[2] ++aout[3] aout[4] aout[5] aout[6] aout[7] net@19 addr1in20Bx7 +Xlatch1in@1 fire ain[TT] aout[TT] latch1in20B +Xwire90@0 net@19 fire wire90-2330-layer_1-width_3 +Xwire90@1 fire net@17 wire90-2330-layer_1-width_3 +.ENDS addr1in20Bx15 + +*** CELL: registersM:data1in20Bx37{sch} +.SUBCKT data1in20Bx37 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] ++in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] ++in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] ++out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] ++out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] ++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] ++out[5] out[6] out[7] out[8] out[9] take +Xins1in20@0 net@17 in[29] in[30] in[31] in[32] in[33] in[34] in[35] in[36] ++in[37] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] out[29] ++out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[20] ++out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] ins1in20Bx18 +Xins1in20@1 net@19 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] ++in[18] in[1] in[2] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] ++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[1] out[2] out[3] ++out[4] out[5] out[6] out[7] out[8] out[9] ins1in20Bx18 +Xlatch1in@1 take in[19] out[19] latch1in20B +Xwire90@2 take net@17 wire90-2550-layer_1-width_3 +Xwire90@3 net@19 take wire90-2550-layer_1-width_3 +.ENDS data1in20Bx37 + +*** CELL: gaspM:gaspWeak{sch} +.SUBCKT gaspWeak fire mc pred s[1] succ take tok +XctrAND2i@0 net@10 succ fire ctrAND2in100LT +XdataDriv@0 tok fire take dataDriver60 +Xinv@0 pred net@8 inv-X_5 +XinvI@0 net@10 s[1] inv-X_10 +XpredDri2@0 net@30 mc pred predDri20wMC XsucDri20@0 fire succ sucDri20 -Xwire90@1 net@9 net@16 wire90-602_3-layer_1-width_3 -Xwire90@2 net@25 sir[9] wire90-602_3-layer_1-width_3 -.ENDS gaspWeakDn - -*** CELL: stagesL:weakStageDn{sch} -.SUBCKT weakStageDn ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] -+ainD[2] ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[T] -+aoutD[10] aoutD[11] aoutD[12] aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] -+aoutD[4] aoutD[5] aoutD[6] aoutD[7] aoutD[8] aoutD[9] aoutD[T] inD[10] -+inD[11] inD[12] inD[13] inD[14] inD[15] inD[16] inD[17] inD[18] inD[19] -+inD[1] inD[20] inD[21] inD[22] inD[23] inD[24] inD[25] inD[26] inD[27] -+inD[28] inD[29] inD[2] inD[30] inD[31] inD[32] inD[33] inD[34] inD[35] -+inD[36] inD[37] inD[3] inD[4] inD[5] inD[6] inD[7] inD[8] inD[9] outD[10] -+outD[11] outD[12] outD[13] outD[14] outD[15] outD[16] outD[17] outD[18] -+outD[19] outD[1] outD[20] outD[21] outD[22] outD[23] outD[24] outD[25] -+outD[26] outD[27] outD[28] outD[29] outD[2] outD[30] outD[31] outD[32] -+outD[33] outD[34] outD[35] outD[36] outD[37] outD[3] outD[4] outD[5] outD[6] -+outD[7] outD[8] outD[9] predD sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sir[9] sor[8] succD -Xall1in52@2 ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] ainD[2] -+ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[T] aoutD[10] -+aoutD[11] aoutD[12] aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] -+aoutD[5] aoutD[6] aoutD[7] aoutD[8] aoutD[9] aoutD[T] net@2 inD[10] inD[11] -+inD[12] inD[13] inD[14] inD[15] inD[16] inD[17] inD[18] inD[19] inD[1] -+inD[20] inD[21] inD[22] inD[23] inD[24] inD[25] inD[26] inD[27] inD[28] -+inD[29] inD[2] inD[30] inD[31] inD[32] inD[33] inD[34] inD[35] inD[36] -+inD[37] inD[3] inD[4] inD[5] inD[6] inD[7] inD[8] inD[9] outD[10] outD[11] -+outD[12] outD[13] outD[14] outD[15] outD[16] outD[17] outD[18] outD[19] -+outD[1] outD[20] outD[21] outD[22] outD[23] outD[24] outD[25] outD[26] -+outD[27] outD[28] outD[29] outD[2] outD[30] outD[31] outD[32] outD[33] -+outD[34] outD[35] outD[36] outD[37] outD[3] outD[4] outD[5] outD[6] outD[7] -+outD[8] outD[9] all1in52weak -XgaspWeak@0 net@0 predD sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sir[9] sor[8] succD gaspWeakDn -Xwire90@0 net@0 net@2 wire90-5130_5-layer_1-width_3 -.ENDS weakStageDn +Xwire90@0 net@8 net@10 wire90-602_3-layer_1-width_3 +Xwire90@1 net@30 fire wire90-602_3-layer_1-width_3 +.ENDS gaspWeak + +*** CELL: stagesM:weakStage{sch} +.SUBCKT weakStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] ++aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] ++aout[7] aout[8] aout[9] aout[TT] in[10] in[11] in[12] in[13] in[14] in[15] ++in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] ++in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] ++in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] ++out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] ++out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] ++out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] ++out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] pred sir[1] sir[2] ++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ +Xaddr1in2@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] ++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12] ++aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] ++aout[8] aout[9] aout[TT] net@59 addr1in20Bx15 +Xdata1in2@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] ++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] ++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3] ++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] ++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] ++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] ++out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] ++out[6] out[7] out[8] out[9] net@47 data1in20Bx37 +XgaspWeak@0 net@59 sir[9] pred net@39 succ net@47 ain[TT] gaspWeak +XscanEx1v@0 net@39 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx1vertA +.ENDS weakStage *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-1243_9-R_34_667m a b @@ -7400,175 +7729,175 @@ Rres@3 net@8 net@11 14.443 Xwire@0 a b wire-C_0_011f-1249_9-R_34_667m .ENDS wire90-1249_9-layer_1-width_3 -*** CELL: stageGroupsL:upDown8weak{sch} +*** CELL: stageGroupsM:upDown8weak{sch} .SUBCKT upDown8weak ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] -+ainD[2] ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[T] ++ainD[2] ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[TT] +ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2] ainU[3] ainU[4] -+ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[T] aoutD[10] aoutD[11] aoutD[12] -+aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] aoutD[5] aoutD[6] -+aoutD[7] aoutD[8] aoutD[9] aoutD[T] aoutU[10] aoutU[11] aoutU[12] aoutU[13] -+aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] aoutU[5] aoutU[6] aoutU[7] -+aoutU[8] aoutU[9] aoutU[T] inD[10] inD[11] inD[12] inD[13] inD[14] inD[15] -+inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22] inD[23] -+inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30] inD[31] -+inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5] inD[6] -+inD[7] inD[8] inD[9] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15] inU[16] -+inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23] inU[24] -+inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31] inU[32] -+inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6] inU[7] -+inU[8] inU[9] outD[10] outD[11] outD[12] outD[13] outD[14] outD[15] outD[16] -+outD[17] outD[18] outD[19] outD[1] outD[20] outD[21] outD[22] outD[23] -+outD[24] outD[25] outD[26] outD[27] outD[28] outD[29] outD[2] outD[30] -+outD[31] outD[32] outD[33] outD[34] outD[35] outD[36] outD[37] outD[3] -+outD[4] outD[5] outD[6] outD[7] outD[8] outD[9] outU[10] outU[11] outU[12] -+outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] outU[19] outU[1] -+outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] outU[26] outU[27] -+outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] outU[33] outU[34] -+outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7] outU[8] -+outU[9] predD predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] -+sir[9] sor[1] sor[8] succD succU -XweakStag@10 ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2] -+ainU[3] ainU[4] ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[T] net@111[4] -+net@111[3] net@111[2] net@111[1] net@111[0] net@111[13] net@111[12] -+net@111[11] net@111[10] net@111[9] net@111[8] net@111[7] net@111[6] -+net@111[5] net@111[14] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15] ++ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[TT] aoutD[10] aoutD[11] ++aoutD[12] aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] aoutD[5] ++aoutD[6] aoutD[7] aoutD[8] aoutD[9] aoutD[TT] aoutU[10] aoutU[11] aoutU[12] ++aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] aoutU[5] aoutU[6] ++aoutU[7] aoutU[8] aoutU[9] aoutU[TT] inD[10] inD[11] inD[12] inD[13] inD[14] ++inD[15] inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22] ++inD[23] inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30] ++inD[31] inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5] ++inD[6] inD[7] inD[8] inD[9] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15] ++inU[16] inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23] ++inU[24] inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31] ++inU[32] inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6] ++inU[7] inU[8] inU[9] outD[10] outD[11] outD[12] outD[13] outD[14] outD[15] ++outD[16] outD[17] outD[18] outD[19] outD[1] outD[20] outD[21] outD[22] ++outD[23] outD[24] outD[25] outD[26] outD[27] outD[28] outD[29] outD[2] ++outD[30] outD[31] outD[32] outD[33] outD[34] outD[35] outD[36] outD[37] ++outD[3] outD[4] outD[5] outD[6] outD[7] outD[8] outD[9] outU[10] outU[11] ++outU[12] outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] outU[19] ++outU[1] outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] outU[26] ++outU[27] outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] outU[33] ++outU[34] outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7] ++outU[8] outU[9] predD predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sir[9] sor[1] succD succU +XweakStag@18 ainU[10] ainU[11] ainU[12] ainU[13] ainU[14] ainU[1] ainU[2] ++ainU[3] ainU[4] ainU[5] ainU[6] ainU[7] ainU[8] ainU[9] ainU[TT] net@189[41] ++net@189[40] net@189[39] net@189[38] net@189[37] net@189[50] net@189[49] ++net@189[48] net@189[47] net@189[46] net@189[45] net@189[44] net@189[43] ++net@189[42] net@189[51] inU[10] inU[11] inU[12] inU[13] inU[14] inU[15] +inU[16] inU[17] inU[18] inU[19] inU[1] inU[20] inU[21] inU[22] inU[23] +inU[24] inU[25] inU[26] inU[27] inU[28] inU[29] inU[2] inU[30] inU[31] +inU[32] inU[33] inU[34] inU[35] inU[36] inU[37] inU[3] inU[4] inU[5] inU[6] -+inU[7] inU[8] inU[9] net@111[42] net@111[41] net@111[40] net@111[39] -+net@111[38] net@111[37] net@111[36] net@111[35] net@111[34] net@111[33] -+net@111[51] net@111[32] net@111[31] net@111[30] net@111[29] net@111[28] -+net@111[27] net@111[26] net@111[25] net@111[24] net@111[23] net@111[50] -+net@111[22] net@111[21] net@111[20] net@111[19] net@111[18] net@111[17] -+net@111[16] net@111[15] net@111[49] net@111[48] net@111[47] net@111[46] -+net@111[45] net@111[44] net@111[43] predU sir[1] sir[2] sir[3] sir[4] sir[5] -+sir[6] sir[7] sir[8] sir[9] net@117[8] net@28 weakStageUp -XweakStag@11 net@111[4] net@111[3] net@111[2] net@111[1] net@111[0] -+net@111[13] net@111[12] net@111[11] net@111[10] net@111[9] net@111[8] -+net@111[7] net@111[6] net@111[5] net@111[14] net@112[4] net@112[3] net@112[2] -+net@112[1] net@112[0] net@112[13] net@112[12] net@112[11] net@112[10] -+net@112[9] net@112[8] net@112[7] net@112[6] net@112[5] net@112[14] -+net@111[42] net@111[41] net@111[40] net@111[39] net@111[38] net@111[37] -+net@111[36] net@111[35] net@111[34] net@111[33] net@111[51] net@111[32] -+net@111[31] net@111[30] net@111[29] net@111[28] net@111[27] net@111[26] -+net@111[25] net@111[24] net@111[23] net@111[50] net@111[22] net@111[21] -+net@111[20] net@111[19] net@111[18] net@111[17] net@111[16] net@111[15] -+net@111[49] net@111[48] net@111[47] net@111[46] net@111[45] net@111[44] -+net@111[43] net@112[42] net@112[41] net@112[40] net@112[39] net@112[38] -+net@112[37] net@112[36] net@112[35] net@112[34] net@112[33] net@112[51] -+net@112[32] net@112[31] net@112[30] net@112[29] net@112[28] net@112[27] -+net@112[26] net@112[25] net@112[24] net@112[23] net@112[50] net@112[22] -+net@112[21] net@112[20] net@112[19] net@112[18] net@112[17] net@112[16] -+net@112[15] net@112[49] net@112[48] net@112[47] net@112[46] net@112[45] -+net@112[44] net@112[43] net@46 net@117[8] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] net@120[1] sir[9] net@123[8] net@62 weakStageUp -XweakStag@12 net@112[4] net@112[3] net@112[2] net@112[1] net@112[0] -+net@112[13] net@112[12] net@112[11] net@112[10] net@112[9] net@112[8] -+net@112[7] net@112[6] net@112[5] net@112[14] net@113[4] net@113[3] net@113[2] -+net@113[1] net@113[0] net@113[13] net@113[12] net@113[11] net@113[10] -+net@113[9] net@113[8] net@113[7] net@113[6] net@113[5] net@113[14] -+net@112[42] net@112[41] net@112[40] net@112[39] net@112[38] net@112[37] -+net@112[36] net@112[35] net@112[34] net@112[33] net@112[51] net@112[32] -+net@112[31] net@112[30] net@112[29] net@112[28] net@112[27] net@112[26] -+net@112[25] net@112[24] net@112[23] net@112[50] net@112[22] net@112[21] -+net@112[20] net@112[19] net@112[18] net@112[17] net@112[16] net@112[15] -+net@112[49] net@112[48] net@112[47] net@112[46] net@112[45] net@112[44] -+net@112[43] net@113[42] net@113[41] net@113[40] net@113[39] net@113[38] -+net@113[37] net@113[36] net@113[35] net@113[34] net@113[33] net@113[51] -+net@113[32] net@113[31] net@113[30] net@113[29] net@113[28] net@113[27] -+net@113[26] net@113[25] net@113[24] net@113[23] net@113[50] net@113[22] -+net@113[21] net@113[20] net@113[19] net@113[18] net@113[17] net@113[16] -+net@113[15] net@113[49] net@113[48] net@113[47] net@113[46] net@113[45] -+net@113[44] net@113[43] net@63 net@123[8] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] net@126[1] sir[9] net@129[8] net@64 weakStageUp -XweakStag@13 net@113[4] net@113[3] net@113[2] net@113[1] net@113[0] -+net@113[13] net@113[12] net@113[11] net@113[10] net@113[9] net@113[8] -+net@113[7] net@113[6] net@113[5] net@113[14] aoutU[10] aoutU[11] aoutU[12] ++inU[7] inU[8] inU[9] net@189[27] net@189[26] net@189[25] net@189[24] ++net@189[23] net@189[22] net@189[21] net@189[20] net@189[19] net@189[18] ++net@189[36] net@189[17] net@189[16] net@189[15] net@189[14] net@189[13] ++net@189[12] net@189[11] net@189[10] net@189[9] net@189[8] net@189[35] ++net@189[7] net@189[6] net@189[5] net@189[4] net@189[3] net@189[2] net@189[1] ++net@189[0] net@189[34] net@189[33] net@189[32] net@189[31] net@189[30] ++net@189[29] net@189[28] predU sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sir[9] net@117[8] net@28 weakStage +XweakStag@19 net@189[41] net@189[40] net@189[39] net@189[38] net@189[37] ++net@189[50] net@189[49] net@189[48] net@189[47] net@189[46] net@189[45] ++net@189[44] net@189[43] net@189[42] net@189[51] net@190[41] net@190[40] ++net@190[39] net@190[38] net@190[37] net@190[50] net@190[49] net@190[48] ++net@190[47] net@190[46] net@190[45] net@190[44] net@190[43] net@190[42] ++net@190[51] net@189[27] net@189[26] net@189[25] net@189[24] net@189[23] ++net@189[22] net@189[21] net@189[20] net@189[19] net@189[18] net@189[36] ++net@189[17] net@189[16] net@189[15] net@189[14] net@189[13] net@189[12] ++net@189[11] net@189[10] net@189[9] net@189[8] net@189[35] net@189[7] ++net@189[6] net@189[5] net@189[4] net@189[3] net@189[2] net@189[1] net@189[0] ++net@189[34] net@189[33] net@189[32] net@189[31] net@189[30] net@189[29] ++net@189[28] net@190[27] net@190[26] net@190[25] net@190[24] net@190[23] ++net@190[22] net@190[21] net@190[20] net@190[19] net@190[18] net@190[36] ++net@190[17] net@190[16] net@190[15] net@190[14] net@190[13] net@190[12] ++net@190[11] net@190[10] net@190[9] net@190[8] net@190[35] net@190[7] ++net@190[6] net@190[5] net@190[4] net@190[3] net@190[2] net@190[1] net@190[0] ++net@190[34] net@190[33] net@190[32] net@190[31] net@190[30] net@190[29] ++net@190[28] net@46 net@120[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sir[9] net@123[8] net@62 weakStage +XweakStag@20 net@190[41] net@190[40] net@190[39] net@190[38] net@190[37] ++net@190[50] net@190[49] net@190[48] net@190[47] net@190[46] net@190[45] ++net@190[44] net@190[43] net@190[42] net@190[51] net@191[41] net@191[40] ++net@191[39] net@191[38] net@191[37] net@191[50] net@191[49] net@191[48] ++net@191[47] net@191[46] net@191[45] net@191[44] net@191[43] net@191[42] ++net@191[51] net@190[27] net@190[26] net@190[25] net@190[24] net@190[23] ++net@190[22] net@190[21] net@190[20] net@190[19] net@190[18] net@190[36] ++net@190[17] net@190[16] net@190[15] net@190[14] net@190[13] net@190[12] ++net@190[11] net@190[10] net@190[9] net@190[8] net@190[35] net@190[7] ++net@190[6] net@190[5] net@190[4] net@190[3] net@190[2] net@190[1] net@190[0] ++net@190[34] net@190[33] net@190[32] net@190[31] net@190[30] net@190[29] ++net@190[28] net@191[27] net@191[26] net@191[25] net@191[24] net@191[23] ++net@191[22] net@191[21] net@191[20] net@191[19] net@191[18] net@191[36] ++net@191[17] net@191[16] net@191[15] net@191[14] net@191[13] net@191[12] ++net@191[11] net@191[10] net@191[9] net@191[8] net@191[35] net@191[7] ++net@191[6] net@191[5] net@191[4] net@191[3] net@191[2] net@191[1] net@191[0] ++net@191[34] net@191[33] net@191[32] net@191[31] net@191[30] net@191[29] ++net@191[28] net@63 net@126[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sir[9] net@129[8] net@64 weakStage +XweakStag@21 net@191[41] net@191[40] net@191[39] net@191[38] net@191[37] ++net@191[50] net@191[49] net@191[48] net@191[47] net@191[46] net@191[45] ++net@191[44] net@191[43] net@191[42] net@191[51] aoutU[10] aoutU[11] aoutU[12] +aoutU[13] aoutU[14] aoutU[1] aoutU[2] aoutU[3] aoutU[4] aoutU[5] aoutU[6] -+aoutU[7] aoutU[8] aoutU[9] aoutU[T] net@113[42] net@113[41] net@113[40] -+net@113[39] net@113[38] net@113[37] net@113[36] net@113[35] net@113[34] -+net@113[33] net@113[51] net@113[32] net@113[31] net@113[30] net@113[29] -+net@113[28] net@113[27] net@113[26] net@113[25] net@113[24] net@113[23] -+net@113[50] net@113[22] net@113[21] net@113[20] net@113[19] net@113[18] -+net@113[17] net@113[16] net@113[15] net@113[49] net@113[48] net@113[47] -+net@113[46] net@113[45] net@113[44] net@113[43] outU[10] outU[11] outU[12] -+outU[13] outU[14] outU[15] outU[16] outU[17] outU[18] outU[19] outU[1] -+outU[20] outU[21] outU[22] outU[23] outU[24] outU[25] outU[26] outU[27] -+outU[28] outU[29] outU[2] outU[30] outU[31] outU[32] outU[33] outU[34] -+outU[35] outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7] outU[8] -+outU[9] net@65 net@129[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+net@132[1] sir[9] sor[1] succU weakStageUp -XweakStag@14 net@104[4] net@104[3] net@104[2] net@104[1] net@104[0] -+net@104[13] net@104[12] net@104[11] net@104[10] net@104[9] net@104[8] -+net@104[7] net@104[6] net@104[5] net@104[14] aoutD[10] aoutD[11] aoutD[12] ++aoutU[7] aoutU[8] aoutU[9] aoutU[TT] net@191[27] net@191[26] net@191[25] ++net@191[24] net@191[23] net@191[22] net@191[21] net@191[20] net@191[19] ++net@191[18] net@191[36] net@191[17] net@191[16] net@191[15] net@191[14] ++net@191[13] net@191[12] net@191[11] net@191[10] net@191[9] net@191[8] ++net@191[35] net@191[7] net@191[6] net@191[5] net@191[4] net@191[3] net@191[2] ++net@191[1] net@191[0] net@191[34] net@191[33] net@191[32] net@191[31] ++net@191[30] net@191[29] net@191[28] outU[10] outU[11] outU[12] outU[13] ++outU[14] outU[15] outU[16] outU[17] outU[18] outU[19] outU[1] outU[20] ++outU[21] outU[22] outU[23] outU[24] outU[25] outU[26] outU[27] outU[28] ++outU[29] outU[2] outU[30] outU[31] outU[32] outU[33] outU[34] outU[35] ++outU[36] outU[37] outU[3] outU[4] outU[5] outU[6] outU[7] outU[8] outU[9] ++net@65 net@132[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] ++net@135[8] succU weakStage +XweakStag@22 net@192[41] net@192[40] net@192[39] net@192[38] net@192[37] ++net@192[50] net@192[49] net@192[48] net@192[47] net@192[46] net@192[45] ++net@192[44] net@192[43] net@192[42] net@192[51] aoutD[10] aoutD[11] aoutD[12] +aoutD[13] aoutD[14] aoutD[1] aoutD[2] aoutD[3] aoutD[4] aoutD[5] aoutD[6] -+aoutD[7] aoutD[8] aoutD[9] aoutD[T] net@104[42] net@104[41] net@104[40] -+net@104[39] net@104[38] net@104[37] net@104[36] net@104[35] net@104[34] -+net@104[33] net@104[51] net@104[32] net@104[31] net@104[30] net@104[29] -+net@104[28] net@104[27] net@104[26] net@104[25] net@104[24] net@104[23] -+net@104[50] net@104[22] net@104[21] net@104[20] net@104[19] net@104[18] -+net@104[17] net@104[16] net@104[15] net@104[49] net@104[48] net@104[47] -+net@104[46] net@104[45] net@104[44] net@104[43] outD[10] outD[11] outD[12] -+outD[13] outD[14] outD[15] outD[16] outD[17] outD[18] outD[19] outD[1] -+outD[20] outD[21] outD[22] outD[23] outD[24] outD[25] outD[26] outD[27] -+outD[28] outD[29] outD[2] outD[30] outD[31] outD[32] outD[33] outD[34] -+outD[35] outD[36] outD[37] outD[3] outD[4] outD[5] outD[6] outD[7] outD[8] -+outD[9] net@50 net@117[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] -+sir[9] net@120[1] succD weakStageDn -XweakStag@15 net@106[4] net@106[3] net@106[2] net@106[1] net@106[0] -+net@106[13] net@106[12] net@106[11] net@106[10] net@106[9] net@106[8] -+net@106[7] net@106[6] net@106[5] net@106[14] net@104[4] net@104[3] net@104[2] -+net@104[1] net@104[0] net@104[13] net@104[12] net@104[11] net@104[10] -+net@104[9] net@104[8] net@104[7] net@104[6] net@104[5] net@104[14] -+net@106[42] net@106[41] net@106[40] net@106[39] net@106[38] net@106[37] -+net@106[36] net@106[35] net@106[34] net@106[33] net@106[51] net@106[32] -+net@106[31] net@106[30] net@106[29] net@106[28] net@106[27] net@106[26] -+net@106[25] net@106[24] net@106[23] net@106[50] net@106[22] net@106[21] -+net@106[20] net@106[19] net@106[18] net@106[17] net@106[16] net@106[15] -+net@106[49] net@106[48] net@106[47] net@106[46] net@106[45] net@106[44] -+net@106[43] net@104[42] net@104[41] net@104[40] net@104[39] net@104[38] -+net@104[37] net@104[36] net@104[35] net@104[34] net@104[33] net@104[51] -+net@104[32] net@104[31] net@104[30] net@104[29] net@104[28] net@104[27] -+net@104[26] net@104[25] net@104[24] net@104[23] net@104[50] net@104[22] -+net@104[21] net@104[20] net@104[19] net@104[18] net@104[17] net@104[16] -+net@104[15] net@104[49] net@104[48] net@104[47] net@104[46] net@104[45] -+net@104[44] net@104[43] net@44 net@123[8] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] net@120[1] sir[9] net@126[1] net@51 weakStageDn -XweakStag@16 net@107[4] net@107[3] net@107[2] net@107[1] net@107[0] -+net@107[13] net@107[12] net@107[11] net@107[10] net@107[9] net@107[8] -+net@107[7] net@107[6] net@107[5] net@107[14] net@106[4] net@106[3] net@106[2] -+net@106[1] net@106[0] net@106[13] net@106[12] net@106[11] net@106[10] -+net@106[9] net@106[8] net@106[7] net@106[6] net@106[5] net@106[14] -+net@107[42] net@107[41] net@107[40] net@107[39] net@107[38] net@107[37] -+net@107[36] net@107[35] net@107[34] net@107[33] net@107[51] net@107[32] -+net@107[31] net@107[30] net@107[29] net@107[28] net@107[27] net@107[26] -+net@107[25] net@107[24] net@107[23] net@107[50] net@107[22] net@107[21] -+net@107[20] net@107[19] net@107[18] net@107[17] net@107[16] net@107[15] -+net@107[49] net@107[48] net@107[47] net@107[46] net@107[45] net@107[44] -+net@107[43] net@106[42] net@106[41] net@106[40] net@106[39] net@106[38] -+net@106[37] net@106[36] net@106[35] net@106[34] net@106[33] net@106[51] -+net@106[32] net@106[31] net@106[30] net@106[29] net@106[28] net@106[27] -+net@106[26] net@106[25] net@106[24] net@106[23] net@106[50] net@106[22] -+net@106[21] net@106[20] net@106[19] net@106[18] net@106[17] net@106[16] -+net@106[15] net@106[49] net@106[48] net@106[47] net@106[46] net@106[45] -+net@106[44] net@106[43] net@52 net@129[8] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] net@126[1] sir[9] net@132[1] net@43 weakStageDn -XweakStag@17 ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] ainD[2] -+ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[T] net@107[4] -+net@107[3] net@107[2] net@107[1] net@107[0] net@107[13] net@107[12] -+net@107[11] net@107[10] net@107[9] net@107[8] net@107[7] net@107[6] -+net@107[5] net@107[14] inD[10] inD[11] inD[12] inD[13] inD[14] inD[15] ++aoutD[7] aoutD[8] aoutD[9] aoutD[TT] net@192[27] net@192[26] net@192[25] ++net@192[24] net@192[23] net@192[22] net@192[21] net@192[20] net@192[19] ++net@192[18] net@192[36] net@192[17] net@192[16] net@192[15] net@192[14] ++net@192[13] net@192[12] net@192[11] net@192[10] net@192[9] net@192[8] ++net@192[35] net@192[7] net@192[6] net@192[5] net@192[4] net@192[3] net@192[2] ++net@192[1] net@192[0] net@192[34] net@192[33] net@192[32] net@192[31] ++net@192[30] net@192[29] net@192[28] outD[10] outD[11] outD[12] outD[13] ++outD[14] outD[15] outD[16] outD[17] outD[18] outD[19] outD[1] outD[20] ++outD[21] outD[22] outD[23] outD[24] outD[25] outD[26] outD[27] outD[28] ++outD[29] outD[2] outD[30] outD[31] outD[32] outD[33] outD[34] outD[35] ++outD[36] outD[37] outD[3] outD[4] outD[5] outD[6] outD[7] outD[8] outD[9] ++net@50 net@117[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] ++net@120[8] succD weakStage +XweakStag@23 net@193[41] net@193[40] net@193[39] net@193[38] net@193[37] ++net@193[50] net@193[49] net@193[48] net@193[47] net@193[46] net@193[45] ++net@193[44] net@193[43] net@193[42] net@193[51] net@192[41] net@192[40] ++net@192[39] net@192[38] net@192[37] net@192[50] net@192[49] net@192[48] ++net@192[47] net@192[46] net@192[45] net@192[44] net@192[43] net@192[42] ++net@192[51] net@193[27] net@193[26] net@193[25] net@193[24] net@193[23] ++net@193[22] net@193[21] net@193[20] net@193[19] net@193[18] net@193[36] ++net@193[17] net@193[16] net@193[15] net@193[14] net@193[13] net@193[12] ++net@193[11] net@193[10] net@193[9] net@193[8] net@193[35] net@193[7] ++net@193[6] net@193[5] net@193[4] net@193[3] net@193[2] net@193[1] net@193[0] ++net@193[34] net@193[33] net@193[32] net@193[31] net@193[30] net@193[29] ++net@193[28] net@192[27] net@192[26] net@192[25] net@192[24] net@192[23] ++net@192[22] net@192[21] net@192[20] net@192[19] net@192[18] net@192[36] ++net@192[17] net@192[16] net@192[15] net@192[14] net@192[13] net@192[12] ++net@192[11] net@192[10] net@192[9] net@192[8] net@192[35] net@192[7] ++net@192[6] net@192[5] net@192[4] net@192[3] net@192[2] net@192[1] net@192[0] ++net@192[34] net@192[33] net@192[32] net@192[31] net@192[30] net@192[29] ++net@192[28] net@44 net@123[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sir[9] net@126[8] net@51 weakStage +XweakStag@24 net@194[41] net@194[40] net@194[39] net@194[38] net@194[37] ++net@194[50] net@194[49] net@194[48] net@194[47] net@194[46] net@194[45] ++net@194[44] net@194[43] net@194[42] net@194[51] net@193[41] net@193[40] ++net@193[39] net@193[38] net@193[37] net@193[50] net@193[49] net@193[48] ++net@193[47] net@193[46] net@193[45] net@193[44] net@193[43] net@193[42] ++net@193[51] net@194[27] net@194[26] net@194[25] net@194[24] net@194[23] ++net@194[22] net@194[21] net@194[20] net@194[19] net@194[18] net@194[36] ++net@194[17] net@194[16] net@194[15] net@194[14] net@194[13] net@194[12] ++net@194[11] net@194[10] net@194[9] net@194[8] net@194[35] net@194[7] ++net@194[6] net@194[5] net@194[4] net@194[3] net@194[2] net@194[1] net@194[0] ++net@194[34] net@194[33] net@194[32] net@194[31] net@194[30] net@194[29] ++net@194[28] net@193[27] net@193[26] net@193[25] net@193[24] net@193[23] ++net@193[22] net@193[21] net@193[20] net@193[19] net@193[18] net@193[36] ++net@193[17] net@193[16] net@193[15] net@193[14] net@193[13] net@193[12] ++net@193[11] net@193[10] net@193[9] net@193[8] net@193[35] net@193[7] ++net@193[6] net@193[5] net@193[4] net@193[3] net@193[2] net@193[1] net@193[0] ++net@193[34] net@193[33] net@193[32] net@193[31] net@193[30] net@193[29] ++net@193[28] net@52 net@129[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sir[9] net@132[8] net@43 weakStage +XweakStag@25 ainD[10] ainD[11] ainD[12] ainD[13] ainD[14] ainD[1] ainD[2] ++ainD[3] ainD[4] ainD[5] ainD[6] ainD[7] ainD[8] ainD[9] ainD[TT] net@194[41] ++net@194[40] net@194[39] net@194[38] net@194[37] net@194[50] net@194[49] ++net@194[48] net@194[47] net@194[46] net@194[45] net@194[44] net@194[43] ++net@194[42] net@194[51] inD[10] inD[11] inD[12] inD[13] inD[14] inD[15] +inD[16] inD[17] inD[18] inD[19] inD[1] inD[20] inD[21] inD[22] inD[23] +inD[24] inD[25] inD[26] inD[27] inD[28] inD[29] inD[2] inD[30] inD[31] +inD[32] inD[33] inD[34] inD[35] inD[36] inD[37] inD[3] inD[4] inD[5] inD[6] -+inD[7] inD[8] inD[9] net@107[42] net@107[41] net@107[40] net@107[39] -+net@107[38] net@107[37] net@107[36] net@107[35] net@107[34] net@107[33] -+net@107[51] net@107[32] net@107[31] net@107[30] net@107[29] net@107[28] -+net@107[27] net@107[26] net@107[25] net@107[24] net@107[23] net@107[50] -+net@107[22] net@107[21] net@107[20] net@107[19] net@107[18] net@107[17] -+net@107[16] net@107[15] net@107[49] net@107[48] net@107[47] net@107[46] -+net@107[45] net@107[44] net@107[43] predD sor[1] sir[2] sir[3] sir[4] sir[5] -+sir[6] sir[7] net@132[1] sir[9] sor[8] net@53 weakStageDn ++inD[7] inD[8] inD[9] net@194[27] net@194[26] net@194[25] net@194[24] ++net@194[23] net@194[22] net@194[21] net@194[20] net@194[19] net@194[18] ++net@194[36] net@194[17] net@194[16] net@194[15] net@194[14] net@194[13] ++net@194[12] net@194[11] net@194[10] net@194[9] net@194[8] net@194[35] ++net@194[7] net@194[6] net@194[5] net@194[4] net@194[3] net@194[2] net@194[1] ++net@194[0] net@194[34] net@194[33] net@194[32] net@194[31] net@194[30] ++net@194[29] net@194[28] predD net@135[8] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sir[9] sor[1] net@53 weakStage Xwire90@1 net@44 net@43 wire90-1243_9-layer_1-width_3 Xwire90@2 net@28 net@46 wire90-1185_9-layer_1-width_3 Xwire90@3 net@62 net@63 wire90-1185_9-layer_1-width_3 @@ -7577,11 +7906,11 @@ Xwire90@5 net@50 net@51 wire90-1249_9-layer_1-width_3 Xwire90@6 net@52 net@53 wire90-1249_9-layer_1-width_3 .ENDS upDown8weak -*** CELL: stageGroupsL:northFifo{sch} +*** CELL: stageGroupsM:northFifo{sch} .SUBCKT northFifo ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] -+ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] ++ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] +aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] -+aout[7] aout[8] aout[9] aout[T] fin fout in[10] in[11] in[12] in[13] in[14] ++aout[7] aout[8] aout[9] aout[TT] fin fout in[10] in[11] in[12] in[13] in[14] +in[15] in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] +in[25] in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] +in[35] in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] @@ -7592,61 +7921,60 @@ Xwire90@6 net@52 net@53 wire90-1249_9-layer_1-width_3 +sic[2] sic[3] sic[4] sic[5] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] +sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[8] sir[9] +succ -XfillDrai@0 net@256[4] net@256[3] net@256[2] net@256[1] net@256[0] -+net@256[13] net@256[12] net@256[11] net@256[10] net@256[9] net@256[8] -+net@256[7] net@256[6] net@256[5] net@256[14] net@259[4] net@259[3] net@259[2] -+net@259[1] net@259[0] net@259[13] net@259[12] net@259[11] net@259[10] -+net@259[9] net@259[8] net@259[7] net@259[6] net@259[5] net@259[14] fin fout -+net@256[42] net@256[41] net@256[40] net@256[39] net@256[38] net@256[37] -+net@256[36] net@256[35] net@256[34] net@256[33] net@256[51] net@256[32] -+net@256[31] net@256[30] net@256[29] net@256[28] net@256[27] net@256[26] -+net@256[25] net@256[24] net@256[23] net@256[50] net@256[22] net@256[21] -+net@256[20] net@256[19] net@256[18] net@256[17] net@256[16] net@256[15] -+net@256[49] net@256[48] net@256[47] net@256[46] net@256[45] net@256[44] -+net@256[43] net@259[42] net@259[41] net@259[40] net@259[39] net@259[38] -+net@259[37] net@259[36] net@259[35] net@259[34] net@259[33] net@259[51] -+net@259[32] net@259[31] net@259[30] net@259[29] net@259[28] net@259[27] -+net@259[26] net@259[25] net@259[24] net@259[23] net@259[50] net@259[22] -+net@259[21] net@259[20] net@259[19] net@259[18] net@259[17] net@259[16] -+net@259[15] net@259[49] net@259[48] net@259[47] net@259[46] net@259[45] -+net@259[44] net@259[43] net@263 sic[1] sic[2] sic[3] sic[4] sic[5] sic[3] +XfillDrai@1 net@256[41] net@256[40] net@256[39] net@256[38] net@256[37] ++net@256[50] net@256[49] net@256[48] net@256[47] net@256[46] net@256[45] ++net@256[44] net@256[43] net@256[42] net@256[51] net@259[41] net@259[40] ++net@259[39] net@259[38] net@259[37] net@259[50] net@259[49] net@259[48] ++net@259[47] net@259[46] net@259[45] net@259[44] net@259[43] net@259[42] ++net@259[51] fin fout net@256[27] net@256[26] net@256[25] net@256[24] ++net@256[23] net@256[22] net@256[21] net@256[20] net@256[19] net@256[18] ++net@256[36] net@256[17] net@256[16] net@256[15] net@256[14] net@256[13] ++net@256[12] net@256[11] net@256[10] net@256[9] net@256[8] net@256[35] ++net@256[7] net@256[6] net@256[5] net@256[4] net@256[3] net@256[2] net@256[1] ++net@256[0] net@256[34] net@256[33] net@256[32] net@256[31] net@256[30] ++net@256[29] net@256[28] net@259[27] net@259[26] net@259[25] net@259[24] ++net@259[23] net@259[22] net@259[21] net@259[20] net@259[19] net@259[18] ++net@259[36] net@259[17] net@259[16] net@259[15] net@259[14] net@259[13] ++net@259[12] net@259[11] net@259[10] net@259[9] net@259[8] net@259[35] ++net@259[7] net@259[6] net@259[5] net@259[4] net@259[3] net@259[2] net@259[1] ++net@259[0] net@259[34] net@259[33] net@259[32] net@259[31] net@259[30] ++net@259[29] net@259[28] net@263 sic[1] sic[2] sic[3] sic[4] sic[5] sic[3] +sic[2] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] -+sid[9] net@254[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] net@254[1] sir[9] -+sic[8] sid[8] sid[7] sid[6] net@235[5] net@235[4] net@254[1] net@267 ++sid[9] net@254[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] sir[9] ++sic[8] sid[8] sid[7] sid[6] net@235[5] net@235[4] sir[8] net@267 +fillDrainCount -XscanCap@1 sic[8] sic[2] sic[3] sic[4] sic[5] sic[9] scanCap -XscanCap@2 sid[8] sid[7] sid[6] net@235[5] net@235[4] sid[9] scanCap -XscanCap@4 net@254[1] sir[2] sir[3] sir[4] sir[5] sir[9] scanCap -XupDown8w@1 net@259[4] net@259[3] net@259[2] net@259[1] net@259[0] -+net@259[13] net@259[12] net@259[11] net@259[10] net@259[9] net@259[8] -+net@259[7] net@259[6] net@259[5] net@259[14] ain[10] ain[11] ain[12] ain[13] -+ain[14] ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] -+aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] -+aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@256[4] net@256[3] -+net@256[2] net@256[1] net@256[0] net@256[13] net@256[12] net@256[11] -+net@256[10] net@256[9] net@256[8] net@256[7] net@256[6] net@256[5] -+net@256[14] net@259[42] net@259[41] net@259[40] net@259[39] net@259[38] -+net@259[37] net@259[36] net@259[35] net@259[34] net@259[33] net@259[51] -+net@259[32] net@259[31] net@259[30] net@259[29] net@259[28] net@259[27] -+net@259[26] net@259[25] net@259[24] net@259[23] net@259[50] net@259[22] -+net@259[21] net@259[20] net@259[19] net@259[18] net@259[17] net@259[16] -+net@259[15] net@259[49] net@259[48] net@259[47] net@259[46] net@259[45] -+net@259[44] net@259[43] in[10] in[11] in[12] in[13] in[14] in[15] in[16] +XscanCap@5 sid[8] sid[7] sid[6] net@235[5] net@235[4] sid[9] scanCap +XscanCap@6 sic[8] sic[2] sic[3] sic[4] sic[5] sic[9] scanCap +XscanCap@7 sir[8] sir[2] sir[3] sir[4] sir[5] sir[9] scanCap +XupDown8w@2 net@259[41] net@259[40] net@259[39] net@259[38] net@259[37] ++net@259[50] net@259[49] net@259[48] net@259[47] net@259[46] net@259[45] ++net@259[44] net@259[43] net@259[42] net@259[51] ain[10] ain[11] ain[12] ++ain[13] ain[14] ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ++ain[9] ain[TT] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] ++aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] net@256[41] ++net@256[40] net@256[39] net@256[38] net@256[37] net@256[50] net@256[49] ++net@256[48] net@256[47] net@256[46] net@256[45] net@256[44] net@256[43] ++net@256[42] net@256[51] net@259[27] net@259[26] net@259[25] net@259[24] ++net@259[23] net@259[22] net@259[21] net@259[20] net@259[19] net@259[18] ++net@259[36] net@259[17] net@259[16] net@259[15] net@259[14] net@259[13] ++net@259[12] net@259[11] net@259[10] net@259[9] net@259[8] net@259[35] ++net@259[7] net@259[6] net@259[5] net@259[4] net@259[3] net@259[2] net@259[1] ++net@259[0] net@259[34] net@259[33] net@259[32] net@259[31] net@259[30] ++net@259[29] net@259[28] in[10] in[11] in[12] in[13] in[14] in[15] in[16] +in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] +in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] +in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] +out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] out[20] +out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] out[29] +out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] -+out[4] out[5] out[6] out[7] out[8] out[9] net@256[42] net@256[41] net@256[40] -+net@256[39] net@256[38] net@256[37] net@256[36] net@256[35] net@256[34] -+net@256[33] net@256[51] net@256[32] net@256[31] net@256[30] net@256[29] -+net@256[28] net@256[27] net@256[26] net@256[25] net@256[24] net@256[23] -+net@256[50] net@256[22] net@256[21] net@256[20] net@256[19] net@256[18] -+net@256[17] net@256[16] net@256[15] net@256[49] net@256[48] net@256[47] -+net@256[46] net@256[45] net@256[44] net@256[43] net@229 pred sir[1] sir[2] -+sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] sir[9] net@254[8] net@254[1] succ -+net@264 upDown8weak ++out[4] out[5] out[6] out[7] out[8] out[9] net@256[27] net@256[26] net@256[25] ++net@256[24] net@256[23] net@256[22] net@256[21] net@256[20] net@256[19] ++net@256[18] net@256[36] net@256[17] net@256[16] net@256[15] net@256[14] ++net@256[13] net@256[12] net@256[11] net@256[10] net@256[9] net@256[8] ++net@256[35] net@256[7] net@256[6] net@256[5] net@256[4] net@256[3] net@256[2] ++net@256[1] net@256[0] net@256[34] net@256[33] net@256[32] net@256[31] ++net@256[30] net@256[29] net@256[28] net@229 pred sir[1] sir[2] sir[3] sir[4] ++sir[5] sir[3] sir[2] sir[8] sir[9] net@254[8] succ net@264 upDown8weak Xwire90@6 net@229 net@267 wire90-1185_9-layer_1-width_3 Xwire90@18 net@264 net@263 wire90-1185_9-layer_1-width_3 .ENDS northFifo @@ -7694,44 +8022,39 @@ Xwire90@4 net@134 net@104 wire90-1013_8-layer_1-width_3 Xwire90@5 net@143 net@138 wire90-472_4-layer_1-width_3 .ENDS ctrAND3in100LT -*** CELL: gaspL:gaspTap{sch} -.SUBCKT gaspTap fire pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] -+sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] -+soc[1] sor[1] succ[A] succ[B] -XctrAND3i@2 succ[B] succ[A] net@163 fire ctrAND3in100LT -Xinv@0 pred net@240 inv-X_5 -XpredDri2@0 fire net@104 pred predDri20wMC -XscanEx1v@0 pred sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertA -XscanFx2v@0 net@418 net@409 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] -+sic[8] sic[9] soc[1] scanFx2vert -XsucANDdr@3 net@409 fire succ[B] sucANDdri20 -XsucANDdr@6 net@418 fire succ[A] sucANDdri20 +*** CELL: gaspM:gaspTap{sch} +.SUBCKT gaspTap fire mc pred s[1] succ[A] succ[B] take to[A] to[B] tok +XctrAND3i@0 succ[A] succ[B] net@163 fire ctrAND3in100LT +XdataDriv@0 tok fire take dataDriver60 +Xinv@0 pred net@240 inv-X_10 +XinvI@0 net@240 s[1] inv-X_10 +XpredDri6@0 fire mc pred driversJ__predDri60wMC +XsucANDdr@2 to[A] fire succ[A] sucANDdri60 +XsucANDdr@3 to[B] fire succ[B] sucANDdri60 Xwire90@0 net@240 net@163 wire90-602_3-layer_1-width_3 -Xwire90@4 net@104 sir[9] wire90-602_3-layer_1-width_3 .ENDS gaspTap -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-5331_6-R_34_667m a b -Ccap@0 gnd net@14 19.549f -Ccap@1 gnd net@8 19.549f -Ccap@2 gnd net@11 19.549f -Rres@0 net@14 a 30.805 -Rres@1 net@11 net@14 61.61 -Rres@2 b net@8 30.805 -Rres@3 net@8 net@11 61.61 -.ENDS wire-C_0_011f-5331_6-R_34_667m +*** CELL: scanM:scanEx1{sch} +.SUBCKT scanEx1 dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] +XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanM__scanCellE +.ENDS scanEx1 -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-5331_6-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-5331_6-R_34_667m -.ENDS wire90-5331_6-layer_1-width_3 +*** CELL: scanM:scanFx2{sch} +.SUBCKT scanFx2 dout[1] dout[2] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] ++sic[7] sic[8] sic[9] soc[1] +XscanCell@3 dout[1] sic[9] sic[3] sic[2] sic[5] sic[1] net@30 sic[4] ++scanCellF +XscanCell@4 dout[2] sic[9] sic[3] sic[2] sic[5] net@32 soc[1] sic[4] ++scanCellF +Xwire90@0 net@30 net@32 wire90-297_6-layer_1-width_3 +.ENDS scanFx2 -*** CELL: stagesL:tapStage{sch} +*** CELL: stagesM:tapStage{sch} .SUBCKT tapStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] -+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] aout[12] ++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12] +aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] -+aout[8] aout[9] aout[T] in[10] in[11] in[12] in[13] in[14] in[15] in[16] ++aout[8] aout[9] aout[TT] in[10] in[11] in[12] in[13] in[14] in[15] in[16] +in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] +in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] +in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] @@ -7741,24 +8064,27 @@ Xwire@0 a b wire-C_0_011f-5331_6-R_34_667m +out[4] out[5] out[6] out[7] out[8] out[9] pred sic[1] sic[2] sic[3] sic[4] +sic[5] sic[6] sic[7] sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] +sir[7] sir[8] sir[9] soc[1] sor[1] succ[A] succ[B] -Xall1in52@3 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] -+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] aout[12] +Xaddr1in6@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] ++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[TT] aout[10] aout[11] aout[12] +aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] -+aout[8] aout[9] aout[T] net@2 in[10] in[11] in[12] in[13] in[14] in[15] -+in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] -+in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] -+in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] -+out[12] out[13] out[14] out[15] out[16] out[17] out[18] out[19] out[1] -+out[20] out[21] out[22] out[23] out[24] out[25] out[26] out[27] out[28] -+out[29] out[2] out[30] out[31] out[32] out[33] out[34] out[35] out[36] -+out[37] out[3] out[4] out[5] out[6] out[7] out[8] out[9] all1in52weak -XgaspSwit@0 net@0 pred sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] -+sic[8] sic[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] -+soc[1] sor[1] succ[A] succ[B] gaspTap -Xwire90@0 net@0 net@2 wire90-5331_6-layer_1-width_3 ++aout[8] aout[9] aout[TT] net@0 addr1in60Cx15 +Xdata1in6@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] ++in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] ++in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[37] in[3] ++in[4] in[5] in[6] in[7] in[8] in[9] out[10] out[11] out[12] out[13] out[14] ++out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] ++out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] ++out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] ++out[6] out[7] out[8] out[9] net@3 data1in60Cx37 +XgaspTap@0 net@0 sir[9] pred net@54 succ[A] succ[B] net@3 to[A] to[B] ain[TT] ++gaspTap +XscanEx1@0 net@54 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx1 +XscanFx2@0 to[A] to[B] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] ++sic[8] sic[9] soc[1] scanFx2 .ENDS tapStage -*** CELL: stageGroupsL:tapPropStop{sch} +*** CELL: stageGroupsM:tapPropStop{sch} .SUBCKT tapPropStop ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] +ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] aout[10] aout[11] +aout[12] aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] @@ -7773,48 +8099,48 @@ Xwire90@0 net@0 net@2 wire90-5331_6-layer_1-width_3 +sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] +sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] +sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] -+succ[A] succ[tap] ++succ[A] succ[B] Xinstruct@0 cin net@91 fin fout net@105[8] sod[2] sod[3] sod[4] sod[5] sid[6] +sid[7] sid[8] sid[9] sod[1] instructionCount -XproperSt@0 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] -+ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] net@107[4] net@107[3] -+net@107[2] net@107[1] net@107[0] net@107[13] net@107[12] net@107[11] -+net@107[10] net@107[9] net@107[8] net@107[7] net@107[6] net@107[5] -+net@107[14] net@91 properSt@0_fire in[10] in[11] in[12] in[13] in[14] in[15] +XproperSt@1 ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] ++ain[4] ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] net@107[41] net@107[40] ++net@107[39] net@107[38] net@107[37] net@107[50] net@107[49] net@107[48] ++net@107[47] net@107[46] net@107[45] net@107[44] net@107[43] net@107[42] ++net@107[51] net@91 properSt@1_fire in[10] in[11] in[12] in[13] in[14] in[15] +in[16] in[17] in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] +in[26] in[27] in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] -+in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] net@107[42] -+net@107[41] net@107[40] net@107[39] net@107[38] net@107[37] net@107[36] -+net@107[35] net@107[34] net@107[33] net@107[51] net@107[32] net@107[31] -+net@107[30] net@107[29] net@107[28] net@107[27] net@107[26] net@107[25] -+net@107[24] net@107[23] net@107[50] net@107[22] net@107[21] net@107[20] -+net@107[19] net@107[18] net@107[17] net@107[16] net@107[15] net@107[49] -+net@107[48] net@107[47] net@107[46] net@107[45] net@107[44] net@107[43] pred -+sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] -+sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] -+sir[5] sir[6] sir[7] sir[8] sir[9] net@100[8] net@105[8] sod[2] sod[3] sod[4] -+sod[5] net@101[8] net@98 properStopper -XtapStage@1 net@107[4] net@107[3] net@107[2] net@107[1] net@107[0] -+net@107[13] net@107[12] net@107[11] net@107[10] net@107[9] net@107[8] -+net@107[7] net@107[6] net@107[5] net@107[14] aout[10] aout[11] aout[12] ++in[36] in[37] in[3] in[4] in[5] in[6] in[7] in[8] in[9] net@107[27] ++net@107[26] net@107[25] net@107[24] net@107[23] net@107[22] net@107[21] ++net@107[20] net@107[19] net@107[18] net@107[36] net@107[17] net@107[16] ++net@107[15] net@107[14] net@107[13] net@107[12] net@107[11] net@107[10] ++net@107[9] net@107[8] net@107[35] net@107[7] net@107[6] net@107[5] net@107[4] ++net@107[3] net@107[2] net@107[1] net@107[0] net@107[34] net@107[33] ++net@107[32] net@107[31] net@107[30] net@107[29] net@107[28] pred sic[1] ++sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] ++sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sir[9] net@100[8] net@105[8] sod[2] sod[3] sod[4] sod[5] ++net@101[8] net@98 properStopper +XtapStage@2 net@107[41] net@107[40] net@107[39] net@107[38] net@107[37] ++net@107[50] net@107[49] net@107[48] net@107[47] net@107[46] net@107[45] ++net@107[44] net@107[43] net@107[42] net@107[51] aout[10] aout[11] aout[12] +aout[13] aout[14] aout[1] aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] -+aout[8] aout[9] aout[T] net@107[42] net@107[41] net@107[40] net@107[39] -+net@107[38] net@107[37] net@107[36] net@107[35] net@107[34] net@107[33] -+net@107[51] net@107[32] net@107[31] net@107[30] net@107[29] net@107[28] -+net@107[27] net@107[26] net@107[25] net@107[24] net@107[23] net@107[50] -+net@107[22] net@107[21] net@107[20] net@107[19] net@107[18] net@107[17] -+net@107[16] net@107[15] net@107[49] net@107[48] net@107[47] net@107[46] -+net@107[45] net@107[44] net@107[43] out[10] out[11] out[12] out[13] out[14] -+out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] -+out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] -+out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] -+out[6] out[7] out[8] out[9] net@85 net@100[8] sic[2] sic[3] sic[4] sic[5] -+sic[6] sic[7] sic[8] sic[9] net@101[8] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sir[9] soc[1] sor[1] succ[A] succ[tap] tapStage ++aout[8] aout[9] aout[T] net@107[27] net@107[26] net@107[25] net@107[24] ++net@107[23] net@107[22] net@107[21] net@107[20] net@107[19] net@107[18] ++net@107[36] net@107[17] net@107[16] net@107[15] net@107[14] net@107[13] ++net@107[12] net@107[11] net@107[10] net@107[9] net@107[8] net@107[35] ++net@107[7] net@107[6] net@107[5] net@107[4] net@107[3] net@107[2] net@107[1] ++net@107[0] net@107[34] net@107[33] net@107[32] net@107[31] net@107[30] ++net@107[29] net@107[28] out[10] out[11] out[12] out[13] out[14] out[15] ++out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] ++out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] ++out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] ++out[7] out[8] out[9] net@85 net@100[8] sic[2] sic[3] sic[4] sic[5] sic[6] ++sic[7] sic[8] sic[9] net@101[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sir[9] soc[1] sor[1] succ[A] succ[B] tapStage Xwire90@2 net@98 net@85 wire90-2080_4-layer_1-width_3 .ENDS tapPropStop -*** CELL: stageGroupsL:southFifo{sch} +*** CELL: stageGroupsM:southFifo{sch} .SUBCKT southFifo aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] +aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] cin +fin fout out[10] out[11] out[12] out[13] out[14] out[15] out[16] out[17] @@ -7824,62 +8150,82 @@ Xwire90@2 net@98 net@85 wire90-2080_4-layer_1-width_3 +out[9] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] sic[7] sic[8] sic[9] sid[1] +sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] +sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] soc[1] sod[1] sod[2] sod[3] sod[4] -+sod[5] sor[1] sor[8] succ[tap] -XtapPropS@0 net@43[4] net@43[3] net@43[2] net@43[1] net@43[0] net@43[13] -+net@43[12] net@43[11] net@43[10] net@43[9] net@43[8] net@43[7] net@43[6] -+net@43[5] net@43[14] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] ++sod[5] sor[1] succ[tap] +XtapPropS@1 net@43[41] net@43[40] net@43[39] net@43[38] net@43[37] net@43[50] ++net@43[49] net@43[48] net@43[47] net@43[46] net@43[45] net@43[44] net@43[43] ++net@43[42] net@43[51] aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] +aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] cin -+fin fout net@43[42] net@43[41] net@43[40] net@43[39] net@43[38] net@43[37] -+net@43[36] net@43[35] net@43[34] net@43[33] net@43[51] net@43[32] net@43[31] -+net@43[30] net@43[29] net@43[28] net@43[27] net@43[26] net@43[25] net@43[24] -+net@43[23] net@43[50] net@43[22] net@43[21] net@43[20] net@43[19] net@43[18] -+net@43[17] net@43[16] net@43[15] net@43[49] net@43[48] net@43[47] net@43[46] -+net@43[45] net@43[44] net@43[43] out[10] out[11] out[12] out[13] out[14] ++fin fout net@43[27] net@43[26] net@43[25] net@43[24] net@43[23] net@43[22] ++net@43[21] net@43[20] net@43[19] net@43[18] net@43[36] net@43[17] net@43[16] ++net@43[15] net@43[14] net@43[13] net@43[12] net@43[11] net@43[10] net@43[9] ++net@43[8] net@43[35] net@43[7] net@43[6] net@43[5] net@43[4] net@43[3] ++net@43[2] net@43[1] net@43[0] net@43[34] net@43[33] net@43[32] net@43[31] ++net@43[30] net@43[29] net@43[28] out[10] out[11] out[12] out[13] out[14] +out[15] out[16] out[17] out[18] out[19] out[1] out[20] out[21] out[22] +out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] +out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] +out[6] out[7] out[8] out[9] net@61 sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] +sic[7] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] -+sid[9] net@64[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sor[8] sir[9] ++sid[9] net@64[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] +soc[1] sod[1] sod[2] sod[3] sod[4] sod[5] sor[1] net@53 succ[tap] tapPropStop -XupDown8w@0 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] -+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@50[4] -+net@50[3] net@50[2] net@50[1] net@50[0] net@50[13] net@50[12] net@50[11] -+net@50[10] net@50[9] net@50[8] net@50[7] net@50[6] net@50[5] net@50[14] -+net@50[4] net@50[3] net@50[2] net@50[1] net@50[0] net@50[13] net@50[12] -+net@50[11] net@50[10] net@50[9] net@50[8] net@50[7] net@50[6] net@50[5] -+net@50[14] net@43[4] net@43[3] net@43[2] net@43[1] net@43[0] net@43[13] -+net@43[12] net@43[11] net@43[10] net@43[9] net@43[8] net@43[7] net@43[6] -+net@43[5] net@43[14] out[10] out[11] out[12] out[13] out[14] out[15] out[16] +XupDown8w@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] ++aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@50[41] ++net@50[40] net@50[39] net@50[38] net@50[37] net@50[50] net@50[49] net@50[48] ++net@50[47] net@50[46] net@50[45] net@50[44] net@50[43] net@50[42] net@50[51] ++net@50[41] net@50[40] net@50[39] net@50[38] net@50[37] net@50[50] net@50[49] ++net@50[48] net@50[47] net@50[46] net@50[45] net@50[44] net@50[43] net@50[42] ++net@50[51] net@43[41] net@43[40] net@43[39] net@43[38] net@43[37] net@43[50] ++net@43[49] net@43[48] net@43[47] net@43[46] net@43[45] net@43[44] net@43[43] ++net@43[42] net@43[51] out[10] out[11] out[12] out[13] out[14] out[15] out[16] +out[17] out[18] out[19] out[1] out[20] out[21] out[22] out[23] out[24] +out[25] out[26] out[27] out[28] out[29] out[2] out[30] out[31] out[32] +out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] out[6] out[7] -+out[8] out[9] net@50[42] net@50[41] net@50[40] net@50[39] net@50[38] -+net@50[37] net@50[36] net@50[35] net@50[34] net@50[33] net@50[51] net@50[32] ++out[8] out[9] net@50[27] net@50[26] net@50[25] net@50[24] net@50[23] ++net@50[22] net@50[21] net@50[20] net@50[19] net@50[18] net@50[36] net@50[17] ++net@50[16] net@50[15] net@50[14] net@50[13] net@50[12] net@50[11] net@50[10] ++net@50[9] net@50[8] net@50[35] net@50[7] net@50[6] net@50[5] net@50[4] ++net@50[3] net@50[2] net@50[1] net@50[0] net@50[34] net@50[33] net@50[32] +net@50[31] net@50[30] net@50[29] net@50[28] net@50[27] net@50[26] net@50[25] -+net@50[24] net@50[23] net@50[50] net@50[22] net@50[21] net@50[20] net@50[19] -+net@50[18] net@50[17] net@50[16] net@50[15] net@50[49] net@50[48] net@50[47] -+net@50[46] net@50[45] net@50[44] net@50[43] net@50[42] net@50[41] net@50[40] -+net@50[39] net@50[38] net@50[37] net@50[36] net@50[35] net@50[34] net@50[33] -+net@50[51] net@50[32] net@50[31] net@50[30] net@50[29] net@50[28] net@50[27] -+net@50[26] net@50[25] net@50[24] net@50[23] net@50[50] net@50[22] net@50[21] -+net@50[20] net@50[19] net@50[18] net@50[17] net@50[16] net@50[15] net@50[49] -+net@50[48] net@50[47] net@50[46] net@50[45] net@50[44] net@50[43] net@43[42] -+net@43[41] net@43[40] net@43[39] net@43[38] net@43[37] net@43[36] net@43[35] -+net@43[34] net@43[33] net@43[51] net@43[32] net@43[31] net@43[30] net@43[29] -+net@43[28] net@43[27] net@43[26] net@43[25] net@43[24] net@43[23] net@43[50] -+net@43[22] net@43[21] net@43[20] net@43[19] net@43[18] net@43[17] net@43[16] -+net@43[15] net@43[49] net@43[48] net@43[47] net@43[46] net@43[45] net@43[44] -+net@43[43] net@53 net@58 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sir[9] net@64[8] sor[8] net@58 net@61 upDown8weak ++net@50[24] net@50[23] net@50[22] net@50[21] net@50[20] net@50[19] net@50[18] ++net@50[36] net@50[17] net@50[16] net@50[15] net@50[14] net@50[13] net@50[12] ++net@50[11] net@50[10] net@50[9] net@50[8] net@50[35] net@50[7] net@50[6] ++net@50[5] net@50[4] net@50[3] net@50[2] net@50[1] net@50[0] net@50[34] ++net@50[33] net@50[32] net@50[31] net@50[30] net@50[29] net@50[28] net@43[27] ++net@43[26] net@43[25] net@43[24] net@43[23] net@43[22] net@43[21] net@43[20] ++net@43[19] net@43[18] net@43[36] net@43[17] net@43[16] net@43[15] net@43[14] ++net@43[13] net@43[12] net@43[11] net@43[10] net@43[9] net@43[8] net@43[35] ++net@43[7] net@43[6] net@43[5] net@43[4] net@43[3] net@43[2] net@43[1] ++net@43[0] net@43[34] net@43[33] net@43[32] net@43[31] net@43[30] net@43[29] ++net@43[28] net@53 net@58 sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sir[9] net@64[8] net@58 net@61 upDown8weak .ENDS southFifo +*** CELL: gaspL:aStage{sch} +.SUBCKT gaspL__aStage fire mc pred s[1] succ +XctrAND2i@4 net@494 succ fire ctrAND2in30 +Xinv@4 net@987 s[1] inv-X_10 +Xinv@5 pred net@987 inv-X_5 +XpredDri2@1 fire mc pred predDri20wMC +XsucDri20@1 fire succ sucDri20 +Xwire90@0 net@987 net@494 wire90-291_8-layer_1-width_3 +.ENDS gaspL__aStage + +*** CELL: scanJ:scanEx3hor{sch} +.SUBCKT scanEx3hor dIn[1] dIn[2] dIn[3] mc sir[1] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sor[1] +XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanJ__scanCellE +XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanJ__scanCellE +XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sor[1] scanJ__scanCellE +Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3 +Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3 +.ENDS scanEx3hor + *** CELL: fifoL:tokenFIFO{sch} .SUBCKT tokenFIFO pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] +sir[8] sir[9] sor[1] succ -XaStage@0 aStage@0_fire sir[9] pred s[1] net@0 aStage -XaStage@1 aStage@1_fire sir[9] net@1 s[2] net@2 aStage -XaStage@2 aStage@2_fire sir[9] net@3 s[3] succ aStage +XaStage@0 aStage@0_fire sir[9] pred s[1] net@0 gaspL__aStage +XaStage@1 aStage@1_fire sir[9] net@1 s[2] net@2 gaspL__aStage +XaStage@2 aStage@2_fire sir[9] net@3 s[3] succ gaspL__aStage XscanEx3h@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] +sir[7] sir[8] sor[1] scanEx3hor Xwire90@0 net@0 net@1 wire90-291_8-layer_1-width_3 @@ -7889,57 +8235,51 @@ Xwire90@1 net@2 net@3 wire90-291_8-layer_1-width_3 .global gnd vdd *** TOP LEVEL CELL: marina{sch} -XdataPath@0 dinA[10] dinA[11] dinA[12] dinA[13] dinA[14] dinA[1] dinA[2] -+dinA[3] dinA[4] dinA[5] dinA[6] dinA[7] dinA[8] dinA[9] doutA[10] doutA[11] -+doutA[12] doutA[13] doutA[14] doutA[1] doutA[2] doutA[3] doutA[4] doutA[5] -+doutA[6] doutA[7] doutA[8] doutA[9] net@43 dinD[10] dinD[11] dinD[12] -+dinD[13] dinD[14] dinD[15] dinD[16] dinD[17] dinD[18] dinD[19] dinD[1] -+dinD[20] dinD[21] dinD[22] dinD[23] dinD[24] dinD[25] dinD[26] dinD[27] -+dinD[28] dinD[29] dinD[2] dinD[30] dinD[31] dinD[32] dinD[33] dinD[34] -+dinD[35] dinD[36] dinD[37] dinD[3] dinD[4] dinD[5] dinD[6] dinD[7] dinD[8] -+dinD[9] dinD[T] instrD[10] instrD[11] instrD[12] instrD[13] instrD[14] -+instrD[15] instrD[16] instrD[17] instrD[18] instrD[19] instrD[1] instrD[20] -+instrD[21] instrD[22] instrD[23] instrD[24] instrD[25] instrD[26] instrD[27] -+instrD[28] instrD[29] instrD[2] instrD[30] instrD[31] instrD[32] instrD[33] -+instrD[34] instrD[35] instrD[36] instrD[3] instrD[4] instrD[5] instrD[6] -+instrD[7] instrD[8] instrD[9] instrA[T] doutD[10] doutD[11] doutD[12] -+doutD[13] doutD[14] doutD[15] doutD[16] doutD[17] doutD[18] doutD[19] -+doutD[1] doutD[20] doutD[21] doutD[22] doutD[23] doutD[24] doutD[25] -+doutD[26] doutD[27] doutD[28] doutD[29] doutD[2] doutD[30] doutD[31] -+doutD[32] doutD[33] doutD[34] doutD[35] doutD[36] doutD[37] doutD[3] doutD[4] -+doutD[5] doutD[6] doutD[7] doutD[8] doutD[9] doutD[T] net@14 doo[D] doo[T] -+net@107[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] net@107[1] sir[9] -+dinA[14] net@108[8] sir[7] sir[6] net@108[4] net@108[0] ddo[D] ddo[T] -+dataPath -XnorthFif@0 doutA[10] doutA[11] doutA[12] doutA[13] doutA[14] doutA[1] +XinputDoc@1 doutA[10] doutA[11] doutA[12] doutA[13] doutA[14] doutA[1] +doutA[2] doutA[3] doutA[4] doutA[5] doutA[6] doutA[7] doutA[8] doutA[9] -+doutD[T] dinA[10] dinA[11] dinA[12] dinA[13] dinA[14] dinA[1] dinA[2] dinA[3] -+dinA[4] dinA[5] dinA[6] dinA[7] dinA[8] dinA[9] dinD[T] net@38 fout doutD[10] -+doutD[11] doutD[12] doutD[13] doutD[14] doutD[15] doutD[16] doutD[17] -+doutD[18] doutD[19] doutD[1] doutD[20] doutD[21] doutD[22] doutD[23] -+doutD[24] doutD[25] doutD[26] doutD[27] doutD[28] doutD[29] doutD[2] -+doutD[30] doutD[31] doutD[32] doutD[33] doutD[34] doutD[35] doutD[36] -+doutD[37] doutD[3] doutD[4] doutD[5] doutD[6] doutD[7] doutD[8] doutD[9] -+dinD[10] dinD[11] dinD[12] dinD[13] dinD[14] dinD[15] dinD[16] dinD[17] -+dinD[18] dinD[19] dinD[1] dinD[20] dinD[21] dinD[22] dinD[23] dinD[24] -+dinD[25] dinD[26] dinD[27] dinD[28] dinD[29] dinD[2] dinD[30] dinD[31] -+dinD[32] dinD[33] dinD[34] dinD[35] dinD[36] dinD[37] dinD[3] dinD[4] dinD[5] -+dinD[6] dinD[7] dinD[8] dinD[9] ddo[D] net@116[8] sic[2] sic[3] sic[4] sic[5] -+sic[8] sic[9] net@117[8] net@117[7] net@117[6] net@117[5] net@117[4] sid[6] -+sid[7] sid[8] sid[9] net@109[8] sir[7] sir[6] sir[4] net@108[4] net@107[1] -+net@108[0] doo[D] northFifo -XsouthFif@0 instrA[10] instrA[11] instrA[12] instrA[13] instrA[14] instrA[1] -+instrA[2] instrA[3] instrA[4] instrA[5] instrA[6] instrA[7] instrA[8] -+instrA[9] instrA[T] net@43 fin net@38 instrD[10] instrD[11] instrD[12] -+instrD[13] instrD[14] instrD[15] instrD[16] instrD[17] instrD[18] instrD[19] -+instrD[1] instrD[20] instrD[21] instrD[22] instrD[23] instrD[24] instrD[25] -+instrD[26] instrD[27] instrD[28] instrD[29] instrD[2] instrD[30] instrD[31] -+instrD[32] instrD[33] instrD[34] instrD[35] instrD[36] instrD[37] instrD[3] -+instrD[4] instrD[5] instrD[6] instrD[7] instrD[8] instrD[9] sic[1] sic[2] -+sic[3] sic[4] sic[5] sic[3] sic[2] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] -+sid[5] sid[6] sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sir[9] net@116[8] net@117[8] net@117[7] net@117[6] net@117[5] -+net@117[4] net@107[8] net@107[1] net@14 southFifo -XtokenFIF@0 ddo[T] net@108[8] sir[7] sir[6] sir[4] net@108[4] sir[6] sir[7] -+net@107[1] net@108[0] net@109[8] doo[T] tokenFIFO ++doutA[TT] net@43 din[10] din[11] din[12] din[13] din[14] din[15] din[16] ++din[17] din[18] din[19] din[1] din[20] din[21] din[22] din[23] din[24] ++din[25] din[26] din[27] din[28] din[29] din[2] din[30] din[31] din[32] ++din[33] din[34] din[35] din[36] din[37] din[3] din[4] din[5] din[6] din[7] ++din[8] din[9] ain[6] iout[10] iout[11] iout[12] iout[13] iout[14] iout[15] ++iout[16] iout[17] iout[18] iout[19] iout[1] iout[20] iout[21] iout[22] ++iout[23] iout[24] iout[25] iout[26] iout[27] iout[28] iout[29] iout[2] ++iout[30] iout[31] iout[32] iout[33] iout[34] iout[35] iout[36] iout[3] ++iout[4] iout[5] iout[6] iout[7] iout[8] iout[9] aout[T] doutD[10] doutD[11] ++doutD[12] doutD[13] doutD[14] doutD[15] doutD[16] doutD[17] doutD[18] ++doutD[19] doutD[1] doutD[20] doutD[21] doutD[22] doutD[23] doutD[24] ++doutD[25] doutD[26] doutD[27] doutD[28] doutD[29] doutD[2] doutD[30] ++doutD[31] doutD[32] doutD[33] doutD[34] doutD[35] doutD[36] doutD[37] ++doutD[3] doutD[4] doutD[5] doutD[6] doutD[7] doutD[8] doutD[9] net@14 doo[T] ++doo[D] ain[14] net@107[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] ++sir[9] net@108[8] ddo[T] ddo[D] inputDock +XnorthFif@1 doutA[10] doutA[11] doutA[12] doutA[13] doutA[14] doutA[1] ++doutA[2] doutA[3] doutA[4] doutA[5] doutA[6] doutA[7] doutA[8] doutA[9] ++doutA[TT] ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] ain[3] ain[4] ++ain[5] ain[6] ain[7] ain[8] ain[9] ain[T] net@38 fout doutD[10] doutD[11] ++doutD[12] doutD[13] doutD[14] doutD[15] doutD[16] doutD[17] doutD[18] ++doutD[19] doutD[1] doutD[20] doutD[21] doutD[22] doutD[23] doutD[24] ++doutD[25] doutD[26] doutD[27] doutD[28] doutD[29] doutD[2] doutD[30] ++doutD[31] doutD[32] doutD[33] doutD[34] doutD[35] doutD[36] doutD[37] ++doutD[3] doutD[4] doutD[5] doutD[6] doutD[7] doutD[8] doutD[9] din[10] ++din[11] din[12] din[13] din[14] din[15] din[16] din[17] din[18] din[19] ++din[1] din[20] din[21] din[22] din[23] din[24] din[25] din[26] din[27] ++din[28] din[29] din[2] din[30] din[31] din[32] din[33] din[34] din[35] ++din[36] din[37] din[3] din[4] din[5] din[6] din[7] din[8] din[9] ddo[D] ++net@116[8] sic[2] sic[3] sic[4] sic[5] sic[8] sic[9] net@117[8] net@117[7] ++net@117[6] net@117[5] net@117[4] sid[6] sid[7] sid[8] sid[9] net@109[8] ++sir[2] sir[3] sir[4] sir[5] sir[8] sir[9] doo[D] northFifo +XsouthFif@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] ++aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[T] net@43 fin ++net@38 iout[10] iout[11] iout[12] iout[13] iout[14] iout[15] iout[16] ++iout[17] iout[18] iout[19] iout[1] iout[20] iout[21] iout[22] iout[23] ++iout[24] iout[25] iout[26] iout[27] iout[28] iout[29] iout[2] iout[30] ++iout[31] iout[32] iout[33] iout[34] iout[35] iout[36] iout[37] iout[3] ++iout[4] iout[5] iout[6] iout[7] iout[8] iout[9] sic[1] sic[2] sic[3] sic[4] ++sic[5] sic[3] sic[2] sic[8] sic[9] sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] ++sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] ++sir[9] net@116[8] net@117[8] net@117[7] net@117[6] net@117[5] net@117[4] ++net@107[8] net@14 southFifo +XtokenFIF@0 ddo[T] net@108[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] ++sir[8] sir[9] net@109[8] doo[T] tokenFIFO .END