From: Adam Megacz <adam.megacz@sun.com>
Date: Mon, 4 May 2009 20:50:55 +0000 (+0000)
Subject: new files from ivan, test updates
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=d2c57c5c995cd4f885e127fcf13f879be8229e28;p=fleet.git

new files from ivan, test updates
---

diff --git a/testCode/com/sun/vlsi/chips/marina/test/Marina.java b/testCode/com/sun/vlsi/chips/marina/test/Marina.java
index cdcd7a7..ce76f93 100644
--- a/testCode/com/sun/vlsi/chips/marina/test/Marina.java
+++ b/testCode/com/sun/vlsi/chips/marina/test/Marina.java
@@ -165,13 +165,8 @@ public class Marina {
                     vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.\\inLO["+i+"]", (i==1)?0:1);
             }
 
-            // pulse ilc[load] and olc[load]
-            vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_", 1);
-            vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_", 1);
             vm.setNodeState("northFif@1.upDown8w@2.weakStag@22.addr1in2@0.fire", 1);
             model.waitNS(1000);
-            vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_", 0);
-            vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_", 0);
             vm.setNodeState("northFif@1.upDown8w@2.weakStag@22.addr1in2@0.fire", 0);
             model.waitNS(1000);
 
@@ -184,6 +179,13 @@ public class Marina {
             vm.setNodeState("sir[9]", 0);
             model.waitNS(1000);
 
+            // pulse ilc[load] and olc[load]
+            vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_", 1);
+            vm.setNodeState("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_", 1);
+            model.waitNS(100);
+            vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_");
+            vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_");
+
             vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_A__set_");
             vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_A__clr_");
             vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.flag_B__set_");
@@ -202,13 +204,11 @@ public class Marina {
             vm.releaseNode("northFif@1.upDown8w@2.weakStag@22.ain["+(INDEX_OF_ADDRESS_BIT_COPIED_TO_C_FLAG_WHEN_DC_EQUALS_ZERO+1)+"]");
             vm.releaseNode("northFif@1.upDown8w@2.weakStag@22.addr1in2@0.fire");
 
-            vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.ilc_load_");
             for(int i=1; i<=8; i++) {
                 if (i!=7)
                     vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.ilcMoveO@0.ilc@0.\\inLO["+i+"] ");
             }
             model.waitNS(1000);
-            vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.olc_load_");
             for(int i=1; i<=6; i++)
                 vm.releaseNode("outputDo@0.outM1Pre@0.outDockP@0.outDockC@0.olcWcont@0.olc@0.inLO["+i+"]");
 
diff --git a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
index f7bc75d..27f9522 100644
--- a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
+++ b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java
@@ -112,6 +112,9 @@ public class MarinaTest {
     private CmdArgs cmdArgs;
     private PowerChannel corePowerSupply, padsPowerSupply;
     private VoltageReadable coreVoltmeter, voltmeterForCurrent;
+
+    private ChainTest ctD, ctR, ctC;
+    private ChainControl ccD, ccR, ccC;
         
     //--------------------------  private methods -----------------------------
     /** @return true if simulation. Return false if we're testing silicon. */
@@ -218,6 +221,9 @@ public class MarinaTest {
                 return;
         }
         model = cmdArgs.useVerilog ? new VerilogModel() : new NanosimModel();
+
+        ((SimulationModel)model).setOptimizedDirectReadsWrites(true);
+
         CYCLE_TIME_NS = cmdArgs.useVerilog ? (100*20) : 0.250;
 
         //tester = ((SimulationModel)model).createJtagTester("TCK", "TMS", "TRSTb", "TDI", "TDO");
@@ -230,7 +236,6 @@ public class MarinaTest {
 
         int khz   = model instanceof VerilogModel ?  100000 : 1000000;
         
-        ChainControl ccD, ccR, ccC;
         ccD = new ChainControl(SCAN_CHAIN_XML, testerD, 1.8f, khz);
         ccR = new ChainControl(SCAN_CHAIN_XML, testerR, 1.8f, khz);
         ccC = new ChainControl(SCAN_CHAIN_XML, testerC, 1.8f, khz);
@@ -238,51 +243,24 @@ public class MarinaTest {
         
         PowerChannel pc = new ManualPowerChannel("pc", false);
         
-        ChainTest ctD, ctR, ctC;
         ctD = new ChainTest(ccD, pc);
         ctR = new ChainTest(ccR, pc);
         ctC = new ChainTest(ccC, pc);
-        
-        if (model instanceof VerilogModel) {
-            VerilogModel vm = (VerilogModel)model;
-            vm.start("verilog", "marina.v", VerilogModel.DUMPVARS, !cmdArgs.jtagShift);
-            vm.setNodeState("sid[9]", 1);
-            vm.setNodeState("sic[9]", 1);
-            vm.setNodeState("sir[9]", 1);
-            model.waitNS(1000);
-            vm.setNodeState("sid[9]", 0);
-            vm.setNodeState("sic[9]", 0);
-            vm.setNodeState("sir[9]", 0);
-            model.waitNS(1000);
-        } else {
-            ((SimulationModel)model).start("nanosim -c cfg", netListName, 0, !cmdArgs.jtagShift);
-            System.out.println("**** vdd="+((NanosimModel)model).getVdd());
-        }
-
-        if (cmdArgs.testChains) {
-            prln("Testing control chain...");
-            ctC.testOneChain(Marina.CONTROL_CHAIN, Infrastructure.SEVERITY_WARNING);
-        }
-        ccC.resetInBits();
-        ccC.shift(Marina.CONTROL_CHAIN, false, true);
-        if (cmdArgs.testChains) {            
-            prln("Testing data chain...");
-            ctD.testOneChain(Marina.DATA_CHAIN, Infrastructure.SEVERITY_WARNING);
-            //ccD.resetInBits();
-            //ccD.shift(Marina.DATA_CHAIN, false, true);
-
-            prln("Testing report chain...");            
-            ctR.testOneChain(Marina.REPORT_CHAIN, Infrastructure.SEVERITY_WARNING);
-            //ccR.resetInBits();
-            //ccR.shift(Marina.REPORT_CHAIN, false, true);
-        }
 
         ccs.addChain(Marina.DATA_CHAIN, ccD);
         ccs.addChain(Marina.REPORT_CHAIN, ccR);
         ccs.addChain(Marina.CONTROL_CHAIN, ccC);
-
+        
         marina = new Marina(ccs, model, !cmdArgs.jtagShift, indenter);
 
+        if (model instanceof VerilogModel)
+            ((SimulationModel)model).start("verilog", "marina.v", VerilogModel.DUMPVARS, !cmdArgs.jtagShift);
+        else
+            ((SimulationModel)model).start("nanosim -c cfg", netListName, 0, !cmdArgs.jtagShift);
+
+        ccC.resetInBits();
+        ccC.shift(Marina.CONTROL_CHAIN, false, true);
+        
         doOneTest(cmdArgs.testNum);
         
         ((SimulationModel)model).finish();
@@ -303,11 +281,8 @@ public class MarinaTest {
         PowerChannel pc = new ManualPowerChannel("pc", false);
         ChainTest ct = new ChainTest(cc, pc);
         ct.testAllChains("marina", Infrastructure.SEVERITY_WARNING);
-
         doOneTest(cmdArgs.testNum);
-        
         setUpSuppliesAndMeters(cmdArgs.station);
-                
     }
 
     /** In the absence of looping, the longest path through Infinity is 4 column delays */
@@ -453,6 +428,23 @@ public class MarinaTest {
     //=========================================================================
     // Put top level tests here
 
+    private void testChains(Marina marina) {
+        prln("Testing control chain...");
+        ctC.testOneChain(Marina.CONTROL_CHAIN, Infrastructure.SEVERITY_WARNING);
+        ccC.resetInBits();
+        ccC.shift(Marina.CONTROL_CHAIN, false, true);
+        
+        prln("Testing data chain...");
+        ctD.testOneChain(Marina.DATA_CHAIN, Infrastructure.SEVERITY_WARNING);
+        //ccD.resetInBits();
+        //ccD.shift(Marina.DATA_CHAIN, false, true);
+        
+        prln("Testing report chain...");            
+        ctR.testOneChain(Marina.REPORT_CHAIN, Infrastructure.SEVERITY_WARNING);
+        //ccR.resetInBits();
+        //ccR.shift(Marina.REPORT_CHAIN, false, true);
+    }
+
     private void testProperStoppers(Marina marina) {
         prln("Begin testProperStoppers");
         adjustIndent(2);
@@ -1235,7 +1227,6 @@ public class MarinaTest {
                                                  false                  // tokenOut    
                                                  ));
         marina.instrIn.fill(new Instruction.Set(dock,Predicate.IgnoreFlagD, SET_FLAG, SET_FLAG));
-
         model.waitNS(64 * CYCLE_TIME_NS);
 
         prln("checking to confirm that A flag is cleared");
@@ -1247,6 +1238,7 @@ public class MarinaTest {
         for(int i=0; i<data.getNumBits(); i++) data.set(i, false);
         for(int i=0; i<addr.getNumBits(); i++) addr.set(i, false);
         marina.fillNorthProperStopper(new MarinaPacket(data, false, addr));
+        model.waitNS(64 * CYCLE_TIME_NS);
 
         prln("checking to see if A flag got set");
         fatal(!marina.getFlagA(), "bad A flag: "+marina.getFlagA());
@@ -1989,6 +1981,7 @@ public class MarinaTest {
 
                 doOneTest(1);
                 doOneTest(2);
+                doOneTest(3);
                 doOneTest(4);
                 doOneTest(5);
                 doOneTest(6);
@@ -2027,12 +2020,12 @@ public class MarinaTest {
 
                 break;
             }
-            case 1:    testProperStoppers(marina);             break; // passes, 24-Mar (+verilog)
-            case 2:    sendInstructions(marina);               break; // passes, 24-Mar (+verilog)
-
+            case 1:    testChains(marina);                     break; // passes, 24-Mar (+verilog)
+            case 2:    testProperStoppers(marina);             break; // passes, 24-Mar (+verilog)
+            case 3:    testSouthRecirculate(marina, 1);        break; // passes, 24-Mar (+verilog)
             case 4:    getCtrsFlags(marina);                   break; //         20-Apr (+verilog)
-            case 5:    walkOneOLC(marina);                     break; //         21-Apr (+verilog)
-            case 6:    testSouthRecirculate(marina, 1);        break; // passes, 24-Mar (+verilog)
+            case 5:    sendInstructions(marina);               break; // passes, 24-Mar (+verilog)
+            case 6:    walkOneOLC(marina);                     break; //         21-Apr (+verilog)
                 
                 // Russell's tests begin with 1000
             case 1000: walkOneILC(marina);                     break; //         20-Apr (+verilog)
diff --git a/testCode/marina.bsh b/testCode/marina.bsh
index 4a6db88..fd37d8f 100644
--- a/testCode/marina.bsh
+++ b/testCode/marina.bsh
@@ -44,4 +44,4 @@ import com.sun.electric.plugins.menus.ScanChainXML;
    gen.startFromExport("sir[1]", "marina_report");
    gen.startFromExport("sic[1]", "marina_control");
    gen.startFromExport("sid[1]", "marina_data");
-   gen.start("aMarinaM","marinaOut{sch}");
+   gen.start("aMarinaM","marinaOutDock{sch}");
diff --git a/testCode/marina.spi b/testCode/marina.spi
index 8d466f1..c2b50a2 100644
--- a/testCode/marina.spi
+++ b/testCode/marina.spi
@@ -1,7 +1,7 @@
-*** SPICE deck for cell marinaOut{sch} from library aMarinaM
+*** SPICE deck for cell marinaOutDock{sch} from library aMarinaM
 *** Created on Mon Nov 17, 2008 08:47:24
-*** Last revised on Mon Mar 30, 2009 06:59:15
-*** Written on Thu Apr 30, 2009 17:07:37 by Electric VLSI Design System, 
+*** Last revised on Sat May 02, 2009 06:16:53
+*** Written on Mon May 04, 2009 13:31:09 by Electric VLSI Design System, 
 *version 8.08k
 *** Layout tech: cmos90, foundry TSMC
 *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF
@@ -4749,6 +4749,8 @@ Xinv@3 ps[15] net@52 inv-X_10
 XinvI@0 net@58 net@40 inv-X_30
 XlatchAnd@1 ps[14] fire[M] net@43 latchAndDriver30
 Xnand3@1 net@25 net@28 fire[M] net@59 nand3-X_6_667
+Xtc[1] tranCap
+Xtc[2] tranCap
 Xwire90@0 net@43 take[ps] wire90-3495_7-layer_1-width_3
 Xwire90@1 net@40 take[dp] wire90-3616_3-layer_1-width_3
 Xwire90@3 net@46 net@28 wire90-270-layer_1-width_3
@@ -5712,6 +5714,11 @@ XinvI@0 flag[A][F] s[1] inv-X_10
 XinvI@1 flag[B][F] s[2] inv-X_10
 XinvI@2 flag[C][F] s[3] inv-X_10
 XscanEx3h@0 s[1] s[2] s[3] mc p1p p2p rd sin sout scanEx3h
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
 .ENDS flags
 
 *** CELL: orangeTSMC090nm:wire{sch}
@@ -6557,7 +6564,7 @@ Xarbiter2@1 net@130 net@129 torp in[T] arbiter2
 XinvI@0 net@150 fire[T] inv-X_20
 XinvI@6 net@271 net@217 inv-X_5
 XinvI@7 net@224 invI@7_out inv-X_10
-Xnand2@2 net@224 do[ins] net@86 nand2-X_10
+Xnand2@2 net@224 do[ins] net@86 nand2-X_5
 Xnand2@5 winLO[M] sel[Mv] net@221 nand2-X_5
 Xnand2@6 sel[Tp] do[ins] net@254 nand2-X_10
 Xnand2n@0 sel[Di] net@11 net@57 nand2n-X_20
@@ -6971,6 +6978,37 @@ Xpms1@2 out inA pms1-X_3
 Xpms1@3 out resetLO pms1-X_20
 .ENDS nand3in20sr
 
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-431_3-R_34_667m a b
+Ccap@0 gnd net@14 1.581f
+Ccap@1 gnd net@8 1.581f
+Ccap@2 gnd net@11 1.581f
+Rres@0 net@14 a 2.492
+Rres@1 net@11 net@14 4.984
+Rres@2 b net@8 2.492
+Rres@3 net@8 net@11 4.984
+.ENDS wire-C_0_011f-431_3-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-431_3-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-431_3-R_34_667m
+.ENDS wire90-431_3-layer_1-width_3
+
+*** CELL: predicateM:flagNOP{sch}
+.SUBCKT flagNOP do[ins] ps[Fl]
+Xinv@0 net@16 net@23 inv-X_5
+XinvI@0 net@22 net@21 inv-X_10
+XinvI@1 net@29 net@15 inv-X_5
+XinvI@2 net@15 invI@2_out inv-X_10
+XinvI@3 net@23 invI@3_out inv-X_10
+Xnand2@0 ps[Fl] do[ins] net@0 nand2-X_5
+XpredDri4@0 net@4 do[ins] predDri40
+Xwire90@0 net@0 net@29 wire90-431_3-layer_1-width_3
+Xwire90@1 net@15 net@16 wire90-414-layer_1-width_3
+Xwire90@2 net@4 net@21 wire90-431_3-layer_1-width_3
+Xwire90@3 net@22 net@23 wire90-414-layer_1-width_3
+.ENDS flagNOP
+
 *** CELL: redFive:pms2{sch}
 .SUBCKT pms2-X_1_5 d g g2
 XPMOS@0 net@2 g vdd PMOSx-X_3
@@ -7062,48 +7100,65 @@ XpredCond@0 sel[rD] fire[do] mc flag[D][clr] predCond20wMC
 XpredCond@1 sel[rD] fire[do] mc flag[D][set] predCond20wMS
 .ENDS predFlagDri
 
+*** CELL: orangeTSMC090nm:NMOSxwk{sch}
+.SUBCKT NMOSxwk-X_4 d g s
+MNMOSfwk@0 d g s gnd nch W='12*(1+ABN/sqrt(12*2))' L='2'  
++DELVTO='AVT0N/sqrt(12*2)'
+.ENDS NMOSxwk-X_4
+
+*** CELL: redFive:invK{sch}
+.SUBCKT invK-X_4 in out
+XNMOSwk@0 out in gnd NMOSxwk-X_4
+XPMOSwk@0 out in vdd PMOSxwk-X_4
+.ENDS invK-X_4
+
 *** CELL: redFive:nms1{sch}
 .SUBCKT nms1-X_10 d g
 XNMOS@1 d g gnd NMOSx-X_10
 .ENDS nms1-X_10
 
-*** CELL: redFive:pms1{sch}
-.SUBCKT pms1-X_4 d g
-XPMOS@0 d g vdd PMOSx-X_4
-.ENDS pms1-X_4
-
-*** CELL: redFive:pms2{sch}
-.SUBCKT pms2-X_40 d g g2
-XPMOS@0 net@2 g vdd PMOSx-X_80
-XPMOS@1 d g2 net@2 PMOSx-X_80
-.ENDS pms2-X_40
-
-*** CELL: driversM:sucNANDdri40keep{sch}
-.SUBCKT sucNANDdri40keep in inB mc succ
-MNMOS4fwk@0 gnd net@164 succ NMOS4fwk@0_b nch W='3*(1+ABN/sqrt(3*2))' L='2' 
-+DELVTO='AVT0N/sqrt(3*2)'
-MPMOS4fwk@1 net@174 net@164 succ PMOS4fwk@1_b pch W='3*(1+ABP/sqrt(3*2))' 
-+L='2' DELVTO='AVT0P/sqrt(3*2)'
-Xinv@3 succ net@167 inv-X_4
-XinvI@0 in net@144 inv-X_20
+*** CELL: driversM:sucDri40keep{sch}
+.SUBCKT sucDri40keep in mc succ
+XPMOSx@0 succ net@124 vdd PMOSx-X_40
+Xinv@2 in net@110 inv-X_10
+Xinv@3 succ net@115 inv-X_4
+XinvK@0 net@113 succ invK-X_4
 Xnms1@0 succ mc nms1-X_10
-Xpms1@0 net@174 mc pms1-X_4
-Xpms2a@0 succ inB net@145 pms2-X_40
-Xwire90@1 net@144 net@145 wire90-503_4-layer_1-width_3
-Xwire90@2 net@167 net@164 wire90-124_7-layer_1-width_3
-.ENDS sucNANDdri40keep
+Xwire90@0 net@113 net@115 wire90-124_7-layer_1-width_3
+Xwire90@1 net@110 net@124 wire90-503_4-layer_1-width_3
+.ENDS sucDri40keep
+
+*** CELL: orangeTSMC090nm:wire{sch}
+.SUBCKT wire-C_0_011f-215_4-R_34_667m a b
+Ccap@0 gnd net@14 0.79f
+Ccap@1 gnd net@8 0.79f
+Ccap@2 gnd net@11 0.79f
+Rres@0 net@14 a 1.245
+Rres@1 net@11 net@14 2.489
+Rres@2 b net@8 1.245
+Rres@3 net@8 net@11 2.489
+.ENDS wire-C_0_011f-215_4-R_34_667m
+
+*** CELL: orangeTSMC090nm:wire90{sch}
+.SUBCKT wire90-215_4-layer_1-width_3 a b
+Xwire@0 a b wire-C_0_011f-215_4-R_34_667m
+.ENDS wire90-215_4-layer_1-width_3
 
 *** CELL: predicateM:ohPredDo{sch}
 .SUBCKT ohPredDo do[ins] fire[do] fire[skip] flag[A][clr] flag[A][set] 
-+flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[Fl] m1[rD] mc ps[do] 
-+ps[skip]
++flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[Fl] m1[rD] mc ps[Fl] 
++ps[do] ps[skip] s[3]
 XbitAssig@0 bitAssignments
+XflagNOP@0 do[ins] ps[Fl] flagNOP
+Xinv@0 do[ins] net@159 inv-X_5
+XinvI@0 net@156 s[3] inv-X_10
 XpredFlag@1 fire[do] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] 
 +flag[D][clr] flag[D][set] mc m1[Fl] m1[rD] predFlagDri
 XsucDri20@0 net@55 ps[skip] sucDri20
 XsucDri20@1 fire[do] ps[do] sucDri20
-XsucNANDd@0 fire[do] m1[Fl] mc do[ins] sucNANDdri40keep
+XsucDri40@0 fire[do] mc do[ins] sucDri40keep
 Xwire90@2 fire[skip] net@55 wire90-309-layer_1-width_3
+Xwire90@3 net@159 net@156 wire90-215_4-layer_1-width_3
 .ENDS ohPredDo
 
 *** CELL: redFive:pms1{sch}
@@ -7259,22 +7314,6 @@ Rres@3 net@8 net@11 7.223
 Xwire@0 a b wire-C_0_011f-625_1-R_34_667m
 .ENDS wire90-625_1-layer_1-width_3
 
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-215_4-R_34_667m a b
-Ccap@0 gnd net@14 0.79f
-Ccap@1 gnd net@8 0.79f
-Ccap@2 gnd net@11 0.79f
-Rres@0 net@14 a 1.245
-Rres@1 net@11 net@14 2.489
-Rres@2 b net@8 1.245
-Rres@3 net@8 net@11 2.489
-.ENDS wire-C_0_011f-215_4-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-215_4-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-215_4-R_34_667m
-.ENDS wire90-215_4-layer_1-width_3
-
 *** CELL: predicateM:ohPredPred{sch}
 .SUBCKT ohPredPred any do fire[both] flag[A][clr] flag[A][set] flag[B][clr] 
 +flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F] 
@@ -7457,26 +7496,29 @@ Xwire@0 a b wire-C_0_011f-2516_8-R_34_667m
 .SUBCKT ohPredAll do[ins] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] 
 +flag[D][clr] flag[D][set] m1[Fl] m1[rD] m1cate[1][F] m1cate[1][T] 
 +m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] 
-+m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p ps[do] 
++m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p ps[Fl] ps[do] 
 +ps[skip] rd sin sout
 XbitAssig@0 bitAssignments
-Xinv@1 do[ins] net@206 inv-X_5
 XinvI@0 net@82 net@166 inv-X_40
 XinvI@1 net@63 net@144 inv-X_10
 XinvI@2 do[ins] net@193 inv-X_10
-XinvI@3 net@200 s[3] inv-X_10
 Xnand2_sy@0 net@94 net@11 net@63 nand2_sy-X_10
 Xnand2n_s@0 net@147 net@84 fire[both] nand2n_sy-X_30
 Xnand3in2@1 net@46 net@41 net@11 net@82 net@21 nand3in20sr
 Xnor2n_sy@0 ps[skip] ps[do] net@39 nor2n_sy-X_10
 XohPredDo@1 do[ins] fire[do] fire[skip] flag[A][clr] flag[A][set] 
-+flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[Fl] m1[rD] mc ps[do] 
-+ps[skip] ohPredDo
++flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1[Fl] m1[rD] mc ps[Fl] 
++ps[do] ps[skip] s[3] ohPredDo
 XohPredPr@1 net@92 net@139 net@160 flag[A][clr] flag[A][set] flag[B][clr] 
 +flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] m1cate[1][T] m1cate[2][F] 
 +m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] 
 +m1cate[5][T] m1cate[6][F] m1cate[6][T] mc net@19 s[1] s[2] ohPredPred
 XscanEx3h@0 s[1] s[2] s[3] mc p1p p2p rd sin sout scanEx3h
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
+Xtc[5] tranCap
 Xwire90@0 net@39 net@11 wire90-1000_9-layer_1-width_3
 Xwire90@1 net@193 net@41 wire90-544-layer_1-width_3
 Xwire90@2 net@46 net@139 wire90-863_3-layer_1-width_3
@@ -7486,7 +7528,6 @@ Xwire90@5 net@147 net@63 wire90-602_8-layer_1-width_3
 Xwire90@6 net@92 net@94 wire90-613_9-layer_1-width_3
 Xwire90@7 fire[skip] net@144 wire90-782-layer_1-width_3
 Xwire90@9 fire[both] net@160 wire90-2516_8-layer_1-width_3
-Xwire90@10 net@206 net@200 wire90-215_4-layer_1-width_3
 Xwire90@11 net@166 fire[do] wire90-782-layer_1-width_3
 .ENDS ohPredAll
 
@@ -7499,22 +7540,6 @@ Xwire90@6 net@158 net@163 wire90-414-layer_1-width_3
 Xwire90@7 net@161 net@162 wire90-927-layer_1-width_3
 .ENDS ctrAND2in100
 
-*** CELL: orangeTSMC090nm:wire{sch}
-.SUBCKT wire-C_0_011f-431_3-R_34_667m a b
-Ccap@0 gnd net@14 1.581f
-Ccap@1 gnd net@8 1.581f
-Ccap@2 gnd net@11 1.581f
-Rres@0 net@14 a 2.492
-Rres@1 net@11 net@14 4.984
-Rres@2 b net@8 2.492
-Rres@3 net@8 net@11 4.984
-.ENDS wire-C_0_011f-431_3-R_34_667m
-
-*** CELL: orangeTSMC090nm:wire90{sch}
-.SUBCKT wire90-431_3-layer_1-width_3 a b
-Xwire@0 a b wire-C_0_011f-431_3-R_34_667m
-.ENDS wire90-431_3-layer_1-width_3
-
 *** CELL: loopCountM:ilcLoad{sch}
 .SUBCKT ilcLoad do[ins] ilc[load] sel[Ld] sel[rD]
 XctrAND2i@0 sel[rD] net@12 ilc[load] ctrAND2in100
@@ -7762,7 +7787,6 @@ Xinv@32 net@1032 net@1057 inv-X_5
 Xinv@34 net@913 inv@34_out inv-X_10
 XinvI@7 net@929 net@913 inv-X_5
 XinvI@8 net@1046 net@937 inv-X_10
-XinvI@11 net@908 invI@11_out inv-X_10
 Xnand2@5 sel[Ld] do[ins] net@956 nand2-X_5
 Xnand2@7 net@1035 do[2] net@1033 nand2-X_5
 Xnand2n_s@1 doneLO[M] net@908 fire[zz] nand2n_sy-X_6
@@ -8098,6 +8122,10 @@ Xolc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] inLO[1] inLO[2]
 XscanEx2h@0 s[1] s[2] mc p1p p2p rd net@81 sout scanEx2h
 XscanEx3h@1 bitt[1] bitt[3] bitt[5] mc p1p p2p rd sin net@46 scanEx3h
 XscanEx3h@2 bitt[2] bitt[4] bitt[6] mc p1p p2p rd net@46 net@81 scanEx3h
+Xtc[1] tranCap
+Xtc[2] tranCap
+Xtc[3] tranCap
+Xtc[4] tranCap
 Xwire90@1 olc[zero] wire90@1_b wire90-1022_9-layer_1-width_3
 Xwire90@2 olc[zoo] wire90@2_b wire90-810_8-layer_1-width_3
 Xwire90@3 olc[load] wire90@3_b wire90-4437_9-layer_1-width_3
@@ -8213,9 +8241,9 @@ Xwire@0 a b wire-C_0_011f-867_8-R_34_667m
 +m1[1] m1[21] m1[22] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] 
 +m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] 
 +m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] 
-+pred[D] pred[T] ps[18] ps[19] ps[20] ps[21] ps[23] ps[24] ps[25] ps[26] 
-+ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] 
-+sir[9] sor[1] succ[sf]
++pred[D] pred[T] ps[18] ps[19] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] 
++ps[26] ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] 
++sir[8] sir[9] sor[1] succ[sf]
 XbitAssig@0 bitAssignments
 Xflags@0 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][T] 
 +m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] 
@@ -8229,7 +8257,7 @@ XohPredAl@0 do[ins] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set]
 +flag[D][clr] flag[D][set] m1[22] m1[21] m1cate[1][F] m1cate[1][T] 
 +m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] 
 +m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9] sir[3] sir[2] 
-+ps[do] ps[skip] sir[5] net@244 net@249 ohPredAll
++ps[22] ps[do] ps[skip] sir[5] net@244 net@249 ohPredAll
 XolcWcont@0 do[ins] doneLO[M] flag[D][clr] flag[D][set] net@165 inLO[1] 
 +inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] sir[9] sir[3] sir[2] sir[5] ps[24] 
 +ps[23] ps[21] net@279 net@244 olcWcont
@@ -8247,6 +8275,8 @@ Xtc[11] tranCap
 Xtc[12] tranCap
 Xtc[13] tranCap
 Xtc[14] tranCap
+Xtc[15] tranCap
+Xtc[16] tranCap
 Xwire90@5 wire90@5_a flag[A][set] wire90-3750-layer_1-width_3
 Xwire90@6 wire90@6_a flag[A][clr] wire90-3560-layer_1-width_3
 Xwire90@7 wire90@7_a flag[B][set] wire90-3750-layer_1-width_3
@@ -8384,17 +8414,18 @@ XdockPSre@0 do[ins] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17]
 +m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] 
 +m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] inLO[1] inLO[2] inLO[3] 
 +inLO[4] inLO[5] inLO[6] inLO[8] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] 
-+ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] 
-+ps[26] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] dockPSreg
++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] psx[21] psx[22] psx[23] psx[24] 
++psx[25] psx[26] ps[27] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] 
++dockPSreg
 XoutDockC@0 net@101 epi[torp] fire[M] flag[A][clr] flag[A][set] flag[C][T] 
 +flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] 
 +inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] m1[11] m1[12] m1[1] m1[21] 
 +m1[22] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] 
 +m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] 
 +m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D] 
-+pred[T] ps[18] ps[19] ps[20] ps[21] ps[23] ps[24] ps[25] ps[26] ps[do] 
-+ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] 
-+sor[1] succ[sf] outDockCenter
++pred[T] ps[18] ps[19] ps[20] psx[21] psx[22] psx[23] psx[24] psx[25] psx[26] 
++ps[do] ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] 
++sir[9] sor[1] succ[sf] outDockCenter
 Xwire90@1 wire90@1_a inLO[1] wire90-5146_2-layer_1-width_3
 Xwire90@2 wire90@2_a inLO[2] wire90-5054_2-layer_1-width_3
 Xwire90@3 wire90@3_a inLO[3] wire90-4771_5-layer_1-width_3
@@ -9062,7 +9093,7 @@ Xwire90@1 net@2 net@3 wire90-291_8-layer_1-width_3
 
 .global gnd vdd
 
-*** TOP LEVEL CELL: marinaOut{sch}
+*** TOP LEVEL CELL: marinaOutDock{sch}
 XnorthFif@1 dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] 
 +dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9] dsA[TT] ain[10] ain[11] ain[12] 
 +ain[13] ain[14] ain[1] ain[2] ain[3] ain[4] ain[5] ain[6] ain[7] ain[8] 
diff --git a/testCode/marina.v b/testCode/marina.v
index 9fc4dd2..31e484e 100644
--- a/testCode/marina.v
+++ b/testCode/marina.v
@@ -1,7 +1,7 @@
-/* Verilog for cell 'marinaOut{sch}' from library 'aMarinaM' */
+/* Verilog for cell 'marinaOutDock{sch}' from library 'aMarinaM' */
 /* Created on Mon Nov 17, 2008 08:47:24 */
-/* Last revised on Mon Mar 30, 2009 06:59:15 */
-/* Written on Thu Apr 30, 2009 17:07:05 by Electric VLSI Design System, version 8.08k */
+/* Last revised on Sat May 02, 2009 06:16:53 */
+/* Written on Mon May 04, 2009 13:31:06 by Electric VLSI Design System, version 8.08k */
 
 module orangeTSMC090nm__wire(a);
   input a;
@@ -3715,6 +3715,8 @@ module registersM__newPathReg(dp, fire_M_, ps, aout, aout_TT_);
   /* begin Verilog_template for redFive:nand3{sch}*/
   nand (strong0, strong1) #(100) nand3_1 (net_58, net_25, net_28, fire_M_);
   // end Verilog_template
+  wiresL__tranCap tc_1_();
+  wiresL__tranCap tc_2_();
   orangeTSMC090nm__wire90 wire90_0(.a(take_ps_));
   orangeTSMC090nm__wire90 wire90_1(.a(take_dp_));
   orangeTSMC090nm__wire90 wire90_3(.a(net_28));
@@ -4372,6 +4374,11 @@ module oneHotM__flags(flag_A__clr_, flag_A__set_, flag_B__clr_, flag_B__set_,
   // end Verilog_template
   scanM__scanEx3h scanEx3h_0(.dIn(s[1:3]), .sin(sin), .mc(mc), .sout(sout), 
       .p1p(p1p), .p2p(p2p), .rd(rd));
+  wiresL__tranCap tc_1_();
+  wiresL__tranCap tc_2_();
+  wiresL__tranCap tc_3_();
+  wiresL__tranCap tc_4_();
+  wiresL__tranCap tc_5_();
 endmodule   /* oneHotM__flags */
 
 module loopCountM__calculate(bit, bit_1, bit_2, bit_3, bit_4, bit_5, do, do_1, 
@@ -4996,6 +5003,39 @@ module predicateM__nand3in20sr(inA, inB, inC, resetLO, out);
   redFive__pms1 pms1_3(.g(resetLO), .d(out));
 endmodule   /* predicateM__nand3in20sr */
 
+module predicateM__flagNOP(do_ins_, ps_Fl_);
+  input do_ins_;
+  input ps_Fl_;
+
+  supply1 vdd;
+  supply0 gnd;
+  wire invI_2_out, invI_3_out, net_0, net_15, net_22, net_4;
+
+  /* begin Verilog_template for redFive:inv{sch}*/
+  not (strong0, strong1) #(100) inv_0 (net_22, net_15);
+  // end Verilog_template
+  /* begin Verilog_template for redFive:inv{sch}*/
+  not (strong0, strong1) #(100) invI_0 (net_4, net_22);
+  // end Verilog_template
+  /* begin Verilog_template for redFive:inv{sch}*/
+  not (strong0, strong1) #(100) invI_1 (net_15, net_0);
+  // end Verilog_template
+  /* begin Verilog_template for redFive:inv{sch}*/
+  not (strong0, strong1) #(100) invI_2 (invI_2_out, net_15);
+  // end Verilog_template
+  /* begin Verilog_template for redFive:inv{sch}*/
+  not (strong0, strong1) #(100) invI_3 (invI_3_out, net_22);
+  // end Verilog_template
+  /* begin Verilog_template for redFive:nand2{sch}*/
+  nand (strong0, strong1) #(100) nand2_0 (net_0, ps_Fl_, do_ins_);
+  // end Verilog_template
+  driversM__predDri40 predDri4_0(.in(net_4), .pred(do_ins_));
+  orangeTSMC090nm__wire90 wire90_0(.a(net_0));
+  orangeTSMC090nm__wire90 wire90_1(.a(net_15));
+  orangeTSMC090nm__wire90 wire90_2(.a(net_4));
+  orangeTSMC090nm__wire90 wire90_3(.a(net_22));
+endmodule   /* predicateM__flagNOP */
+
 module driversM__predCond20wMC(cond, in, mc, pred);
   input cond;
   input in;
@@ -5074,41 +5114,33 @@ module predicateM__predFlagDri(fire_do_, flag_A__clr_, flag_A__set_,
       .pred(flag_D__set_));
 endmodule   /* predicateM__predFlagDri */
 
-module driversM__sucNANDdri40keep(in, inB, mc, succ);
+module driversM__sucDri40keep(in, mc, succ);
   input in;
-  input inB;
   input mc;
   output succ;
 
   supply1 vdd;
   supply0 gnd;
-  wire NMOS4fwk_0_b, PMOS4fwk_1_b, net_144, net_164, net_174;
-
-  /* user-specified Verilog declarations */
-  wor succ;
+  wire net_110, net_113;
 
-  /* begin Verilog_template for orangeTSMC090nm:NMOS4fwk{sch}*/
-  rtranif1 #(100) NMOS4fwk_0 (gnd, succ, net_164);
-  // end Verilog_template
-  /* begin Verilog_template for orangeTSMC090nm:PMOS4fwk{sch}*/
-  rtranif0 #(100) PMOS4fwk_1 (net_174, succ, net_164);
-  // end Verilog_template
+  orangeTSMC090nm__PMOSx PMOSx_0(.g(net_110), .d(succ), .s(vdd));
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) inv_3 (net_164, succ);
+  not (strong0, strong1) #(100) inv_2 (net_110, in);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) invI_0 (net_144, in);
+  not (strong0, strong1) #(100) inv_3 (net_113, succ);
+  // end Verilog_template
+  /* begin Verilog_template for redFive:invK{sch}*/
+  not (weak0, weak1) #(100) invK_0 (succ, net_113);
   // end Verilog_template
   redFive__nms1 nms1_0(.g(mc), .d(succ));
-  redFive__pms1 pms1_0(.g(mc), .d(net_174));
-  redFive__pms2 pms2a_0(.g(inB), .g2(net_144), .d(succ));
-  orangeTSMC090nm__wire90 wire90_1(.a(net_144));
-  orangeTSMC090nm__wire90 wire90_2(.a(net_164));
-endmodule   /* driversM__sucNANDdri40keep */
+  orangeTSMC090nm__wire90 wire90_0(.a(net_113));
+  orangeTSMC090nm__wire90 wire90_1(.a(net_110));
+endmodule   /* driversM__sucDri40keep */
 
 module predicateM__ohPredDo(fire_do_, fire_skip_, flag_A__clr_, flag_A__set_, 
       flag_B__clr_, flag_B__set_, flag_D__clr_, flag_D__set_, m1_Fl_, m1_rD_, 
-      mc, do_ins_, ps_do_, ps_skip_);
+      mc, ps_Fl_, do_ins_, ps_do_, ps_skip_, s);
   input fire_do_;
   input fire_skip_;
   input flag_A__clr_;
@@ -5120,13 +5152,24 @@ module predicateM__ohPredDo(fire_do_, fire_skip_, flag_A__clr_, flag_A__set_,
   input m1_Fl_;
   input m1_rD_;
   input mc;
+  input ps_Fl_;
   output do_ins_;
   output ps_do_;
   output ps_skip_;
+  output [3:3] s;
 
   supply1 vdd;
   supply0 gnd;
+  wire net_156;
+
   wiresL__bitAssignments bitAssig_0();
+  predicateM__flagNOP flagNOP_0(.do_ins_(do_ins_), .ps_Fl_(ps_Fl_));
+  /* begin Verilog_template for redFive:inv{sch}*/
+  not (strong0, strong1) #(100) inv_0 (net_156, do_ins_);
+  // end Verilog_template
+  /* begin Verilog_template for redFive:inv{sch}*/
+  not (strong0, strong1) #(100) invI_0 (s[3], net_156);
+  // end Verilog_template
   predicateM__predFlagDri predFlag_1(.fire_do_(fire_do_), 
       .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_), 
       .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_), 
@@ -5134,9 +5177,9 @@ module predicateM__ohPredDo(fire_do_, fire_skip_, flag_A__clr_, flag_A__set_,
       .sel_Fl_(m1_Fl_), .sel_rD_(m1_rD_));
   driversM__sucDri20 sucDri20_0(.in(fire_skip_), .succ(ps_skip_));
   driversM__sucDri20 sucDri20_1(.in(fire_do_), .succ(ps_do_));
-  driversM__sucNANDdri40keep sucNANDd_0(.in(fire_do_), .inB(m1_Fl_), .mc(mc), 
-      .succ(do_ins_));
+  driversM__sucDri40keep sucDri40_0(.in(fire_do_), .mc(mc), .succ(do_ins_));
   orangeTSMC090nm__wire90 wire90_2(.a(fire_skip_));
+  orangeTSMC090nm__wire90 wire90_3(.a(net_156));
 endmodule   /* predicateM__ohPredDo */
 
 module predicateM__ohSRxor(flag_F_, flag_T_, resetLO, sel, out);
@@ -5303,7 +5346,8 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_,
       flag_B__set_, flag_D__clr_, flag_D__set_, m1_Fl_, m1_rD_, m1cate_1__F_, 
       m1cate_1__T_, m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_, 
       m1cate_4__F_, m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_, 
-      m1cate_6__T_, sin, do_ins_, ps_do_, ps_skip_, sout, mc, p1p, p2p, rd);
+      m1cate_6__T_, ps_Fl_, sin, do_ins_, ps_do_, ps_skip_, sout, mc, p1p, p2p, 
+      rd);
   input flag_A__clr_;
   input flag_A__set_;
   input flag_B__clr_;
@@ -5324,6 +5368,7 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_,
   input m1cate_5__T_;
   input m1cate_6__F_;
   input m1cate_6__T_;
+  input ps_Fl_;
   input sin;
   output do_ins_;
   output ps_do_;
@@ -5336,15 +5381,12 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_,
 
   supply1 vdd;
   supply0 gnd;
-  wire fire_both_, fire_do_, fire_skip_, net_11, net_19, net_200, net_41;
-  wire net_46, net_63, net_82, net_92;
+  wire fire_both_, fire_do_, fire_skip_, net_11, net_19, net_41, net_46, net_63;
+  wire net_82, net_92;
   wire [1:3] s;
 
   wiresL__bitAssignments bitAssig_0();
   /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) inv_1 (net_200, do_ins_);
-  // end Verilog_template
-  /* begin Verilog_template for redFive:inv{sch}*/
   not (strong0, strong1) #(100) invI_0 (fire_do_, net_82);
   // end Verilog_template
   /* begin Verilog_template for redFive:inv{sch}*/
@@ -5353,9 +5395,6 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_,
   /* begin Verilog_template for redFive:inv{sch}*/
   not (strong0, strong1) #(100) invI_2 (net_41, do_ins_);
   // end Verilog_template
-  /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) invI_3 (s[3], net_200);
-  // end Verilog_template
   /* begin Verilog_template for redFive:nand2_sy{sch}*/
   nand (strong0, strong1) #(100) nand2_sy_0 (net_63, net_92, net_11);
   // end Verilog_template
@@ -5367,8 +5406,8 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_,
       .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_), 
       .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_), 
       .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), 
-      .m1_Fl_(m1_Fl_), .m1_rD_(m1_rD_), .mc(mc), .do_ins_(do_ins_), 
-      .ps_do_(ps_do_), .ps_skip_(ps_skip_));
+      .m1_Fl_(m1_Fl_), .m1_rD_(m1_rD_), .mc(mc), .ps_Fl_(ps_Fl_), 
+      .do_ins_(do_ins_), .ps_do_(ps_do_), .ps_skip_(ps_skip_), .s({s[3]}));
   predicateM__ohPredPred ohPredPr_1(.fire_both_(fire_both_), 
       .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_), 
       .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_), 
@@ -5382,6 +5421,11 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_,
       .any(net_92), .do(net_46), .resetLO(net_19), .s(s[1:2]));
   scanM__scanEx3h scanEx3h_0(.dIn(s[1:3]), .sin(sin), .mc(mc), .sout(sout), 
       .p1p(p1p), .p2p(p2p), .rd(rd));
+  wiresL__tranCap tc_1_();
+  wiresL__tranCap tc_2_();
+  wiresL__tranCap tc_3_();
+  wiresL__tranCap tc_4_();
+  wiresL__tranCap tc_5_();
   orangeTSMC090nm__wire90 wire90_0(.a(net_11));
   orangeTSMC090nm__wire90 wire90_1(.a(net_41));
   orangeTSMC090nm__wire90 wire90_2(.a(net_46));
@@ -5391,7 +5435,6 @@ module predicateM__ohPredAll(flag_A__clr_, flag_A__set_, flag_B__clr_,
   orangeTSMC090nm__wire90 wire90_6(.a(net_92));
   orangeTSMC090nm__wire90 wire90_7(.a(fire_skip_));
   orangeTSMC090nm__wire90 wire90_9(.a(fire_both_));
-  orangeTSMC090nm__wire90 wire90_10(.a(net_200));
   orangeTSMC090nm__wire90 wire90_11(.a(fire_do_));
 endmodule   /* predicateM__ohPredAll */
 
@@ -5584,8 +5627,8 @@ module loopCountM__olcLoad(do_ins_, doneLO_M_, mc, sel_Ld_, sel_rD_, fire_zz_,
 
   supply1 vdd;
   supply0 gnd;
-  wire invI_11_out, inv_34_out, net_1035, net_905, net_908, net_929, net_937;
-  wire net_956, net_976;
+  wire inv_34_out, net_1035, net_905, net_908, net_929, net_937, net_956;
+  wire net_976;
   wire [2:2] do;
 
   centersJ__ctrAND3in100A ctrAND3i_2(.inA(do[2]), .inB(net_976), .inC(net_956), 
@@ -5608,9 +5651,6 @@ module loopCountM__olcLoad(do_ins_, doneLO_M_, mc, sel_Ld_, sel_rD_, fire_zz_,
   /* begin Verilog_template for redFive:inv{sch}*/
   not (strong0, strong1) #(100) invI_8 (net_937, net_908);
   // end Verilog_template
-  /* begin Verilog_template for redFive:inv{sch}*/
-  not (strong0, strong1) #(100) invI_11 (invI_11_out, net_908);
-  // end Verilog_template
   /* begin Verilog_template for redFive:nand2{sch}*/
   nand (strong0, strong1) #(100) nand2_5 (net_956, sel_Ld_, do_ins_);
   // end Verilog_template
@@ -5803,6 +5843,10 @@ module loopCountM__olcWcont(do_ins_, doneLO_M_, inLO, sel_Co_, sel_Ld_,
       .mc(mc), .sout(net_46), .p1p(p1p), .p2p(p2p), .rd(rd));
   scanM__scanEx3h scanEx3h_2(.dIn({bitt[2], bitt[4], bitt[6]}), .sin(net_46), 
       .mc(mc), .sout(net_81), .p1p(p1p), .p2p(p2p), .rd(rd));
+  wiresL__tranCap tc_1_();
+  wiresL__tranCap tc_2_();
+  wiresL__tranCap tc_3_();
+  wiresL__tranCap tc_4_();
   orangeTSMC090nm__wire90 wire90_1(.a(olc_zero_));
   orangeTSMC090nm__wire90 wire90_2(.a(olc_zoo_));
   orangeTSMC090nm__wire90 wire90_3(.a(olc_load_));
@@ -5821,10 +5865,8 @@ module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] ,
       \m1[11] , \m1[12] , \m1[21] , \m1[22] , m1cate_1__F_, m1cate_1__T_, 
       m1cate_2__F_, m1cate_2__T_, m1cate_3__F_, m1cate_3__T_, m1cate_4__F_, 
       m1cate_4__T_, m1cate_5__F_, m1cate_5__T_, m1cate_6__F_, m1cate_6__T_, 
-      pred_D_, pred_T_, \ps[18] , \ps[19] , \ps[20] , \ps[21] , \ps[23] , 
-      \ps[24] , \ps[25] , \ps[26] , sir, succ_sf_, do_ins_, fire_M_, 
-      flag_A__clr_, flag_A__set_, flag_D__clr_, flag_D__set_, ps_do_, ps_skip_, 
-      sor);
+      pred_D_, pred_T_, ps, sir, succ_sf_, do_ins_, fire_M_, flag_A__clr_, 
+      flag_A__set_, flag_D__clr_, flag_D__set_, ps_do_, ps_skip_, sor);
   input epi_torp_;
   input flag_C__T_;
   input [1:6] in;
@@ -5846,8 +5888,7 @@ module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] ,
   input m1cate_6__T_;
   input pred_D_;
   input pred_T_;
-  input \ps[18] , \ps[19] , \ps[20] , \ps[21] , \ps[23] , \ps[24] , \ps[25] , 
-      \ps[26] ;
+  input [18:26] ps;
   input [1:9] sir;
   input succ_sf_;
   output do_ins_;
@@ -5876,13 +5917,13 @@ module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] ,
       .ilc_load_(ilc_load_), .\inLO[1] ( \inLO[1] ), .\inLO[2] ( \inLO[2] ), 
       .\inLO[3] ( \inLO[3] ), .\inLO[4] ( \inLO[4] ), .\inLO[5] ( \inLO[5] ), 
       .\inLO[6] ( \inLO[6] ), .\inLO[8] ( \inLO[8] ), .pred_D_(pred_D_), 
-      .pred_T_(pred_T_), .sel_Di_( \ps[18] ), .sel_Mv_( \ps[25] ), .sel_Ti_( 
-      \ps[19] ), .sel_Tp_( \ps[26] ), .sin(net_249), .succ_sf_(succ_sf_), 
+      .pred_T_(pred_T_), .sel_Di_(ps[18]), .sel_Mv_(ps[25]), .sel_Ti_(ps[19]), 
+      .sel_Tp_(ps[26]), .sin(net_249), .succ_sf_(succ_sf_), 
       .doneLO_M_(doneLO_M_), .fire_M_(fire_M_), .flag_D__set_(flag_D__set_), 
       .sout(sor[1]), .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
-  loopCountM__muxForD muxForD_0(.in(in[1:6]), .sel( \ps[20] ), .outLO({ 
-      \inLO[1] ,  \inLO[2] ,  \inLO[3] ,  \inLO[4] ,  \inLO[5] ,  \inLO[6] ,  
-      \inLO[8] }));
+  loopCountM__muxForD muxForD_0(.in(in[1:6]), .sel(ps[20]), .outLO({ \inLO[1] , 
+       \inLO[2] ,  \inLO[3] ,  \inLO[4] ,  \inLO[5] ,  \inLO[6] ,  \inLO[8] 
+      }));
   predicateM__ohPredAll ohPredAl_0(.flag_A__clr_(flag_A__clr_), 
       .flag_A__set_(flag_A__set_), .flag_B__clr_(flag_B__clr_), 
       .flag_B__set_(flag_B__set_), .flag_D__clr_(flag_D__clr_), 
@@ -5892,15 +5933,16 @@ module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] ,
       .m1cate_3__F_(m1cate_3__F_), .m1cate_3__T_(m1cate_3__T_), 
       .m1cate_4__F_(m1cate_4__F_), .m1cate_4__T_(m1cate_4__T_), 
       .m1cate_5__F_(m1cate_5__F_), .m1cate_5__T_(m1cate_5__T_), 
-      .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_), .sin(net_244), 
-      .do_ins_(do_ins_), .ps_do_(ps_do_), .ps_skip_(ps_skip_), .sout(net_249), 
-      .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
+      .m1cate_6__F_(m1cate_6__F_), .m1cate_6__T_(m1cate_6__T_), 
+      .ps_Fl_(ps[22]), .sin(net_244), .do_ins_(do_ins_), .ps_do_(ps_do_), 
+      .ps_skip_(ps_skip_), .sout(net_249), .mc(sir[9]), .p1p(sir[3]), 
+      .p2p(sir[2]), .rd(sir[5]));
   loopCountM__olcWcont olcWcont_0(.do_ins_(do_ins_), .doneLO_M_(doneLO_M_), 
       .inLO({ \inLO[1] ,  \inLO[2] ,  \inLO[3] ,  \inLO[4] ,  \inLO[5] ,  
-      \inLO[6] }), .sel_Co_( \ps[24] ), .sel_Ld_( \ps[23] ), .sel_rD_( \ps[21] 
-      ), .sin(net_279), .flag_D__clr_(flag_D__clr_), 
-      .flag_D__set_(flag_D__set_), .ilc_load_(ilc_load_), .sout(net_244), 
-      .mc(sir[9]), .p1p(sir[3]), .p2p(sir[2]), .rd(sir[5]));
+      \inLO[6] }), .sel_Co_(ps[24]), .sel_Ld_(ps[23]), .sel_rD_(ps[21]), 
+      .sin(net_279), .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), 
+      .ilc_load_(ilc_load_), .sout(net_244), .mc(sir[9]), .p1p(sir[3]), 
+      .p2p(sir[2]), .rd(sir[5]));
   wiresL__tranCap tc_1_();
   wiresL__tranCap tc_2_();
   wiresL__tranCap tc_3_();
@@ -5915,6 +5957,8 @@ module stagesM__outDockCenter(epi_torp_, flag_C__T_, in, \inLO[1] , \inLO[2] ,
   wiresL__tranCap tc_12_();
   wiresL__tranCap tc_13_();
   wiresL__tranCap tc_14_();
+  wiresL__tranCap tc_15_();
+  wiresL__tranCap tc_16_();
   orangeTSMC090nm__wire90 wire90_5(.a(flag_A__set_));
   orangeTSMC090nm__wire90 wire90_6(.a(flag_A__clr_));
   orangeTSMC090nm__wire90 wire90_7(.a(flag_B__set_));
@@ -5975,14 +6019,14 @@ module stagesM__outDockPredStage(epi_torp_, flag_C__T_, in, m1, m1cate_1__F_,
   wire \inLO[5] ;
   wire \inLO[6] ;
   wire \inLO[8] ;
-  wire [21:26] ps_1;
+  wire [21:26] psx;
 
   registersM__dockPSreg dockPSre_0(.do_ins_(do_ins_), .m1(m1[1:27]), .outLO({ 
       \inLO[1] ,  \inLO[2] ,  \inLO[3] ,  \inLO[4] ,  \inLO[5] ,  \inLO[6] ,  
       \inLO[8] }), .ps({ \ps[1] ,  \ps[2] ,  \ps[3] ,  \ps[4] ,  \ps[5] ,  
       \ps[6] ,  \ps[7] ,  \ps[8] ,  \ps[9] ,  \ps[10] ,  \ps[11] ,  \ps[12] ,  
       \ps[13] ,  \ps[14] ,  \ps[15] ,  \ps[16] ,  \ps[17] ,  \ps[18] ,  \ps[19] 
-      ,  \ps[20] , ps_1[21], ps_1[22], ps_1[23], ps_1[24], ps_1[25], ps_1[26],  
+      ,  \ps[20] , psx[21], psx[22], psx[23], psx[24], psx[25], psx[26],  
       \ps[27] }));
   stagesM__outDockCenter outDockC_0(.epi_torp_(epi_torp_), 
       .flag_C__T_(flag_C__T_), .in(in[1:6]), .\inLO[1] ( \inLO[1] ), .\inLO[2] 
@@ -5997,10 +6041,9 @@ module stagesM__outDockPredStage(epi_torp_, flag_C__T_, in, m1, m1cate_1__F_,
       .m1cate_3__T_(m1cate_3__T_), .m1cate_4__F_(m1cate_4__F_), 
       .m1cate_4__T_(m1cate_4__T_), .m1cate_5__F_(m1cate_5__F_), 
       .m1cate_5__T_(m1cate_5__T_), .m1cate_6__F_(m1cate_6__F_), 
-      .m1cate_6__T_(m1cate_6__T_), .pred_D_(pred_D_), .pred_T_(pred_T_), 
-      .\ps[18] ( \ps[18] ), .\ps[19] ( \ps[19] ), .\ps[20] ( \ps[20] ), 
-      .\ps[21] (ps_1[21]), .\ps[23] (ps_1[23]), .\ps[24] (ps_1[24]), .\ps[25] 
-      (ps_1[25]), .\ps[26] (ps_1[26]), .sir(sir[1:9]), .succ_sf_(succ_sf_), 
+      .m1cate_6__T_(m1cate_6__T_), .pred_D_(pred_D_), .pred_T_(pred_T_), .ps({ 
+      \ps[18] ,  \ps[19] ,  \ps[20] , psx[21], psx[22], psx[23], psx[24], 
+      psx[25], psx[26]}), .sir(sir[1:9]), .succ_sf_(succ_sf_), 
       .do_ins_(do_ins_), .fire_M_(fire_M_), .flag_A__clr_(flag_A__clr_), 
       .flag_A__set_(flag_A__set_), .flag_D__clr_(flag_D__clr_), 
       .flag_D__set_(flag_D__set_), .ps_do_(ps_do_), .ps_skip_(ps_skip_), 
@@ -6528,7 +6571,7 @@ module stageGroupsM__tokenFIFO(pred, succ, sir, sor);
   orangeTSMC090nm__wire90 wire90_1(.a(net_2));
 endmodule   /* stageGroupsM__tokenFIFO */
 
-module marinaOut(fin, fout, sic, sid, sir);
+module marinaOutDock(fin, fout, sic, sid, sir);
   input fin;
   output fout;
   inout [1:9] sic;
@@ -6629,4 +6672,4 @@ module marinaOut(fin, fout, sic, sid, sir);
   stageGroupsM__tokenFIFO tokenFIF_1(.pred(dockSucc_T_), .succ(dockPred_T_), 
       .sir({net_120[8], net_109[7], net_109[6], net_109[5], net_109[4], sir[6], 
       sir[7], sir[8], sir[9]}), .sor({net_109[8]}));
-endmodule   /* marinaOut */
+endmodule   /* marinaOutDock */