From: adam Date: Wed, 30 Jan 2008 11:08:43 +0000 (+0100) Subject: more reset code X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=d446e2eee8e7170bfd23b198e6cf844e9f260d96;p=fleet.git more reset code --- diff --git a/ships/Alu1.ship b/ships/Alu1.ship index 8db948c..ee942cd 100644 --- a/ships/Alu1.ship +++ b/ships/Alu1.ship @@ -56,6 +56,11 @@ The result of this operation is then made available at {\tt out}. reg [(`PACKET_WIDTH-1):0] extrabits; always @(posedge clk) begin + if (!rst) begin + have_a = 0; + have_op = 0; + `reset + end else begin if (!have_a) begin `onread(in_r, in_a) have_a = 1; reg_a = in_d; end end @@ -82,6 +87,7 @@ The result of this operation is then made available at {\tt out}. have_op = 0; end end + end end == Test ============================================================================== diff --git a/ships/Alu2.ship b/ships/Alu2.ship index b1a7f1c..4a7298d 100644 --- a/ships/Alu2.ship +++ b/ships/Alu2.ship @@ -82,6 +82,11 @@ public void service() { reg [(`DATAWIDTH-1):0] reg_op; always @(posedge clk) begin + if (!rst) begin + have_a = 0; + have_b = 0; + have_op = 0; + end else begin if (!have_a) begin `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end end @@ -107,6 +112,7 @@ public void service() { end end end + end == Test ============================================================================== // expected output diff --git a/ships/Alu3.ship b/ships/Alu3.ship index 24b3efd..81f2a05 100644 --- a/ships/Alu3.ship +++ b/ships/Alu3.ship @@ -86,6 +86,21 @@ public void service() { reg wrote; initial wrote = 0; always @(posedge clk) begin + if (!rst) begin + `reset + mode = 0; + have_in1 <= 0; + have_in2 <= 0; + have_in3 <= 0; + keep_in1 <= 0; + keep_in2 <= 0; + keep_in3 <= 0; + have_out1 <= 0; + have_out2 <= 0; + bitstorage = 0; + bitstorage_count <= 0; + wrote = 0; + end else begin wrote = 0; if (bitstorage_count >= `DATAWIDTH) begin outBits_d = bitstorage[(`DATAWIDTH-1):0]; @@ -116,13 +131,13 @@ public void service() { have_in2 <= 0; have_in3 <= 0; end + end end == Test ======================================================================== - #ship alu3 : Alu3 #ship lut3 : Lut3 #ship bitfifo : BitFifo diff --git a/ships/BitFifo.ship b/ships/BitFifo.ship index 81aed63..e315122 100644 --- a/ships/BitFifo.ship +++ b/ships/BitFifo.ship @@ -378,6 +378,12 @@ public void service() { initial bitstorage_count = 0; always @(posedge clk) begin + if (!rst) begin + bitstorage_count <= 0; + enqueue_remaining <= 0; + dequeue_remaining <= 0; + `reset + end else begin if (!in_r && in_a) in_a <= 0; if (!inOp_r && inOp_a) inOp_a <= 0; if (!outOp_r && outOp_a) outOp_a <= 0; @@ -422,6 +428,7 @@ public void service() { out_d <= (outOp_d[`OP_SIGNEXT] && bitstorage[outOp_d[`OP_DROP]]) ? 37'b1111111111111111111111111111111111111 : 0; end + end end diff --git a/ships/Choice.ship b/ships/Choice.ship index eb56a40..9309c87 100644 --- a/ships/Choice.ship +++ b/ships/Choice.ship @@ -120,6 +120,17 @@ public void service() { reg neg; always @(posedge clk) begin + if (!rst) begin + `reset + have_in1 = 0; + have_in2 = 0; + have_in = 0; + have_out1 = 0; + have_out2 = 0; + zero = 0; + pos = 0; + neg = 0; + end else begin if (!have_in1) begin `onread(in1_r, in1_a) have_in1 <= 1; reg_in1 <= in1_d; end @@ -203,6 +214,7 @@ public void service() { end end + end end diff --git a/ships/Lut3.ship b/ships/Lut3.ship index 6b68cc5..9e408c5 100644 --- a/ships/Lut3.ship +++ b/ships/Lut3.ship @@ -80,6 +80,13 @@ is considered ``bit zero''). endgenerate always @(posedge clk) begin + if (!rst) begin + have_in1 = 0; + have_in2 = 0; + have_in3 = 0; + have_inLut = 0; + `reset + end else begin if (!have_in1) begin `onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end end else @@ -102,6 +109,7 @@ is considered ``bit zero''). have_inLut = 0; end end + end end diff --git a/ships/Memory.ship b/ships/Memory.ship index 65a08b0..bf66bb0 100644 --- a/ships/Memory.ship +++ b/ships/Memory.ship @@ -261,6 +261,20 @@ module memory (clk, rst, always @(posedge clk /*or negedge rst*/) begin if (!rst) begin + +/* + in_addr_a = 1; + write_addr_a = 1; + write_data_a = 1; + stride_a <= 1; + count_a <= 1; + preload_a <= 1; + cbd_a <= 1; +*/ + out_r <= 0; + ihorn_r <= 0; + dhorn_r <= 0; + ihorn_full <= 0; dhorn_full <= 0; command_valid <= 0; diff --git a/ships/Stack.ship b/ships/Stack.ship- similarity index 99% rename from ships/Stack.ship rename to ships/Stack.ship- index 3e9871f..bd639ff 100644 --- a/ships/Stack.ship +++ b/ships/Stack.ship- @@ -79,8 +79,9 @@ the arbitration issues. == Test ==================================================== +#skip #ship stack : Stack -#ship debug : Debug +#ship stack : Debug #expect 4 #expect 3 diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java index e4fafdf..bc97213 100644 --- a/src/edu/berkeley/fleet/fpga/Fpga.java +++ b/src/edu/berkeley/fleet/fpga/Fpga.java @@ -35,13 +35,14 @@ public class Fpga extends Fleet { createShip("Alu2", "alu2a"); createShip("BitFifo", "bitfifo"); // above is the minimal ship set needed to run the regression suite, excluding "ships" tests - /* - createShip("Fifo", "fifo3"); createShip("Alu1", "alu1"); createShip("Lut3", "lut3"); - createShip("Choice", "Choice"); - createShip("Stack", "Stack"); createShip("Alu3", "alu3"); + + /* + createShip("Stack", "Stack"); + createShip("Fifo", "fifo3"); + createShip("Choice", "Choice"); */ // above is the minimal ship set needed to run the regression suite, including "ships" tests @@ -374,9 +375,22 @@ public class Fpga extends Fleet { !"execute".equals(filename) && !"memory".equals(filename) && !"fifo".equals(filename); + if (auto) { pw.println("`include \"macros.v\""); pw.println(); + + pw.print("`define reset "); + for(PumpDescription bb : sd) { + String bb_name = bb.getName(); + if (bb.isInbox()) { + pw.print(bb_name+"_a <= 1; "); + } else { + pw.print(bb_name+"_r <= 0; "); + } + } + pw.println(); + pw.println("module " + filename + "( clk, rst "); for(PumpDescription bb : sd) { String bb_name = bb.getName(); diff --git a/src/edu/berkeley/fleet/fpga/Generator.java b/src/edu/berkeley/fleet/fpga/Generator.java index f3f0adc..e41e162 100644 --- a/src/edu/berkeley/fleet/fpga/Generator.java +++ b/src/edu/berkeley/fleet/fpga/Generator.java @@ -174,6 +174,7 @@ public class Generator { public String getVerilogName() { return name; } public Value getBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); } public Assignable getAssignableBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); } + public String doReset() { return name+"<=0;"; } public void dump(PrintWriter pw) { pw.println(" reg ["+(width-1)+":0] "+name+";"); pw.println(" initial "+name+"=0;"); @@ -355,6 +356,8 @@ public class Generator { pw.println(precrap); pw.println("always @(posedge clk) begin"); pw.println(" if (!rst) begin"); + for(Latch l : latches.values()) + pw.println(l.doReset()); for(StateWire sw : statewires.values()) pw.println(sw.doReset()); for(Port p : ports.values()) { diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v index b84287f..d21a446 100644 --- a/src/edu/berkeley/fleet/fpga/main.v +++ b/src/edu/berkeley/fleet/fpga/main.v @@ -18,6 +18,7 @@ module main wire clk; assign clk = sys_clk_pin; wire break_o; + wire break; reg break_last; wire rst; assign rst = sys_rst_pin; @@ -38,7 +39,7 @@ module main wire ser_rst; reg ser_rst_r; initial ser_rst_r = 0; - assign ser_rst = rst & ser_rst_r; + assign ser_rst = (rst & ser_rst_r); wire sio_ce; wire sio_ce_x4;