From: Amir Kamil <kamil@cs.berkeley.edu>
Date: Wed, 28 Feb 2007 08:43:05 +0000 (+0100)
Subject: Add an Alu2 that uses virtual destinations instead of commands. Add an example.
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=d4b4ddf25652eec4c1a543eead3d1ba1cd45e66f;p=fleet.git

Add an Alu2 that uses virtual destinations instead of commands. Add an example.
---

diff --git a/contrib/ps3-1b.fleet b/contrib/ps3-1b.fleet
new file mode 100644
index 0000000..cf44f85
--- /dev/null
+++ b/contrib/ps3-1b.fleet
@@ -0,0 +1,52 @@
+// Problem 1 (Amir)
+//
+// Two Fifo ships contain the same number of elements. Send a combined 
+// sequence to the Debug ship such that each pair of elements is in 
+// increasing order.
+//
+// Hint: look at the ship file that defines the Alu2 ship
+//
+// Author: Amir Kamil
+//
+// Unlike the Alu2 version, no flow control/sequencing is necessary.
+
+
+#import edu.berkeley.fleet.ships
+#ship alu          : Alu2b
+#ship debug        : Debug
+#ship fifo1        : Fifo
+#ship fifo2        : Fifo
+
+#expect 1
+#expect 2
+#expect 3
+#expect 9
+#expect 8
+#expect 11
+
+// for debugging; your solution must work with any
+// set of numbers
+
+1:          sendto fifo1.in;
+3:          sendto fifo1.in;
+8:          sendto fifo1.in;
+fifo1.in:   [*] take, deliver;
+2:          sendto fifo2.in;
+9:          sendto fifo2.in;
+11:         sendto fifo2.in;
+fifo2.in:   [*] take, deliver;
+
+// your solution goes here
+
+fifo1.out:  [*] nop;
+            (*) take, sendto alu.in1.min;
+            (*) sendto alu.in1.max;
+            kill;
+fifo2.out:  [*] take, sendto alu.in2;
+alu.in1:    [*] take, deliver;
+alu.in2:    [*] nop;
+            (*) take, deliver;
+            (*) deliver;
+            kill;
+alu.out:    [*] take, sendto debug.in;
+debug.in:   [*] take, deliver;
diff --git a/ships/Alu2b.ship b/ships/Alu2b.ship
new file mode 100644
index 0000000..b4dd254
--- /dev/null
+++ b/ships/Alu2b.ship
@@ -0,0 +1,84 @@
+ship: Alu2b
+
+== Ports ===========================================================
+data  in:   in1.add
+data  in:   in1.sub
+data  in:   in1.max
+data  in:   in1.min
+
+data  in:   in2
+
+data  out:  out
+
+== Constants ========================================================
+
+== TeX ==============================================================
+This ship is a two-input arithmetic unit.  The first input is split
+into multiple virtual destinations that control the operation to be
+performed.
+
+== Fleeterpreter ====================================================
+public void service() {
+  if (!box_out.readyForDataFromShip() ||
+      !box_in1.dataReadyForShip() ||
+      !box_in2.dataReadyForShip()) return;
+
+  Packet selector = box_in1.removePacketForShip();
+  String port = selector.destination.getDestinationName();
+  long a      = selector.value;
+  long b      = box_in2.removeDataForShip();
+
+  if (port.equals("add")) {
+    box_out.addDataFromShip(a+b); // ADD
+  } else if (port.equals("sub")) {
+    box_out.addDataFromShip(a-b); // SUB
+  } else if (port.equals("max")) {
+    box_out.addDataFromShip(Math.max(a,b)); // MAX
+  } else if (port.equals("min")) {
+    box_out.addDataFromShip(Math.min(a,b)); // MIN
+  } else {
+    box_out.addDataFromShip(0);
+  }
+}
+
+== FleetSim ==============================================================
+
+== FPGA ==============================================================
+
+  reg                    have_a;
+  reg [(`PACKET_WIDTH-1):0] reg_a;
+  reg                    have_b;
+  reg [(`DATAWIDTH-1):0] reg_b;
+
+  reg a_val;
+
+  always @(posedge clk) begin
+    if (!have_a) begin
+      `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
+      end
+    if (!have_b) begin
+      `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
+      end
+  
+    if (have_a && have_b) begin
+      a_val = reg_a[`DATAWIDTH-1:0];
+      case (reg_a[`PACKET_WIDTH-1:`DATAWIDTH])
+        0: out_d = a_val + reg_b;
+        1: out_d = a_val - reg_b;
+        2: out_d = a_val > reg_b ? a_val : reg_b;
+        3: out_d = a_val > reg_b ? reg_b : a_val;
+        default: out_d = 0;
+      endcase        
+      `onwrite(out_r, out_a)
+        have_a  = 0;
+        have_b  = 0;
+      end
+    end
+  end
+
+
+
+
+== Contributors =========================================================
+Adam Megacz <megacz@cs.berkeley.edu>
+Amir Kamil  <kamil@cs.berkeley.edu>