From: adam <adam@megacz.com>
Date: Mon, 10 Nov 2008 12:36:56 +0000 (+0100)
Subject: re-enable bitgen DRC, disable unused ddr2 signals
X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=e6a2f5ae76197f919749ae6bd5c19737b2ee0e9a;p=fleet.git

re-enable bitgen DRC, disable unused ddr2 signals
---

diff --git a/Makefile b/Makefile
index 440b295..9e8b284 100644
--- a/Makefile
+++ b/Makefile
@@ -148,7 +148,7 @@ synth:
 	$(xilinx_ise)ngdbuild -aul -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd
 	$(xilinx_ise)map -cm area -intstyle xflow -p $(device) -pr b -ol high -o main_map.ncd main.ngd main.pcf
 	$(xilinx_ise)par -w -intstyle xflow -t 99 -pl high -rl high main_map.ncd main.ncd main.pcf
-	$(xilinx_ise)bitgen -intstyle xflow -d -f main.ut main.ncd
+	$(xilinx_ise)bitgen -intstyle xflow -f main.ut main.ncd
 #	$(xilinx_ise)trce -intstyle xflow -e 3 -l 3 -s ${speed_grade} -xml main main.ncd -o main.twr main.pcf
 	$(xilinx_edk)xmd -tcl $(remote_edk)/data/xmd/genace.tcl -jprog -hw main.bit -board ml410 -ace mainx.ace
 	mv build/fpga/mainx.ace build/fpga/main.ace   # genace throws a fit if the filename prefix is the same?
diff --git a/src/edu/berkeley/fleet/fpga/main.ucf b/src/edu/berkeley/fleet/fpga/main.ucf
index e54b260..dd91600 100644
--- a/src/edu/berkeley/fleet/fpga/main.ucf
+++ b/src/edu/berkeley/fleet/fpga/main.ucf
@@ -782,229 +782,229 @@ Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> TIG;
 
 #### Module DDR2_SDRAM constraints
 
-Net ddr2_ODT_pin LOC=AA25;
-Net ddr2_ODT_pin IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<0> LOC=H28;
-Net ddr2_Addr_pin<0> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<1> LOC=K28;
-Net ddr2_Addr_pin<1> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<2> LOC=L28;
-Net ddr2_Addr_pin<2> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<3> LOC=M25;
-Net ddr2_Addr_pin<3> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<4> LOC=Y24;
-Net ddr2_Addr_pin<4> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<5> LOC=N27;
-Net ddr2_Addr_pin<5> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<6> LOC=AD26;
-Net ddr2_Addr_pin<6> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<7> LOC=AC25;
-Net ddr2_Addr_pin<7> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<8> LOC=R26;
-Net ddr2_Addr_pin<8> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<9> LOC=R28;
-Net ddr2_Addr_pin<9> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<10> LOC=T26;
-Net ddr2_Addr_pin<10> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<11> LOC=T28;
-Net ddr2_Addr_pin<11> IOSTANDARD = SSTL18_I;
-Net ddr2_Addr_pin<12> LOC=U27;
-Net ddr2_Addr_pin<12> IOSTANDARD = SSTL18_I;
-Net ddr2_BankAddr_pin<0> LOC=V28;
-Net ddr2_BankAddr_pin<0> IOSTANDARD = SSTL18_I;
-Net ddr2_BankAddr_pin<1> LOC=W26;
-Net ddr2_BankAddr_pin<1> IOSTANDARD = SSTL18_I;
-Net ddr2_CAS_n_pin LOC=R31;
-Net ddr2_CAS_n_pin IOSTANDARD = SSTL18_I;
-Net ddr2_CE_pin LOC=AJ31;
-Net ddr2_CE_pin IOSTANDARD = SSTL18_I;
-Net ddr2_CS_n_pin LOC=AJ30;
-Net ddr2_CS_n_pin IOSTANDARD = SSTL18_I;
-Net ddr2_RAS_n_pin LOC=R32;
-Net ddr2_RAS_n_pin IOSTANDARD = SSTL18_I;
-Net ddr2_WE_n_pin LOC=T31;
-Net ddr2_WE_n_pin IOSTANDARD = SSTL18_I;
-Net ddr2_DM_pin<0> LOC=AH30;
-Net ddr2_DM_pin<0> IOSTANDARD = SSTL18_II;
-Net ddr2_DM_pin<1> LOC=M31;
-Net ddr2_DM_pin<1> IOSTANDARD = SSTL18_II;
-Net ddr2_DM_pin<2> LOC=T30;
-Net ddr2_DM_pin<2> IOSTANDARD = SSTL18_II;
-Net ddr2_DM_pin<3> LOC=U28;
-Net ddr2_DM_pin<3> IOSTANDARD = SSTL18_II;
-Net ddr2_DM_pin<4> LOC=AJ32;
-Net ddr2_DM_pin<4> IOSTANDARD = SSTL18_II;
-Net ddr2_DM_pin<5> LOC=AG31;
-Net ddr2_DM_pin<5> IOSTANDARD = SSTL18_II;
-Net ddr2_DM_pin<6> LOC=AG30;
-Net ddr2_DM_pin<6> IOSTANDARD = SSTL18_II;
-Net ddr2_DM_pin<7> LOC=AF29;
-Net ddr2_DM_pin<7> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS<0> LOC=F29;
-Net ddr2_DQS<0> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS<1> LOC=K29;
-Net ddr2_DQS<1> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS<2> LOC=P27;
-Net ddr2_DQS<2> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS<3> LOC=P32;
-Net ddr2_DQS<3> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS<4> LOC=W27;
-Net ddr2_DQS<4> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS<5> LOC=W31;
-Net ddr2_DQS<5> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS<6> LOC=AG32;
-Net ddr2_DQS<6> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS<7> LOC=AE32;
-Net ddr2_DQS<7> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS_n<0> LOC=E29;
-Net ddr2_DQS_n<0> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS_n<1> LOC=J29;
-Net ddr2_DQS_n<1> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS_n<2> LOC=P26;
-Net ddr2_DQS_n<2> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS_n<3> LOC=N32;
-Net ddr2_DQS_n<3> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS_n<4> LOC=V27;
-Net ddr2_DQS_n<4> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS_n<5> LOC=W30;
-Net ddr2_DQS_n<5> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS_n<6> LOC=AH32;
-Net ddr2_DQS_n<6> IOSTANDARD = SSTL18_II;
-Net ddr2_DQS_n<7> LOC=AE31;
-Net ddr2_DQS_n<7> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<0> LOC=C32;
-Net ddr2_DQ<0> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<1> LOC=D32;
-Net ddr2_DQ<1> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<2> LOC=E32;
-Net ddr2_DQ<2> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<3> LOC=G32;
-Net ddr2_DQ<3> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<4> LOC=H32;
-Net ddr2_DQ<4> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<5> LOC=J32;
-Net ddr2_DQ<5> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<6> LOC=K32;
-Net ddr2_DQ<6> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<7> LOC=M32;
-Net ddr2_DQ<7> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<8> LOC=N28;
-Net ddr2_DQ<8> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<9> LOC=D31;
-Net ddr2_DQ<9> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<10> LOC=E31;
-Net ddr2_DQ<10> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<11> LOC=F31;
-Net ddr2_DQ<11> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<12> LOC=G31;
-Net ddr2_DQ<12> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<13> LOC=J31;
-Net ddr2_DQ<13> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<14> LOC=K31;
-Net ddr2_DQ<14> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<15> LOC=L31;
-Net ddr2_DQ<15> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<16> LOC=C30;
-Net ddr2_DQ<16> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<17> LOC=D30;
-Net ddr2_DQ<17> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<18> LOC=F30;
-Net ddr2_DQ<18> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<19> LOC=G30;
-Net ddr2_DQ<19> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<20> LOC=Y28;
-Net ddr2_DQ<20> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<21> LOC=Y27;
-Net ddr2_DQ<21> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<22> LOC=L30;
-Net ddr2_DQ<22> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<23> LOC=M30;
-Net ddr2_DQ<23> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<24> LOC=N30;
-Net ddr2_DQ<24> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<25> LOC=C29;
-Net ddr2_DQ<25> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<26> LOC=D29;
-Net ddr2_DQ<26> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<27> LOC=J30;
-Net ddr2_DQ<27> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<28> LOC=L29;
-Net ddr2_DQ<28> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<29> LOC=N29;
-Net ddr2_DQ<29> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<30> LOC=P29;
-Net ddr2_DQ<30> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<31> LOC=R29;
-Net ddr2_DQ<31> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<32> LOC=T29;
-Net ddr2_DQ<32> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<33> LOC=U32;
-Net ddr2_DQ<33> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<34> LOC=V32;
-Net ddr2_DQ<34> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<35> LOC=W32;
-Net ddr2_DQ<35> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<36> LOC=Y32;
-Net ddr2_DQ<36> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<37> LOC=AB32;
-Net ddr2_DQ<37> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<38> LOC=AC32;
-Net ddr2_DQ<38> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<39> LOC=AD32;
-Net ddr2_DQ<39> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<40> LOC=AB27;
-Net ddr2_DQ<40> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<41> LOC=U31;
-Net ddr2_DQ<41> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<42> LOC=W25;
-Net ddr2_DQ<42> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<43> LOC=Y31;
-Net ddr2_DQ<43> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<44> LOC=AA31;
-Net ddr2_DQ<44> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<45> LOC=AB31;
-Net ddr2_DQ<45> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<46> LOC=AD31;
-Net ddr2_DQ<46> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<47> LOC=AB28;
-Net ddr2_DQ<47> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<48> LOC=AF31;
-Net ddr2_DQ<48> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<49> LOC=U30;
-Net ddr2_DQ<49> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<50> LOC=V30;
-Net ddr2_DQ<50> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<51> LOC=Y26;
-Net ddr2_DQ<51> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<52> LOC=AA30;
-Net ddr2_DQ<52> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<53> LOC=AB30;
-Net ddr2_DQ<53> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<54> LOC=AC30;
-Net ddr2_DQ<54> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<55> LOC=AD30;
-Net ddr2_DQ<55> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<56> LOC=AF30;
-Net ddr2_DQ<56> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<57> LOC=V29;
-Net ddr2_DQ<57> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<58> LOC=W29;
-Net ddr2_DQ<58> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<59> LOC=Y29;
-Net ddr2_DQ<59> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<60> LOC=AA29;
-Net ddr2_DQ<60> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<61> LOC=AC29;
-Net ddr2_DQ<61> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<62> LOC=AD29;
-Net ddr2_DQ<62> IOSTANDARD = SSTL18_II;
-Net ddr2_DQ<63> LOC=AE29;
-Net ddr2_DQ<63> IOSTANDARD = SSTL18_II;
-Net ddr2_Clk_pin LOC=H30;
-Net ddr2_Clk_pin IOSTANDARD = SSTL18_II;
-Net ddr2_Clk_n_pin LOC=H29;
-Net ddr2_Clk_n_pin IOSTANDARD = SSTL18_II;
-
+# Net ddr2_ODT_pin LOC=AA25;
+# Net ddr2_ODT_pin IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<0> LOC=H28;
+# Net ddr2_Addr_pin<0> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<1> LOC=K28;
+# Net ddr2_Addr_pin<1> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<2> LOC=L28;
+# Net ddr2_Addr_pin<2> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<3> LOC=M25;
+# Net ddr2_Addr_pin<3> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<4> LOC=Y24;
+# Net ddr2_Addr_pin<4> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<5> LOC=N27;
+# Net ddr2_Addr_pin<5> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<6> LOC=AD26;
+# Net ddr2_Addr_pin<6> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<7> LOC=AC25;
+# Net ddr2_Addr_pin<7> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<8> LOC=R26;
+# Net ddr2_Addr_pin<8> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<9> LOC=R28;
+# Net ddr2_Addr_pin<9> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<10> LOC=T26;
+# Net ddr2_Addr_pin<10> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<11> LOC=T28;
+# Net ddr2_Addr_pin<11> IOSTANDARD = SSTL18_I;
+# Net ddr2_Addr_pin<12> LOC=U27;
+# Net ddr2_Addr_pin<12> IOSTANDARD = SSTL18_I;
+# Net ddr2_BankAddr_pin<0> LOC=V28;
+# Net ddr2_BankAddr_pin<0> IOSTANDARD = SSTL18_I;
+# Net ddr2_BankAddr_pin<1> LOC=W26;
+# Net ddr2_BankAddr_pin<1> IOSTANDARD = SSTL18_I;
+# Net ddr2_CAS_n_pin LOC=R31;
+# Net ddr2_CAS_n_pin IOSTANDARD = SSTL18_I;
+# Net ddr2_CE_pin LOC=AJ31;
+# Net ddr2_CE_pin IOSTANDARD = SSTL18_I;
+# Net ddr2_CS_n_pin LOC=AJ30;
+# Net ddr2_CS_n_pin IOSTANDARD = SSTL18_I;
+# Net ddr2_RAS_n_pin LOC=R32;
+# Net ddr2_RAS_n_pin IOSTANDARD = SSTL18_I;
+# Net ddr2_WE_n_pin LOC=T31;
+# Net ddr2_WE_n_pin IOSTANDARD = SSTL18_I;
+# Net ddr2_DM_pin<0> LOC=AH30;
+# Net ddr2_DM_pin<0> IOSTANDARD = SSTL18_II;
+# Net ddr2_DM_pin<1> LOC=M31;
+# Net ddr2_DM_pin<1> IOSTANDARD = SSTL18_II;
+# Net ddr2_DM_pin<2> LOC=T30;
+# Net ddr2_DM_pin<2> IOSTANDARD = SSTL18_II;
+# Net ddr2_DM_pin<3> LOC=U28;
+# Net ddr2_DM_pin<3> IOSTANDARD = SSTL18_II;
+# Net ddr2_DM_pin<4> LOC=AJ32;
+# Net ddr2_DM_pin<4> IOSTANDARD = SSTL18_II;
+# Net ddr2_DM_pin<5> LOC=AG31;
+# Net ddr2_DM_pin<5> IOSTANDARD = SSTL18_II;
+# Net ddr2_DM_pin<6> LOC=AG30;
+# Net ddr2_DM_pin<6> IOSTANDARD = SSTL18_II;
+# Net ddr2_DM_pin<7> LOC=AF29;
+# Net ddr2_DM_pin<7> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS<0> LOC=F29;
+# Net ddr2_DQS<0> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS<1> LOC=K29;
+# Net ddr2_DQS<1> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS<2> LOC=P27;
+# Net ddr2_DQS<2> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS<3> LOC=P32;
+# Net ddr2_DQS<3> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS<4> LOC=W27;
+# Net ddr2_DQS<4> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS<5> LOC=W31;
+# Net ddr2_DQS<5> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS<6> LOC=AG32;
+# Net ddr2_DQS<6> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS<7> LOC=AE32;
+# Net ddr2_DQS<7> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS_n<0> LOC=E29;
+# Net ddr2_DQS_n<0> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS_n<1> LOC=J29;
+# Net ddr2_DQS_n<1> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS_n<2> LOC=P26;
+# Net ddr2_DQS_n<2> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS_n<3> LOC=N32;
+# Net ddr2_DQS_n<3> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS_n<4> LOC=V27;
+# Net ddr2_DQS_n<4> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS_n<5> LOC=W30;
+# Net ddr2_DQS_n<5> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS_n<6> LOC=AH32;
+# Net ddr2_DQS_n<6> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQS_n<7> LOC=AE31;
+# Net ddr2_DQS_n<7> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<0> LOC=C32;
+# Net ddr2_DQ<0> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<1> LOC=D32;
+# Net ddr2_DQ<1> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<2> LOC=E32;
+# Net ddr2_DQ<2> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<3> LOC=G32;
+# Net ddr2_DQ<3> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<4> LOC=H32;
+# Net ddr2_DQ<4> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<5> LOC=J32;
+# Net ddr2_DQ<5> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<6> LOC=K32;
+# Net ddr2_DQ<6> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<7> LOC=M32;
+# Net ddr2_DQ<7> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<8> LOC=N28;
+# Net ddr2_DQ<8> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<9> LOC=D31;
+# Net ddr2_DQ<9> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<10> LOC=E31;
+# Net ddr2_DQ<10> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<11> LOC=F31;
+# Net ddr2_DQ<11> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<12> LOC=G31;
+# Net ddr2_DQ<12> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<13> LOC=J31;
+# Net ddr2_DQ<13> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<14> LOC=K31;
+# Net ddr2_DQ<14> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<15> LOC=L31;
+# Net ddr2_DQ<15> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<16> LOC=C30;
+# Net ddr2_DQ<16> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<17> LOC=D30;
+# Net ddr2_DQ<17> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<18> LOC=F30;
+# Net ddr2_DQ<18> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<19> LOC=G30;
+# Net ddr2_DQ<19> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<20> LOC=Y28;
+# Net ddr2_DQ<20> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<21> LOC=Y27;
+# Net ddr2_DQ<21> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<22> LOC=L30;
+# Net ddr2_DQ<22> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<23> LOC=M30;
+# Net ddr2_DQ<23> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<24> LOC=N30;
+# Net ddr2_DQ<24> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<25> LOC=C29;
+# Net ddr2_DQ<25> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<26> LOC=D29;
+# Net ddr2_DQ<26> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<27> LOC=J30;
+# Net ddr2_DQ<27> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<28> LOC=L29;
+# Net ddr2_DQ<28> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<29> LOC=N29;
+# Net ddr2_DQ<29> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<30> LOC=P29;
+# Net ddr2_DQ<30> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<31> LOC=R29;
+# Net ddr2_DQ<31> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<32> LOC=T29;
+# Net ddr2_DQ<32> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<33> LOC=U32;
+# Net ddr2_DQ<33> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<34> LOC=V32;
+# Net ddr2_DQ<34> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<35> LOC=W32;
+# Net ddr2_DQ<35> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<36> LOC=Y32;
+# Net ddr2_DQ<36> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<37> LOC=AB32;
+# Net ddr2_DQ<37> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<38> LOC=AC32;
+# Net ddr2_DQ<38> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<39> LOC=AD32;
+# Net ddr2_DQ<39> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<40> LOC=AB27;
+# Net ddr2_DQ<40> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<41> LOC=U31;
+# Net ddr2_DQ<41> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<42> LOC=W25;
+# Net ddr2_DQ<42> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<43> LOC=Y31;
+# Net ddr2_DQ<43> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<44> LOC=AA31;
+# Net ddr2_DQ<44> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<45> LOC=AB31;
+# Net ddr2_DQ<45> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<46> LOC=AD31;
+# Net ddr2_DQ<46> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<47> LOC=AB28;
+# Net ddr2_DQ<47> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<48> LOC=AF31;
+# Net ddr2_DQ<48> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<49> LOC=U30;
+# Net ddr2_DQ<49> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<50> LOC=V30;
+# Net ddr2_DQ<50> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<51> LOC=Y26;
+# Net ddr2_DQ<51> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<52> LOC=AA30;
+# Net ddr2_DQ<52> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<53> LOC=AB30;
+# Net ddr2_DQ<53> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<54> LOC=AC30;
+# Net ddr2_DQ<54> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<55> LOC=AD30;
+# Net ddr2_DQ<55> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<56> LOC=AF30;
+# Net ddr2_DQ<56> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<57> LOC=V29;
+# Net ddr2_DQ<57> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<58> LOC=W29;
+# Net ddr2_DQ<58> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<59> LOC=Y29;
+# Net ddr2_DQ<59> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<60> LOC=AA29;
+# Net ddr2_DQ<60> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<61> LOC=AC29;
+# Net ddr2_DQ<61> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<62> LOC=AD29;
+# Net ddr2_DQ<62> IOSTANDARD = SSTL18_II;
+# Net ddr2_DQ<63> LOC=AE29;
+# Net ddr2_DQ<63> IOSTANDARD = SSTL18_II;
+# Net ddr2_Clk_pin LOC=H30;
+# Net ddr2_Clk_pin IOSTANDARD = SSTL18_II;
+# Net ddr2_Clk_n_pin LOC=H29;
+# Net ddr2_Clk_n_pin IOSTANDARD = SSTL18_II;
+# 
 #### Module DDR_SDRAM constraints
 
 Net ddr1_Addr_pin<12> LOC=J24;
diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
index 921a40e..069e898 100644
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ b/src/edu/berkeley/fleet/fpga/main.v
@@ -19,7 +19,7 @@ module main
   ddr1_DM_pin,
   ddr1_DQS,
   ddr1_DQ,
-
+/*
   ddr2_ODT_pin,
   ddr2_Clk_pin,
   ddr2_Clk_n_pin,
@@ -34,7 +34,7 @@ module main
   ddr2_DQS,
   ddr2_DQS_n,
   ddr2_DQ,
-
+*/
   vga_psave,
   vga_hsync,
   vga_vsync,
@@ -67,7 +67,7 @@ module main
   output [3:0]  ddr1_DM_pin;
   inout  [3:0]  ddr1_DQS;
   inout  [31:0] ddr1_DQ;
-
+/*
   output        ddr2_ODT_pin;
   output        ddr2_Clk_pin;
   output        ddr2_Clk_n_pin;
@@ -82,7 +82,7 @@ module main
   inout  [7:0]  ddr2_DQS;
   inout  [7:0]  ddr2_DQS_n;
   inout  [63:0] ddr2_DQ;
-
+*/
   wire  [31:0]  dram_addr;
   wire          dram_addr_r;
   wire          dram_addr_a;
@@ -95,6 +95,7 @@ module main
   wire          dram_read_data_empty;
   wire   [1:0]  dram_read_data_latency;
 
+/*
   wire  [31:0]  ddr2_addr;
   wire          ddr2_addr_r;
   wire          ddr2_addr_a;
@@ -106,6 +107,7 @@ module main
   wire          ddr2_read_data_pop;
   wire          ddr2_read_data_empty;
   wire   [1:0]  ddr2_read_data_latency;
+*/
 
   output vga_psave;
   output vga_hsync;