From: adam Date: Wed, 27 Aug 2008 17:28:26 +0000 (-0700) Subject: 27-aug update X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=eab0ee82e389ca81ebbd9e3d0bae6c8831d4b49d;p=fleet.git 27-aug update darcs-hash:20080827172826-5007d-f8587008c53c93879c351aae159b581e37416146.gz --- diff --git a/am33.tex b/am33.tex index 649f878..0486704 100644 --- a/am33.tex +++ b/am33.tex @@ -66,10 +66,16 @@ Adam Megacz Changes: \begin{tabular}{rl} -\color{red}09-Jul -& \color{red} Fixed a few typos \\ -& \color{red} Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\ -& \color{red} Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\ +27-Aug +& \color{red} Note that decision to requeue is based on value of OLC {\it before} execution\\ +10-Jul +& Added {\tt OLC=0} predicate \\ +& Eliminated {\tt TAPL} (made possible by previous change) \\ +& Expanded {\tt set} {\tt Immediate} field from 13 bits to 14 bits (made possible by previous change)\\ +09-Jul +& Fixed a few typos \\ +& Added {\tt DataLatch}\to{\tt TAPL} (Amir's request) \\ +& Eliminate ability to predicate directly on {\tt C}-flag (Ivan's request) \\ 16-Jun & When a torpedo strikes, {\tt ILC} is set to {\tt 1} \\ & Only {\tt move} can be torpedoed (removed {\tt I}-bit from {\tt set}/{\tt shift}) \\ @@ -281,11 +287,6 @@ A token sent to an instruction destination is called a {\it torpedo}. When a torpedo arrives at the tail of {\tt EF}, it is deposited in a waiting area (not shown) rather than being enqueued into {\tt EF}. -There is a latch (not shown) called the {\it torpedo acknowledgment path - latch} ({\tt TAPL}) which stores a path. When a torpedo is consumed -(see section ``On Deck''), a token is sent along the path held in this -latch. - \subsection{Format of an Instruction} All instruction words have the following format: @@ -394,8 +395,8 @@ Code & Execute & if \\\hline {\tt 001:} & {\tt OLC$\neq$0} & and {\tt A=1} \\ {\tt 010:} & {\tt OLC$\neq$0} & and {\tt B=0} \\ {\tt 011:} & {\tt OLC$\neq$0} & and {\tt B=1} \\ -{\tt 100:} & \color{red}Unused\color{black} & \\ -{\tt 101:} & \color{red}Unused\color{black} & \\ +{\tt 100:} & Unused & \\ +{\tt 101:} & {\tt OLC=0} & \\ {\tt 110:} & {\tt OLC$\neq$0} & \\ {\tt 111:} & always & \\ \hline\end{tabular} @@ -412,9 +413,10 @@ processes have completed: \item Requeueing: \begin{itemize} - \item If the outer loop counter is zero ({\tt OLC=0}) or the - instruction on deck is a one-shot instruction ({\tt - OS=1}), do nothing. + \item If the outer loop counter is zero ({\tt OLC=0}) + \color{red}{\it before executing the + instruction}\color{black}\ or the instruction on deck is a + one-shot instruction ({\tt OS=1}), do nothing. \item {\it Otherwise} wait for the hatch to be sealed and enqueue a copy of the instruction currently on deck. \end{itemize} @@ -431,8 +433,7 @@ processes have completed: and a torpedo is present in the waiting area: consume the torpedo, set the outer loop counter to zero ({\tt OLC=0}), set the inner loop counter to one ({\tt ILC=1}), - unseal the hatch, and transmit a token along in the - {\it torpedo acknowledgment path latch} ({\tt TAPL}). + unseal the hatch. \item {\it Otherwise} if {\tt ILC$\neq$0} or the instruction is {\it @@ -447,7 +448,7 @@ processes have completed: \pagebreak \section{Instructions} -The dock supports \color{red}four\color{black}\ instructions: +The dock supports four instructions: {\tt move} (variants: {\tt moveto}, {\tt dispatch}), {\tt shift}, {\tt set}, and @@ -553,109 +554,92 @@ counter, outer loop counter, and data latch. \end{bytefield}} \begin{bytefield}{26} - \bitheader[b]{0,5,11-18}\\ + \bitheader[b]{0,5,12-18}\\ \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt OLC}} \bitbox[r]{1}{} - \bitbox{5}{\tt 10000} + \bitbox{4}{\tt 1000\color{black}} \bitbox{3}{\tt 100} - \bitbox{5}{} + \bitbox{6}{} \bitbox{6}{\tt Immediate} \end{bytefield} \begin{bytefield}{26} - \bitheader[b]{11-18}\\ + \bitheader[b]{12-18}\\ \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt OLC}} \bitbox[r]{1}{} - \bitbox{5}{\tt 10000} + \bitbox{4}{\tt 1000\color{black}} \bitbox{3}{\tt 010} - \bitbox{11}{} + \bitbox{12}{} \end{bytefield} \begin{bytefield}{26} - \bitheader[b]{11-18}\\ + \bitheader[b]{12-18}\\ \bitbox[1]{6}{\raggedleft {\tt OLC-1}\to{\tt OLC}} \bitbox[r]{1}{} - \bitbox{5}{\tt 10000} + \bitbox{4}{\tt 1000\color{black}} \bitbox{3}{\tt 001} - \bitbox{11}{} + \bitbox{12}{} \end{bytefield} \begin{bytefield}{26} - \bitheader[b]{0,5,6,11-18}\\ + \bitheader[b]{0,5,6,12-18}\\ \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt ILC}} \bitbox[r]{1}{} - \bitbox{5}{\tt 01000} + \bitbox{4}{\tt 0100\color{black}} \bitbox{3}{\tt 100} - \bitbox{4}{} + \bitbox{5}{} \bitbox{1}{\tt 0} \bitbox{6}{\tt Immediate} \end{bytefield} \begin{bytefield}{26} - \bitheader[b]{6,11-18}\\ + \bitheader[b]{6,12-18}\\ \bitbox[1]{6}{\raggedleft $\infty$\to{\tt ILC}} \bitbox[r]{1}{} - \bitbox{5}{\tt 01000} + \bitbox{4}{\tt 0100\color{black}} \bitbox{3}{\tt 100} - \bitbox{4}{} + \bitbox{5}{} \bitbox{1}{\tt 1} \bitbox{6}{} \end{bytefield} \begin{bytefield}{26} - \bitheader[b]{11-18}\\ + \bitheader[b]{12-18}\\ \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt ILC}} \bitbox[r]{1}{} - \bitbox{5}{\tt 01000} + \bitbox{4}{\tt 0100\color{black}} \bitbox{3}{\tt 010} - \bitbox{11}{} + \bitbox{12}{} \end{bytefield} \begin{bytefield}{26} - \bitheader[b]{0,12,13-18}\\ + \bitheader[b]{0,13-18}\\ \bitbox[1]{6}{\raggedleft \footnotesize {\tt 0-Extended Immediate}\to{\tt Data Latch}} \bitbox[r]{1}{} - \bitbox{5}{\tt 00100} + \bitbox{4}{\tt 0010\color{black}} \bitbox{1}{\tt 0} - \bitbox{13}{\tt Immediate} + \bitbox{14}{\tt Immediate} \end{bytefield} \begin{bytefield}{26} - \bitheader[b]{0,12,13-18}\\ + \bitheader[b]{0,13-18}\\ \bitbox[1]{6}{\raggedleft \footnotesize {\tt 1-Extended Immediate}\to{\tt Data Latch}} \bitbox[r]{1}{} - \bitbox{5}{\tt 00100} + \bitbox{4}{\tt 0010\color{black}} \bitbox{1}{\tt 1} - \bitbox{13}{\tt Immediate} + \bitbox{14}{\tt Immediate} \end{bytefield} \begin{bytefield}{26} - \bitheader[b]{0,5,6,11,14-18}\\ + \bitheader[b]{0,5,6,11,15-18}\\ \bitbox[1]{6}{\raggedleft {\tt Update Flags}} \bitbox[r]{1}{} - \bitbox{5}{\tt 00010} - \bitbox{2}{} + \bitbox{4}{\tt 0001\color{black}} + \bitbox{3}{} \bitbox{6}{\tt nextA} \bitbox{6}{\tt nextB} \end{bytefield} -\begin{bytefield}{26} - \bitheader[b]{0,12,14-18}\\ - \bitbox[1]{6}{\raggedleft {\tt Immediate}\to{\tt TAPL}} - \bitbox[r]{1}{} - \bitbox{6}{\tt 000010} - \bitbox{13}{\tt Immediate} -\end{bytefield} - -\color{red} -\begin{bytefield}{26} - \bitheader[b]{0,12,14-18}\\ - \bitbox[1]{6}{\raggedleft {\tt Data Latch}\to{\tt TAPL}} - \bitbox[r]{1}{} - \bitbox{6}{\tt 000001} - \bitbox{13}{} -\end{bytefield} -\color{black} \color{black}