From: Adam Megacz Date: Tue, 24 Mar 2009 22:09:41 +0000 (+0000) Subject: update marina.xml and marina.spi X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=f064717352dba0b8ec16e682aac7948480946f8e;p=fleet.git update marina.xml and marina.spi --- diff --git a/testCode/marina.spi b/testCode/marina.spi index 19e98d4..03d2e04 100644 --- a/testCode/marina.spi +++ b/testCode/marina.spi @@ -1,7 +1,7 @@ *** SPICE deck for cell marinaOut{sch} from library aMarinaM *** Created on Mon Nov 17, 2008 08:47:24 -*** Last revised on Sun Mar 22, 2009 13:04:28 -*** Written on Sun Mar 22, 2009 13:04:40 by Electric VLSI Design System, +*** Last revised on Sun Mar 22, 2009 16:27:39 +*** Written on Tue Mar 24, 2009 15:09:00 by Electric VLSI Design System, *version 8.08k *** Layout tech: cmos90, foundry TSMC *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF @@ -1117,11 +1117,11 @@ Xwire@0 a b wire-C_0_011f-218_4-R_34_667m .ENDS wire90-218_4-layer_1-width_3 *** CELL: scanM:scanCellE{sch} -.SUBCKT scanM__scanCellE dIn[1] p1p p2p rd sin sout +.SUBCKT scanCellE dIn[1] p1p p2p rd sin sout Xlatch1in@0 p2p sin net@2 latch1in10A Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3 -.ENDS scanM__scanCellE +.ENDS scanCellE *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-297_6-R_34_667m a b @@ -1142,8 +1142,8 @@ Xwire@0 a b wire-C_0_011f-297_6-R_34_667m *** CELL: scanM:scanEx2{sch} .SUBCKT scanEx2 dIn[1] dIn[2] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] +sir[7] sir[8] sor[1] -XscanCell@3 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanM__scanCellE -XscanCell@4 dIn[2] sir[3] sir[2] sir[5] net@27 sor[1] scanM__scanCellE +XscanCell@3 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanCellE +XscanCell@4 dIn[2] sir[3] sir[2] sir[5] net@27 sor[1] scanCellE Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3 .ENDS scanEx2 @@ -1282,17 +1282,10 @@ Xwire90@1 net@18 net@16 wire90-242_1-layer_1-width_3 Xwire90@2 net@19 net@17 wire90-555_8-layer_1-width_3 .ENDS latch2in60C -*** CELL: scanJ:scanCellE{sch} -.SUBCKT scanJ__scanCellE dIn[1] p1p p2p rd sin sout -Xlatch1in@0 p2p sin net@2 latch1in10A -Xlatch2in@0 p1p rd net@10 dIn[1] sout latch2in10Alo -Xwire90@0 net@2 net@10 wire90-218_4-layer_1-width_3 -.ENDS scanJ__scanCellE - *** CELL: latchGroupsK:latchWscM2{sch} .SUBCKT latchWscM2 hcl in[1] out[1] p1p p2p rd sin sout wr Xhi2inLat@1 hcl wr in[1] sout out[1] latch2in60C -XscanCell@2 out[1] p1p p2p rd sin sout scanJ__scanCellE +XscanCell@3 out[1] p1p p2p rd sin sout scanCellE .ENDS latchWscM2 *** CELL: registersM:addr1in60Cx7scan{sch} @@ -1510,8 +1503,8 @@ Xwire@0 a b wire-C_0_011f-1177-R_34_667m +so[1] wr[A] wr[D] XdataDriv@2 so[1] si[4] wr[D] dataDriver60 XdataDriv@3 net@4 net@21 wr[A] dataDriver60 -XscanCell@2 scanCell@2_dIn[1] si[3] si[2] si[5] si[1] net@7 scanM__scanCellE -XscanCell@3 scanCell@3_dIn[1] si[3] si[2] si[5] net@4 so[1] scanM__scanCellE +XscanCell@2 scanCell@2_dIn[1] si[3] si[2] si[5] si[1] net@7 scanCellE +XscanCell@3 scanCell@3_dIn[1] si[3] si[2] si[5] net@4 so[1] scanCellE Xwire90@0 net@7 net@4 wire90-918_6-layer_1-width_3 Xwire90@1 net@21 si[4] wire90-1177-layer_1-width_3 .ENDS fillScanControl @@ -1660,14 +1653,14 @@ Rres@3 net@8 net@11 0.809 Xwire@0 a b wire-C_0_011f-70-R_34_667m .ENDS wire90-70-layer_1-width_3 -*** CELL: scanJ:scanAmp{sch} +*** CELL: scanM:scanAmp{sch} .SUBCKT scanAmp in[1] out[1] Xinv@0 in[1] net@1 inv-X_10 Xinv@1 net@2 out[1] inv-X_20 Xwire90@0 net@1 net@2 wire90-70-layer_1-width_3 .ENDS scanAmp -*** CELL: gaspM:scanAMPx5{sch} +*** CELL: scanM:scanAMPx5{sch} .SUBCKT scanAMPx5 si[1] si[2] si[3] si[4] si[5] si[6] si[7] si[8] si[9] so[1] +so[2] so[3] so[4] so[5] Xsa[1] si[1] so[1] scanAmp @@ -1731,9 +1724,9 @@ XlatchWsc@0 net@0 in[19] out[19] sx[3] sx[2] sx[5] net@65 net@64 sx[D] +latchWscM2 XlatchWsc@1 net@13 ain[TT] aout[TT] sx[3] sx[2] sx[5] sy[1] net@61 sx[A] +latchWscM2 -XscanAMPx@0 sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] +XscanAMPx@2 sid[1] sid[2] sid[3] sid[4] sid[5] sid[6] sid[7] sid[8] sid[9] +sx[1] sx[2] sx[3] sx[4] sx[5] scanAMPx5 -XscanAMPx@1 sz[1] sx[2] sx[3] sx[4] sx[5] sid[6] sid[7] sid[8] sid[9] sod[1] +XscanAMPx@3 sz[1] sx[2] sx[3] sx[4] sx[5] sid[6] sid[7] sid[8] sid[9] sod[1] +sod[2] sod[3] sod[4] sod[5] scanAMPx5 XscanEx2@0 s[1] s[2] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] +sir[8] sor[1] scanEx2 @@ -2113,11 +2106,11 @@ Xwire90@0 net@8 net@10 wire90-602_3-layer_1-width_3 Xwire90@1 net@30 fire wire90-602_3-layer_1-width_3 .ENDS gaspWeak -*** CELL: scanJ:scanEx1vertA{sch} -.SUBCKT scanEx1vertA dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sor[1] -XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanJ__scanCellE -.ENDS scanEx1vertA +*** CELL: scanM:scanEx1{sch} +.SUBCKT scanEx1 dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] +XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanCellE +.ENDS scanEx1 *** CELL: stagesM:weakStage{sch} .SUBCKT weakStage ain[10] ain[11] ain[12] ain[13] ain[14] ain[1] ain[2] @@ -2145,8 +2138,8 @@ Xdata1in2@0 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] +out[31] out[32] out[33] out[34] out[35] out[36] out[37] out[3] out[4] out[5] +out[6] out[7] out[8] out[9] net@47 data1in20Bx37 XgaspWeak@0 net@59 sir[9] pred net@39 succ net@47 ain[TT] gaspWeak -XscanEx1v@0 net@39 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertA +XscanEx1@0 net@39 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx1 .ENDS weakStage *** CELL: orangeTSMC090nm:wire{sch} @@ -2763,9 +2756,9 @@ Xwire90@3 hcl[B] net@177 wire90-2550-layer_1-width_3 *** CELL: scanM:scanEx3{sch} .SUBCKT scanEx3 dIn[1] dIn[2] dIn[3] mc sir[1] sir[2] sir[3] sir[4] sir[5] +sir[6] sir[7] sir[8] sor[1] -XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanM__scanCellE -XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanM__scanCellE -XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sor[1] scanM__scanCellE +XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanCellE +XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanCellE +XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sor[1] scanCellE Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3 Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3 .ENDS scanEx3 @@ -2995,7 +2988,7 @@ Rres@3 net@8 net@11 8.603 Xwire@0 a b wire-C_0_011f-744_5-R_34_667m .ENDS wire90-744_5-layer_1-width_3 -*** CELL: gaspL:anAltStart{sch} +*** CELL: gaspM:anAltStart{sch} .SUBCKT anAltStart fire[A] fire[B] mc pred s[1] s[2] succA succB XctrAND4i@1 net@634 succA fire[B] net@912 fire[A] net@866 ctrAND4in30M XctrAND4i@3 net@634 succB net@909 fire[A] fire[B] net@885 ctrAND4in30M @@ -3083,7 +3076,7 @@ Xwire@0 a b wire-C_0_011f-1301_9-R_34_667m +outB[33] outB[34] outB[35] outB[36] outB[3] outB[4] outB[5] outB[6] outB[7] +outB[8] outB[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] +sir[9] sor[1] succA succB -XanAltSta@0 fire[A] fire[B] sir[9] pred net@48[1] net@48[0] succA succB +XanAltSta@1 fire[A] fire[B] sir[9] pred net@48[1] net@48[0] succA succB +anAltStart Xins1in20@0 net@23 in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] @@ -3169,14 +3162,14 @@ Xwire@0 a b wire-C_0_011f-291_8-R_34_667m .ENDS wire90-291_8-layer_1-width_3 *** CELL: gaspM:aStage{sch} -.SUBCKT gaspM__aStage fire mc pred s[1] succ +.SUBCKT aStage fire mc pred s[1] succ XctrAND2i@4 net@494 succ fire ctrAND2in30 Xinv@4 net@987 s[1] inv-X_10 Xinv@5 pred net@987 inv-X_5 XpredDri2@1 fire mc pred predDri20wMC XsucDri20@1 fire succ sucDri20 Xwire90@0 net@987 net@494 wire90-291_8-layer_1-width_3 -.ENDS gaspM__aStage +.ENDS aStage *** CELL: orangeTSMC090nm:wire{sch} .SUBCKT wire-C_0_011f-791_7-R_34_667m a b @@ -3204,7 +3197,7 @@ Xwire@0 a b wire-C_0_011f-791_7-R_34_667m +out[30] out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] +out[6] out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] +sir[7] sir[8] sir[9] sor[1] succ take[1] -XaStage@1 net@1 sir[9] pred net@41 succ gaspM__aStage +XaStage@1 net@1 sir[9] pred net@41 succ aStage Xins1in20@0 take[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +in[18] in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] +in[28] in[29] in[2] in[30] in[31] in[32] in[33] in[34] in[35] in[36] in[3] @@ -3214,8 +3207,8 @@ Xins1in20@0 take[1] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] +out[7] out[8] out[9] ins1in20Bx36 XlatchDri@0 fire[1] take[1] latchDriver60 -XscanEx1v@0 net@41 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertA +XscanEx1@0 net@41 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx1 Xwire90@1 net@1 fire[1] wire90-791_7-layer_1-width_3 .ENDS plainDockStage @@ -3244,7 +3237,7 @@ Xwire@0 a b wire-C_0_011f-414-R_34_667m +out[23] out[24] out[25] out[26] out[27] out[28] out[29] out[2] out[30] +out[31] out[32] out[33] out[34] out[35] out[36] out[3] out[4] out[5] out[6] +out[7] out[8] out[9] pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sir[9] sor[1] succ take[1] take[2] take[3] take[4] take[5] take[6] ++sir[8] sir[9] sor[1] succ take[4] XaltEndDo@0 net@16[26] net@16[25] net@16[24] net@16[23] net@16[22] net@16[21] +net@16[20] net@16[19] net@16[18] net@16[17] net@16[35] net@16[16] net@16[15] +net@16[14] net@16[13] net@16[12] net@16[11] net@16[10] net@16[9] net@16[8] @@ -3287,7 +3280,7 @@ XplainDoc@0 net@2[26] net@2[25] net@2[24] net@2[23] net@2[22] net@2[21] +net@3[13] net@3[12] net@3[11] net@3[10] net@3[9] net@3[8] net@3[7] net@3[34] +net@3[6] net@3[5] net@3[4] net@3[3] net@3[2] net@3[1] net@3[0] net@3[33] +net@3[32] net@3[31] net@3[30] net@3[29] net@3[28] net@3[27] net@107 -+net@131[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@130[8] ++net@136[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@130[8] +net@106 take[5] plainDockStage XplainDoc@1 net@20[26] net@20[25] net@20[24] net@20[23] net@20[22] net@20[21] +net@20[20] net@20[19] net@20[18] net@20[17] net@20[35] net@20[16] net@20[15] @@ -3300,7 +3293,7 @@ XplainDoc@1 net@20[26] net@20[25] net@20[24] net@20[23] net@20[22] net@20[21] +net@2[7] net@2[34] net@2[6] net@2[5] net@2[4] net@2[3] net@2[2] net@2[1] +net@2[0] net@2[33] net@2[32] net@2[31] net@2[30] net@2[29] net@2[28] +net@2[27] net@60 net@125[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] -+sir[9] net@131[8] net@108 take[4] plainDockStage ++sir[9] net@136[8] net@108 take[4] plainDockStage XplainDoc@2 net@3[26] net@3[25] net@3[24] net@3[23] net@3[22] net@3[21] +net@3[20] net@3[19] net@3[18] net@3[17] net@3[35] net@3[16] net@3[15] +net@3[14] net@3[13] net@3[12] net@3[11] net@3[10] net@3[9] net@3[8] net@3[7] @@ -3502,8 +3495,8 @@ Xins1in20@0 take[epi] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] +epi[31] epi[32] epi[33] epi[34] epi[35] epi[36] epi[3] epi[4] epi[5] epi[6] +epi[7] epi[8] epi[9] ins1in20Bx36 XlatchDri@0 net@0 take[epi] latchDriver60 -XscanEx1v@1 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertA +XscanEx1@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx1 Xwire90@0 net@0 net@5 wire90-372_8-layer_1-width_3 .ENDS epiDockStage @@ -3983,9 +3976,9 @@ Xwire90@0 circulate net@3 wire90-1041_2-layer_1-width_3 *** CELL: scanM:scanEx3plain{sch} .SUBCKT scanEx3plain dIn[1] dIn[2] dIn[3] sin sir[2] sir[3] sir[5] sout -XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sin net@26 scanM__scanCellE -XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanM__scanCellE -XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sout scanM__scanCellE +XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sin net@26 scanCellE +XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanCellE +XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sout scanCellE Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3 Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3 .ENDS scanEx3plain @@ -4021,8 +4014,8 @@ XlatchDri@0 net@3 take[E] latchDriver60 XlatchDri@1 net@7 take[P] latchDriver60 XreQueue@0 epi[OTHER] epi[TAIL] fire[E] fire[R] sir[9] od[ABORT] od[HEAD] +od[OTHER] ps[do] ps[skip] rq[succ] s[1] s[2] s[3] s[4] reQueue -XscanEx1v@0 s[1] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sin scanEx1vertA +XscanEx1@0 s[1] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sin scanEx1 XscanEx3p@1 s[2] s[3] s[4] sin sir[2] sir[3] sir[5] sor[1] scanEx3plain Xwire90@0 net@7 fire[R] wire90-1336_2-layer_1-width_3 Xwire90@1 net@3 fire[E] wire90-1307-layer_1-width_3 @@ -4109,11 +4102,11 @@ Xwire90@1 net@24 net@9 wire90-372_8-layer_1-width_3 .ENDS ctrAND2in30A *** CELL: gaspM:gaspLit{sch} -.SUBCKT gaspLit do[L] fire[L] mc ready s[1] +.SUBCKT gaspLit do[Lt] fire[L] mc ready s[1] XctrAND2i@0 net@189 ready fire[L] ctrAND2in30A -Xinv@1 do[L] net@190 inv-X_5 +Xinv@1 do[Lt] net@190 inv-X_5 XinvI@0 net@189 s[1] inv-X_10 -XpredDri2@1 fire[L] mc do[L] predDri20wMC +XpredDri2@1 fire[L] mc do[Lt] predDri20wMC Xwire90@1 net@190 net@189 wire90-414-layer_1-width_3 .ENDS gaspLit @@ -4147,51 +4140,6 @@ Xnand2@0 inA inB net@26 nand2-X_10 Xwire90@0 net@26 net@8 wire90-387_3-layer_1-width_3 .ENDS latchAndDriver30 -*** CELL: loopCountM:mux10/2{sch} -.SUBCKT mux10/2 in[1] out[1] sF sT -Xnms2b@0 out[1] sT in[1] nms2-X_10 -Xpms2@0 out[1] sF in[1] pms2-X_10 -.ENDS mux10/2 - -*** CELL: loopCountM:mux10/2x7{sch} -.SUBCKT mux10/2x7 in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2] -+out[3] out[4] out[5] out[6] out[7] sF sT -Xmux10/2@0 in[1] out[1] sF sT mux10/2 -Xmux10/2@1 in[2] out[2] sF sT mux10/2 -Xmux10/2@2 in[3] out[3] sF sT mux10/2 -Xmux10/2@3 in[4] out[4] sF sT mux10/2 -Xmux10/2@4 in[5] out[5] sF sT mux10/2 -Xmux10/2@5 in[6] out[6] sF sT mux10/2 -Xmux10/2@6 in[7] out[7] sF sT mux10/2 -.ENDS mux10/2x7 - -*** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-704_3-R_34_667m a b -Ccap@0 gnd net@14 2.582f -Ccap@1 gnd net@8 2.582f -Ccap@2 gnd net@11 2.582f -Rres@0 net@14 a 4.069 -Rres@1 net@11 net@14 8.139 -Rres@2 b net@8 4.069 -Rres@3 net@8 net@11 8.139 -.ENDS wire-C_0_011f-704_3-R_34_667m - -*** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-704_3-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-704_3-R_34_667m -.ENDS wire90-704_3-layer_1-width_3 - -*** CELL: loopCountM:muxForD{sch} -.SUBCKT muxForD in[1] in[2] in[3] in[4] in[5] in[6] out[1] out[2] out[3] -+out[4] out[5] out[6] out[7] sel -Xinv@0 sel net@0 inv-X_20 -Xinv@1 sF net@1 inv-X_20 -Xmux10/2x@0 in[1] in[2] in[3] in[4] in[5] in[6] gnd out[1] out[2] out[3] -+out[4] out[5] out[6] out[7] sF sT mux10/2x7 -Xwire90@0 net@0 sF wire90-704_3-layer_1-width_3 -Xwire90@1 net@1 sT wire90-704_3-layer_1-width_3 -.ENDS muxForD - *** CELL: registersM:data2in60Cx18{sch} .SUBCKT data2in60Cx18 dcl[A] dcl[B] inA[10] inA[11] inA[12] inA[13] inA[14] +inA[15] inA[16] inA[17] inA[18] inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] @@ -4708,51 +4656,49 @@ Xpms2_sy@0 out ina inb pms2_sy-X_10 Xnor2@0 ina inb out nor2_sy-X_10 .ENDS nor2n_sy-X_10 -*** CELL: stagesM:litDockStage{sch} -.SUBCKT litDockStage aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] -+aout[2] aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] -+do[L] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18] dp[19] -+dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28] dp[29] -+dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3] dp[4] -+dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] ds[10] ds[11] ds[12] ds[13] ds[14] ds[15] -+ds[16] ds[17] ds[18] ds[19] ds[1] ds[20] ds[21] ds[22] ds[23] ds[24] ds[25] -+ds[26] ds[27] ds[28] ds[29] ds[2] ds[30] ds[31] ds[32] ds[33] ds[34] ds[35] -+ds[36] ds[37] ds[3] ds[4] ds[5] ds[6] ds[7] ds[8] ds[9] fire[M] flag[C] -+outLO[1] outLO[2] outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[10] ps[11] -+ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] -+ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ready -+signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] -XgaspLit@0 do[L] net@10 sir[9] ready net@27 gaspLit +*** CELL: stagesM:litDandP{sch} +.SUBCKT litDandP do[Lt] dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] ++dp[17] dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] ++dp[27] dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] ++dp[37] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11] ++dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] dsA[4] dsA[5] dsA[6] dsA[7] ++dsA[8] dsA[9] dsA[TT] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16] ++dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] ++dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] ++dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] ++dsD[8] dsD[9] fire[M] flag[C] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ++ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ++ps[8] ps[9] signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] ++sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] +XgaspLit@0 do[Lt] net@10 sir[9] net@99 net@27 gaspLit Xinv@0 ps[17] net@77 inv-X_10 Xlatch2in@0 take[A] net@81 dp[B] signalBitFromInboundSwitchFabric flag[C] +latch2in60C XlatchAnd@1 ps[17] fire[M] take[A] latchAndDriver60 XlatchAnd@2 net@77 fire[M] net@81 latchAndDriver30 XlatchDri@0 net@13 take[B] latchDriver60 -XmuxForD@0 out[1] out[2] out[3] out[4] out[5] out[6] outLO[1] outLO[2] -+outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[20] muxForD XnewDregi@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18] +dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] dp[28] +dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] dp[3] -+dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] ds[10] ds[11] ds[12] ds[13] ds[14] ds[15] -+ds[16] ds[17] ds[18] ds[19] ds[1] ds[20] ds[21] ds[22] ds[23] ds[24] ds[25] -+ds[26] ds[27] ds[28] ds[29] ds[2] ds[30] ds[31] ds[32] ds[33] ds[34] ds[35] -+ds[36] ds[37] ds[3] ds[4] ds[5] ds[6] ds[7] ds[8] ds[9] ps[10] ps[11] ps[12] -+ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] -+ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] take[A] take[B] newDregister -XnewPathR@0 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] -+aout[3] aout[4] aout[5] aout[6] aout[7] aout[8] aout[9] aout[TT] dp[10] -+dp[11] dp[12] dp[1] dp[2] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] fire[M] -+ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] -+ps[7] ps[8] ps[9] newPathReg -Xnor2n_sy@0 succ[T] succ[D] ready nor2n_sy-X_10 -XscanEx1v@0 net@27 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertA ++dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] ++dsD[15] dsD[16] dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] ++dsD[23] dsD[24] dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] ++dsD[31] dsD[32] dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] ++dsD[6] dsD[7] dsD[8] dsD[9] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ++ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ++ps[9] take[A] take[B] newDregister +XnewPathR@0 dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] ++dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9] dsA[TT] dp[35] dp[36] dp[37] dp[26] ++dp[27] dp[28] dp[29] dp[30] dp[31] dp[32] dp[33] dp[34] fire[M] ps[10] ps[11] ++ps[12] ps[13] ps[14] ps[15] ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ++ps[9] newPathReg +Xnor2n_sy@0 succ[T] succ[D] net@99 nor2n_sy-X_10 +XscanEx1@0 net@27 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx1 XsucANDdr@0 ps[16] fire[M] succ[D] sucANDdri60 XsucANDdr@1 ps[15] fire[M] succ[T] sucANDdri60 Xwire90@0 net@10 net@13 wire90-4175_4-layer_1-width_3 -.ENDS litDockStage +.ENDS litDandP *** CELL: redFive:pms2{sch} .SUBCKT pms2-X_20 d g g2 @@ -4894,11 +4840,45 @@ XminusOne@0 ring[31] ring[32] ring[33] ring[34] ring[35] ring[36] net@11 +ring[30] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] +m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] +m1cate[6][T] sir[9] pred[R] net@47 succ[m1] minusOne -XscanEx1v@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] scanEx1vertA +XscanEx1@0 net@47 sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] ++sir[8] sor[1] scanEx1 Xwire90@1 net@11 fire[1] wire90-791_7-layer_1-width_3 .ENDS mOneDockStage +*** CELL: loopCountM:mux10/2{sch} +.SUBCKT mux10/2 in[1] out[1] sF sT +Xnms2b@0 out[1] sT in[1] nms2-X_10 +Xpms2@0 out[1] sF in[1] pms2-X_10 +.ENDS mux10/2 + +*** CELL: loopCountM:mux10/2x7{sch} +.SUBCKT mux10/2x7 in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2] ++out[3] out[4] out[5] out[6] out[7] sF sT +Xmux10/2@0 in[1] out[1] sF sT mux10/2 +Xmux10/2@1 in[2] out[2] sF sT mux10/2 +Xmux10/2@2 in[3] out[3] sF sT mux10/2 +Xmux10/2@3 in[4] out[4] sF sT mux10/2 +Xmux10/2@4 in[5] out[5] sF sT mux10/2 +Xmux10/2@5 in[6] out[6] sF sT mux10/2 +Xmux10/2@6 in[7] out[7] sF sT mux10/2 +.ENDS mux10/2x7 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-704_3-R_34_667m a b +Ccap@0 gnd net@14 2.582f +Ccap@1 gnd net@8 2.582f +Ccap@2 gnd net@11 2.582f +Rres@0 net@14 a 4.069 +Rres@1 net@11 net@14 8.139 +Rres@2 b net@8 4.069 +Rres@3 net@8 net@11 8.139 +.ENDS wire-C_0_011f-704_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-704_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-704_3-R_34_667m +.ENDS wire90-704_3-layer_1-width_3 + *** CELL: loopCountM:muxForPS{sch} .SUBCKT muxForPS in[1] in[2] in[3] in[4] in[5] in[6] in[7] out[1] out[2] +out[3] out[4] out[5] out[6] out[7] sel @@ -5900,6 +5880,43 @@ Xinv@0 pred net@145 inv-X_4 Xwire90@0 net@217 net@145 wire90-243_6-layer_1-width_3 .ENDS predORdri20wMC +*** CELL: redFive:nms2{sch} +.SUBCKT nms2-X_1_5 d g g2 +XNMOS@0 d g2 net@0 NMOSx-X_3 +XNMOS@1 net@0 g gnd NMOSx-X_3 +.ENDS nms2-X_1_5 + +*** CELL: redFive:pms2{sch} +.SUBCKT pms2-X_1_5 d g g2 +XPMOS@0 net@2 g vdd PMOSx-X_3 +XPMOS@1 d g2 net@2 PMOSx-X_3 +.ENDS pms2-X_1_5 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-154_5-R_34_667m a b +Ccap@0 gnd net@14 0.566f +Ccap@1 gnd net@8 0.566f +Ccap@2 gnd net@11 0.566f +Rres@0 net@14 a 0.893 +Rres@1 net@11 net@14 1.785 +Rres@2 b net@8 0.893 +Rres@3 net@8 net@11 1.785 +.ENDS wire-C_0_011f-154_5-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-154_5-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-154_5-R_34_667m +.ENDS wire90-154_5-layer_1-width_3 + +*** CELL: gates1inM:amp1.5{sch} +.SUBCKT amp1_5 in[1] out[1] +Xnms2a@0 net@16 in[1] in[1] nms2-X_1_5 +Xnms2a@1 out[1] net@17 net@17 nms2-X_1_5 +Xpms2a@0 net@16 in[1] in[1] pms2-X_1_5 +Xpms2a@1 out[1] net@17 net@17 pms2-X_1_5 +Xwire90@0 net@16 net@17 wire90-154_5-layer_1-width_3 +.ENDS amp1_5 + *** CELL: redFive:nand2n{sch} .SUBCKT nand2n-X_20 ina inb out Xnand2@0 ina inb out nand2-X_20 @@ -6116,14 +6133,14 @@ Xwire@0 a b wire-C_0_011f-590_5-R_34_667m *** CELL: moveM:races{sch} .SUBCKT races bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] in[D] in[T] succ torp -+winHI[M] winLO[M] ++winLO[M] +Xamp1_5@0 winLO[M] net@184 amp1_5 Xarbiter2@0 net@131 net@128 torp in[D] arbiter2 Xarbiter2@1 net@130 net@129 torp in[T] arbiter2 XinvI@0 net@150 fire[T] inv-X_20 Xnand2@0 bit[Di] do[Tp] net@35 nand2-X_10 Xnand2@1 bit[Ti] do[Tp] net@42 nand2-X_10 Xnand2@2 net@94 do[Mv] net@86 nand2-X_5 -Xnand2@3 winLO[M] winLO[M] winHI[M] nand2-X_5 Xnand2n@0 bit[Di] net@11 net@57 nand2n-X_20 Xnand2n@1 bit[Ti] net@53 net@60 nand2n-X_20 Xnand3in4@0 net@159 net@123 net@98 winLO[M] nand3in44s @@ -6131,7 +6148,6 @@ Xnor2_sy@0 net@48 net@45 net@151 nor2_sy-X_20 Xnor2n@0 net@39 net@12 net@44 nor2n-X_20 Xnor2n@1 net@36 net@32 net@43 nor2n-X_20 Xnor2n@2 succ net@153 net@152 nor2n-X_20 -Xnor2n@3 net@171 net@171 net@176 nor2n-X_5 Xwire90@0 net@131 net@12 wire90-321_9-layer_1-width_3 Xwire90@1 net@130 net@32 wire90-321_9-layer_1-width_3 Xwire90@2 net@129 net@53 wire90-294-layer_1-width_3 @@ -6143,10 +6159,9 @@ Xwire90@7 net@43 net@48 wire90-783-layer_1-width_3 Xwire90@8 net@60 net@123 wire90-1254_1-layer_1-width_3 Xwire90@9 net@57 net@159 wire90-1300_1-layer_1-width_3 Xwire90@11 net@86 net@153 wire90-392_9-layer_1-width_3 -Xwire90@12 net@94 net@176 wire90-174_7-layer_1-width_3 +Xwire90@12 net@94 net@184 wire90-174_7-layer_1-width_3 Xwire90@13 net@152 net@98 wire90-1154_9-layer_1-width_3 Xwire90@15 net@151 net@150 wire90-590_5-layer_1-width_3 -Xwire90@17 net@171 winHI[M] wire90-174_7-layer_1-width_3 .ENDS races *** CELL: orangeTSMC090nm:wire{sch} @@ -6214,9 +6229,9 @@ Xwire@0 a b wire-C_0_011f-709_6-R_34_667m .ENDS wire90-709_6-layer_1-width_3 *** CELL: moveM:moveOut{sch} -.SUBCKT moveOut bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] -+fire[M] flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4] -+s[5] succ[sf] winLO[M] +.SUBCKT moveOut bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M] ++flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4] s[5] ++succ[sf] winLO[M] Xinv@0 net@28 s[4] inv-X_10 Xinv@1 net@29 s[3] inv-X_10 Xinv@2 net@50 s[5] inv-X_10 @@ -6242,7 +6257,7 @@ XpredDri2@4 net@200 mc pred[T] predDri20wMC XpredORdr@0 fire[T] done[M] mc do[Tp] predORdri20wMC XpredORdr@1 fire[T] done[M] mc do[Mv] predORdri20wMC Xraces@0 bit[Di] bit[Ti] do[Mv] do[Tp] fire[T] pred[D] pred[T] succ[sf] -+epi[torp] races@0_winHI[M] winLO[M] races ++epi[torp] winLO[M] races XsucDri20@0 done[M] do[reD] sucDri20 Xwire90@9 net@206 net@208 wire90-362_9-layer_1-width_3 Xwire90@10 net@220 net@221 wire90-602_7-layer_1-width_3 @@ -6270,8 +6285,8 @@ Xwire@0 a b wire-C_0_011f-297_9-R_34_667m *** CELL: scanM:scanEx2h{sch} .SUBCKT scanEx2h dIn[1] dIn[2] mc p1p p2p rd sin sout -XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanM__scanCellE -XscanCell@11 dIn[2] p1p p2p rd net@31 sout scanM__scanCellE +XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanCellE +XscanCell@11 dIn[2] p1p p2p rd net@31 sout scanCellE Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3 .ENDS scanEx2h @@ -6293,19 +6308,19 @@ Xwire@0 a b wire-C_0_011f-218_6-R_34_667m *** CELL: scanM:scanEx3h{sch} .SUBCKT scanEx3h dIn[1] dIn[2] dIn[3] mc p1p p2p rd sin sout -XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanM__scanCellE -XscanCell@11 dIn[2] p1p p2p rd net@31 net@20 scanM__scanCellE -XscanCell@12 dIn[3] p1p p2p rd net@32 sout scanM__scanCellE +XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanCellE +XscanCell@11 dIn[2] p1p p2p rd net@31 net@20 scanCellE +XscanCell@12 dIn[3] p1p p2p rd net@32 sout scanCellE Xwire90@0 net@18 net@31 wire90-218_6-layer_1-width_3 Xwire90@1 net@20 net@32 wire90-218_6-layer_1-width_3 .ENDS scanEx3h *** CELL: scanM:scanEx4h{sch} .SUBCKT scanEx4h dIn[1] dIn[2] dIn[3] dIn[4] mc p1p p2p rd sin sout -XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanM__scanCellE -XscanCell@11 dIn[2] p1p p2p rd net@31 net@20 scanM__scanCellE -XscanCell@12 dIn[3] p1p p2p rd net@32 net@24 scanM__scanCellE -XscanCell@13 dIn[4] p1p p2p rd net@33 sout scanM__scanCellE +XscanCell@10 dIn[1] p1p p2p rd sin net@18 scanCellE +XscanCell@11 dIn[2] p1p p2p rd net@31 net@20 scanCellE +XscanCell@12 dIn[3] p1p p2p rd net@32 net@24 scanCellE +XscanCell@13 dIn[4] p1p p2p rd net@33 sout scanCellE Xwire90@0 net@18 net@31 wire90-297_9-layer_1-width_3 Xwire90@1 net@20 net@32 wire90-297_9-layer_1-width_3 Xwire90@2 net@24 net@33 wire90-297_9-layer_1-width_3 @@ -6488,13 +6503,13 @@ Xwire@0 a b wire-C_0_011f-1831_6-R_34_667m .ENDS wire90-1831_6-layer_1-width_3 *** CELL: moveM:ilcMoveOut{sch} -.SUBCKT ilcMoveOut bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] -+fire[M] flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] -+inLO[6] inLO[8] mc p1p p2p pred[D] pred[T] rd sin sout succ[sf] +.SUBCKT ilcMoveOut bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M] ++flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] ++inLO[8] mc p1p p2p pred[D] pred[T] rd sin sout succ[sf] Xilc@0 bitt[1] bitt[2] bitt[3] bitt[4] bitt[5] bitt[6] bitt[7] bitt[8] +ilc[decLO] ilc[do] ilc[load] ilc[mo] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] +inLO[6] inLO[8] ilc -XoutDockM@0 bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M] +XoutDockM@0 bit[Di] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M] +flag[D][set] ilc[do] ilc[mo] mc pred[D] pred[T] s[1] s[2] s[3] s[4] s[5] +succ[sf] net@72 moveOut XscanEx2h@0 s[1] s[5] mc p1p p2p rd net@51 net@58 scanEx2h @@ -6515,6 +6530,17 @@ Xwire90@9 wire90@9_a bitt[6] wire90-1486_5-layer_1-width_3 Xwire90@10 wire90@10_a bitt[7] wire90-1831_6-layer_1-width_3 .ENDS ilcMoveOut +*** CELL: loopCountM:muxForD{sch} +.SUBCKT muxForD in[1] in[2] in[3] in[4] in[5] in[6] outLO[1] outLO[2] ++outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] sel +Xinv@0 sel net@0 inv-X_20 +Xinv@1 sF net@1 inv-X_20 +Xmux10/2x@0 in[1] in[2] in[3] in[4] in[5] in[6] gnd outLO[1] outLO[2] ++outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] sF sT mux10/2x7 +Xwire90@0 net@0 sF wire90-704_3-layer_1-width_3 +Xwire90@1 net@1 sT wire90-704_3-layer_1-width_3 +.ENDS muxForD + *** CELL: wiresL:bitAssignments{sch} .SUBCKT bitAssignments .ENDS bitAssignments @@ -6586,12 +6612,6 @@ MPMOS4f@0 d g s b pch W='18*(1+ABP/sqrt(18*2))' L='2' +DELVTO='AVT0P/sqrt(18*2)' .ENDS PMOS4x-X_3 -*** CELL: redFive:pms2{sch} -.SUBCKT pms2-X_1_5 d g g2 -XPMOS@0 net@2 g vdd PMOSx-X_3 -XPMOS@1 d g2 net@2 PMOSx-X_3 -.ENDS pms2-X_1_5 - *** CELL: driversL:predCond20wMC{sch} .SUBCKT predCond20wMC cond in mc pred XNMOSx@1 pred mc gnd NMOSx-X_10 @@ -7738,29 +7758,33 @@ Xwire@0 a b wire-C_0_011f-867_8-R_34_667m .ENDS wire90-867_8-layer_1-width_3 *** CELL: stagesM:outDockCenter{sch} -.SUBCKT outDockCenter bit[Di] bit[Do] bit[Ti] do[Lt] epi[torp] fire[M] +.SUBCKT outDockCenter bit[18] bit[19] bit[20] do[Lt] epi[torp] fire[M] +fire[do] flag[A][clr] flag[A][set] flag[C][T] flag[D][clr] flag[D][set] -+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] m1[10] m1[11] m1[12] -+m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] -+m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] -+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p -+pred[D] pred[T] ps[do] ps[skip] rd sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] -+sel[Tp] sel[rD] sin sout succ[sf] ++inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[8] in[1] in[2] in[3] ++in[4] in[5] in[6] m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] ++m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] ++m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] ++m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[do] ps[skip] sel[Co] sel[Fl] ++sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] sir[1] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sir[9] sor[1] succ[sf] Xflags@0 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[C][T] -+m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] mc -+flags -XilcMoveO@0 bit[Di] bit[Do] bit[Ti] do[Mv] do[Tp] do[reD] epi[torp] fire[M] ++m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ++sir[9] flags +XilcMoveO@0 bit[18] bit[19] do[Mv] do[Tp] do[reD] epi[torp] fire[M] +flag[D][set] ilc[load] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] -+inLO[8] mc p1p p2p pred[D] pred[T] rd net@249 sout succ[sf] ilcMoveOut ++inLO[8] sir[9] sir[3] sir[2] pred[D] pred[T] sir[5] net@249 sor[1] succ[sf] ++ilcMoveOut +XmuxForD@0 in[1] in[2] in[3] in[4] in[5] in[6] inLO[1] inLO[2] inLO[3] ++inLO[4] inLO[5] inLO[6] inLO[8] bit[20] muxForD XohPredAl@0 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] flag[A][clr] +flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] m1cate[1][F] +m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] -+m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] mc p1p p2p -+ps[do] ps[skip] rd sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] -+net@244 net@249 ohPredAll ++m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9] ++sir[3] sir[2] ps[do] ps[skip] sir[5] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] ++sel[Tp] sel[rD] net@244 net@249 ohPredAll XolcWcont@0 sel[rD] do[Co] do[Ld] do[reD] flag[D][clr] flag[D][set] net@165 -+inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] mc p1p p2p rd sin net@244 -+olcWcont ++inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] sir[9] sir[3] sir[2] sir[5] ++sir[1] net@244 olcWcont Xwire90@5 wire90@5_a flag[A][set] wire90-3750-layer_1-width_3 Xwire90@6 wire90@6_a flag[A][clr] wire90-3560-layer_1-width_3 Xwire90@7 wire90@7_a flag[B][set] wire90-3750-layer_1-width_3 @@ -7772,18 +7796,18 @@ Xwire90@24 net@165 ilc[load] wire90-867_8-layer_1-width_3 *** CELL: stagesM:outDockPredStage{sch} .SUBCKT outDockPredStage do[Lt] epi[torp] fire[M] flag[A][clr] flag[A][set] -+flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] -+inLO[6] inLO[8] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] -+m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] -+m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] -+m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] -+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] -+m1cate[5][T] m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] -+ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] -+ps[23] ps[24] ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] -+ps[33] ps[34] ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] -+ps[skip] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] -+sor[1] succ[sf] take[ps] ++flag[C][T] flag[D][clr] flag[D][set] in[1] in[2] in[3] in[4] in[5] in[6] ++m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] ++m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] ++m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] ++m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] ++m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] ++m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] ++ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ++ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ++ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] ++sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] ++succ[sf] take[ps] XdockPSre@0 net@39 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] +m1[18] m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] +m1[28] m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] @@ -7792,14 +7816,15 @@ XdockPSre@0 net@39 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] +ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ps[27] +ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ps[3] +ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] take[ps] dockPSreg -XoutDockC@0 ps[18] ps[16] ps[19] do[Lt] epi[torp] fire[M] net@6 flag[A][clr] +XoutDockC@0 ps[18] ps[19] ps[20] do[Lt] epi[torp] fire[M] net@6 flag[A][clr] +flag[A][set] flag[C][T] flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] -+inLO[4] inLO[5] inLO[6] inLO[8] m1[10] m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] -+m1[5] m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] -+m1cate[2][T] m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] -+m1cate[5][T] m1cate[6][F] m1cate[6][T] sir[9] sir[3] sir[2] pred[D] pred[T] -+ps[do] ps[skip] sir[5] m1[24] m1[22] m1[23] m1[27] m1[25] m1[26] m1[21] -+sir[1] sor[1] succ[sf] outDockCenter ++inLO[4] inLO[5] inLO[6] inLO[8] in[1] in[2] in[3] in[4] in[5] in[6] m1[10] ++m1[11] m1[12] m1[1] m1[2] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] m1[9] ++m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] m1cate[3][T] ++m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] m1cate[6][T] ++pred[D] pred[T] ps[do] ps[skip] m1[24] m1[22] m1[23] m1[27] m1[25] m1[26] ++m1[21] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] ++succ[sf] outDockCenter Xwire90@0 net@6 net@39 wire90-791_7-layer_1-width_3 .ENDS outDockPredStage @@ -7813,31 +7838,30 @@ Xwire90@0 net@6 net@39 wire90-791_7-layer_1-width_3 +dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] +dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] +dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] -+dsD[8] dsD[9] epi[torp] flag[A][clr] flag[A][set] flag[C][T] flag[D][clr] -+flag[D][set] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] -+m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] -+m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] -+m1[5] m1[6] m1[7] m1[8] m1[9] pred[D] pred[R] pred[T] ps[do] ps[skip] -+ring[10] ring[11] ring[12] ring[13] ring[14] ring[15] ring[16] ring[17] -+ring[18] ring[19] ring[1] ring[20] ring[21] ring[22] ring[23] ring[24] -+ring[25] ring[26] ring[27] ring[28] ring[29] ring[2] ring[30] ring[31] -+ring[32] ring[33] ring[34] ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] -+ring[7] ring[8] ring[9] signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] -+sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] succ[m1] -XlitDockS@0 dsA[10] dsA[11] dsA[12] dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] -+dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] dsA[9] dsA[TT] net@45 dp[10] dp[11] dp[12] -+dp[13] dp[14] dp[15] dp[16] dp[17] dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] -+dp[23] dp[24] dp[25] dp[26] dp[27] dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] -+dp[33] dp[34] dp[35] dp[36] dp[37] dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] -+dp[B] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16] dsD[17] dsD[18] -+dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] dsD[25] dsD[26] -+dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] dsD[33] dsD[34] -+dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] dsD[8] dsD[9] -+net@44 sourceOfFlagC inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] inLO[7] -+ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] -+ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ready -+signalBitFromInboundSwitchFabric net@48[8] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] litDockStage ++dsD[8] dsD[9] epi[torp] flag[A][clr] flag[A][set] flag[D][clr] flag[D][set] ++m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] ++m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] ++m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] ++m1[7] m1[8] m1[9] pred[D] pred[R] pred[T] ps[do] ps[skip] ring[10] ring[11] ++ring[12] ring[13] ring[14] ring[15] ring[16] ring[17] ring[18] ring[19] ++ring[1] ring[20] ring[21] ring[22] ring[23] ring[24] ring[25] ring[26] ++ring[27] ring[28] ring[29] ring[2] ring[30] ring[31] ring[32] ring[33] ++ring[34] ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ++ring[9] signalBitFromInboundSwitchFabric sir[1] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] succ[m1] +XlitDandP@0 net@89 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] ++dp[18] dp[19] dp[1] dp[20] dp[21] dp[22] dp[23] dp[24] dp[25] dp[26] dp[27] ++dp[28] dp[29] dp[2] dp[30] dp[31] dp[32] dp[33] dp[34] dp[35] dp[36] dp[37] ++dp[3] dp[4] dp[5] dp[6] dp[7] dp[8] dp[9] dp[B] dsA[10] dsA[11] dsA[12] ++dsA[13] dsA[14] dsA[1] dsA[2] dsA[3] dsA[4] dsA[5] dsA[6] dsA[7] dsA[8] ++dsA[9] dsA[TT] dsD[10] dsD[11] dsD[12] dsD[13] dsD[14] dsD[15] dsD[16] ++dsD[17] dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] ++dsD[25] dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] ++dsD[33] dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] ++dsD[8] dsD[9] net@90 net@79 ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ++ps[17] ps[18] ps[19] ps[1] ps[20] ps[2] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ++ps[9] signalBitFromInboundSwitchFabric net@48[8] sir[2] sir[3] sir[4] sir[5] ++sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] litDandP XmOneDock@0 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] +m1[19] m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] +m1[29] m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] @@ -7850,19 +7874,22 @@ XmOneDock@0 m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] +ring[35] ring[36] ring[3] ring[4] ring[5] ring[6] ring[7] ring[8] ring[9] +sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@47[8] +succ[m1] take[m1] mOneDockStage -XoutDockP@0 net@45 epi[torp] net@44 flag[A][clr] flag[A][set] flag[C][T] -+flag[D][clr] flag[D][set] inLO[1] inLO[2] inLO[3] inLO[4] inLO[5] inLO[6] -+inLO[7] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] -+m1[1] m1[20] m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] -+m1[2] m1[30] m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] -+m1[6] m1[7] m1[8] m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] -+m1cate[3][F] m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] -+m1cate[6][F] m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] -+ps[15] ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] -+ps[25] ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] -+ps[35] ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] -+net@47[8] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@48[8] -+succ[D] take[ps] outDockPredStage +XoutDockP@0 net@91 epi[torp] fire[M] flag[A][clr] flag[A][set] net@82 ++flag[D][clr] flag[D][set] dsD[1] dsD[2] dsD[3] dsD[4] dsD[5] dsD[6] m1[10] ++m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] m1[18] m1[19] m1[1] m1[20] ++m1[21] m1[22] m1[23] m1[24] m1[25] m1[26] m1[27] m1[28] m1[29] m1[2] m1[30] ++m1[31] m1[32] m1[33] m1[34] m1[35] m1[36] m1[3] m1[4] m1[5] m1[6] m1[7] m1[8] ++m1[9] m1cate[1][F] m1cate[1][T] m1cate[2][F] m1cate[2][T] m1cate[3][F] ++m1cate[3][T] m1cate[4][F] m1cate[4][T] m1cate[5][F] m1cate[5][T] m1cate[6][F] ++m1cate[6][T] pred[D] pred[T] ps[10] ps[11] ps[12] ps[13] ps[14] ps[15] ps[16] ++ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] ps[26] ++ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] ps[36] ++ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ps[do] ps[skip] net@47[8] sir[2] ++sir[3] sir[4] sir[5] sir[6] sir[7] sir[8] sir[9] net@48[8] succ[D] take[ps] ++outDockPredStage +Xwire90@0 net@79 net@82 wire90-4175_4-layer_1-width_3 +Xwire90@1 net@90 fire[M] wire90-4175_4-layer_1-width_3 +Xwire90@2 net@89 net@91 wire90-4175_4-layer_1-width_3 .ENDS outM1PredLit *** CELL: orangeTSMC090nm:wire{sch} @@ -7908,8 +7935,7 @@ XdockWagN@0 net@26[26] net@26[25] net@26[24] net@26[23] net@26[22] net@26[21] +net@57[8] net@57[7] net@57[34] net@57[6] net@57[5] net@57[4] net@57[3] +net@57[2] net@57[1] net@57[0] net@57[33] net@57[32] net@57[31] net@57[30] +net@57[29] net@57[28] net@57[27] net@15 net@75[8] sir[2] sir[3] sir[4] sir[5] -+sir[6] sir[7] sir[8] sir[9] net@76[8] net@85 take[1] take[2] take[3] fout -+take[5] take[6] dockWagNine ++sir[6] sir[7] sir[8] sir[9] net@76[8] net@85 fout dockWagNine XepiRQod@1 do[epi] net@89 net@82 flag[A][clr] flag[A][set] flag[D][clr] +flag[D][set] in[10] in[11] in[12] in[13] in[14] in[15] in[16] in[17] in[18] +in[19] in[1] in[20] in[21] in[22] in[23] in[24] in[25] in[26] in[27] in[28] @@ -7936,20 +7962,20 @@ XoutM1Pre@0 dp[10] dp[11] dp[12] dp[13] dp[14] dp[15] dp[16] dp[17] dp[18] +dsD[18] dsD[19] dsD[1] dsD[20] dsD[21] dsD[22] dsD[23] dsD[24] dsD[25] +dsD[26] dsD[27] dsD[28] dsD[29] dsD[2] dsD[30] dsD[31] dsD[32] dsD[33] +dsD[34] dsD[35] dsD[36] dsD[37] dsD[3] dsD[4] dsD[5] dsD[6] dsD[7] dsD[8] -+dsD[9] torp flag[A][clr] flag[A][set] outM1Pre@0_flag[C][T] flag[D][clr] -+flag[D][set] net@68[26] net@68[25] net@68[24] net@68[23] net@68[22] -+net@68[21] net@68[20] net@68[19] net@68[18] net@68[17] net@68[35] net@68[16] -+net@68[15] net@68[14] net@68[13] net@68[12] net@68[11] net@68[10] net@68[9] -+net@68[8] net@68[7] net@68[34] net@68[6] net@68[5] net@68[4] net@68[3] -+net@68[2] net@68[1] net@68[0] net@68[33] net@68[32] net@68[31] net@68[30] -+net@68[29] net@68[28] net@68[27] pred[D] net@84 pred[T] ps[do] ps[skip] -+net@57[26] net@57[25] net@57[24] net@57[23] net@57[22] net@57[21] net@57[20] -+net@57[19] net@57[18] net@57[17] net@57[35] net@57[16] net@57[15] net@57[14] -+net@57[13] net@57[12] net@57[11] net@57[10] net@57[9] net@57[8] net@57[7] -+net@57[34] net@57[6] net@57[5] net@57[4] net@57[3] net@57[2] net@57[1] -+net@57[0] net@57[33] net@57[32] net@57[31] net@57[30] net@57[29] net@57[28] -+net@57[27] signalBitFromInboundSwitchFabric net@76[8] sir[2] sir[3] sir[4] -+sir[5] sir[6] sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] net@88 outM1PredLit ++dsD[9] torp flag[A][clr] flag[A][set] flag[D][clr] flag[D][set] net@68[26] ++net@68[25] net@68[24] net@68[23] net@68[22] net@68[21] net@68[20] net@68[19] ++net@68[18] net@68[17] net@68[35] net@68[16] net@68[15] net@68[14] net@68[13] ++net@68[12] net@68[11] net@68[10] net@68[9] net@68[8] net@68[7] net@68[34] ++net@68[6] net@68[5] net@68[4] net@68[3] net@68[2] net@68[1] net@68[0] ++net@68[33] net@68[32] net@68[31] net@68[30] net@68[29] net@68[28] net@68[27] ++pred[D] net@84 pred[T] ps[do] ps[skip] net@57[26] net@57[25] net@57[24] ++net@57[23] net@57[22] net@57[21] net@57[20] net@57[19] net@57[18] net@57[17] ++net@57[35] net@57[16] net@57[15] net@57[14] net@57[13] net@57[12] net@57[11] ++net@57[10] net@57[9] net@57[8] net@57[7] net@57[34] net@57[6] net@57[5] ++net@57[4] net@57[3] net@57[2] net@57[1] net@57[0] net@57[33] net@57[32] ++net@57[31] net@57[30] net@57[29] net@57[28] net@57[27] ++signalBitFromInboundSwitchFabric net@76[8] sir[2] sir[3] sir[4] sir[5] sir[6] ++sir[7] sir[8] sir[9] sor[1] succ[D] succ[T] net@88 outM1PredLit Xwire90@1 net@84 net@85 wire90-10-layer_1-width_3 Xwire90@2 torp net@82 wire90-10-layer_1-width_3 Xwire90@3 net@89 net@88 wire90-10-layer_1-width_3 @@ -8011,12 +8037,6 @@ XsucANDdr@3 to[B] fire succ[B] sucANDdri60 Xwire90@0 net@240 net@163 wire90-602_3-layer_1-width_3 .ENDS gaspTap -*** CELL: scanM:scanEx1{sch} -.SUBCKT scanEx1 dIn[1] mc sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] -+sir[8] sor[1] -XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] sor[1] scanM__scanCellE -.ENDS scanEx1 - *** CELL: scanM:scanFx2{sch} .SUBCKT scanFx2 dout[1] dout[2] sic[1] sic[2] sic[3] sic[4] sic[5] sic[6] +sic[7] sic[8] sic[9] soc[1] @@ -8177,34 +8197,13 @@ XupDown8w@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] +sir[8] sir[9] net@64[8] net@58 net@61 upDown8weak .ENDS southFifo -*** CELL: gaspL:aStage{sch} -.SUBCKT gaspL__aStage fire mc pred s[1] succ -XctrAND2i@4 net@494 succ fire ctrAND2in30 -Xinv@4 net@987 s[1] inv-X_10 -Xinv@5 pred net@987 inv-X_5 -XpredDri2@1 fire mc pred predDri20wMC -XsucDri20@1 fire succ sucDri20 -Xwire90@0 net@987 net@494 wire90-291_8-layer_1-width_3 -.ENDS gaspL__aStage - -*** CELL: scanJ:scanEx3hor{sch} -.SUBCKT scanEx3hor dIn[1] dIn[2] dIn[3] mc sir[1] sir[2] sir[3] sir[4] sir[5] -+sir[6] sir[7] sir[8] sor[1] -XscanCell@1 dIn[1] sir[3] sir[2] sir[5] sir[1] net@26 scanJ__scanCellE -XscanCell@2 dIn[2] sir[3] sir[2] sir[5] net@27 net@48 scanJ__scanCellE -XscanCell@3 dIn[3] sir[3] sir[2] sir[5] net@45 sor[1] scanJ__scanCellE -Xwire90@0 net@26 net@27 wire90-297_6-layer_1-width_3 -Xwire90@1 net@48 net@45 wire90-297_6-layer_1-width_3 -.ENDS scanEx3hor - -*** CELL: fifoL:tokenFIFO{sch} +*** CELL: stageGroupsM:tokenFIFO{sch} .SUBCKT tokenFIFO pred sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] sir[7] +sir[8] sir[9] sor[1] succ -XaStage@0 aStage@0_fire sir[9] pred s[1] net@0 gaspL__aStage -XaStage@1 aStage@1_fire sir[9] net@1 s[2] net@2 gaspL__aStage -XaStage@2 aStage@2_fire sir[9] net@3 s[3] succ gaspL__aStage -XscanEx3h@0 s[1] s[2] s[3] sir[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[6] -+sir[7] sir[8] sor[1] scanEx3hor +XaStage@3 aStage@3_fire sir[9] pred s[1] net@0 aStage +XaStage@4 aStage@4_fire sir[9] net@1 s[2] net@2 aStage +XaStage@5 aStage@5_fire sir[9] net@3 s[3] succ aStage +XscanEx3h@1 s[1] s[2] s[3] sir[9] sir[3] sir[2] sir[5] sir[1] sor[1] scanEx3h Xwire90@0 net@0 net@1 wire90-291_8-layer_1-width_3 Xwire90@1 net@2 net@3 wire90-291_8-layer_1-width_3 .ENDS tokenFIFO @@ -8253,6 +8252,6 @@ XsouthFif@1 aout[10] aout[11] aout[12] aout[13] aout[14] aout[1] aout[2] +sid[7] sid[8] sid[9] sir[1] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] sir[8] +sir[9] net@116[8] net@117[8] net@117[7] net@117[6] net@117[5] net@117[4] +net@119[8] net@14 southFifo -XtokenFIF@0 ddo[T] net@120[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] +XtokenFIF@1 ddo[T] net@120[8] sir[2] sir[3] sir[4] sir[5] sir[3] sir[2] +sir[8] sir[9] net@109[8] doo[T] tokenFIFO .END diff --git a/testCode/marina.xml b/testCode/marina.xml index 1bba14e..66ce601 100644 --- a/testCode/marina.xml +++ b/testCode/marina.xml @@ -11,58 +11,58 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -96,58 +96,58 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -181,21 +181,21 @@ '> - - - - - - - + + + + + + + + - - + + @@ -203,16 +203,16 @@ - - - - - - + + + + + + - + @@ -237,18 +237,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -297,9 +297,6 @@ &stageGroupsM_dockWagNine_sir_1_; &stageGroupsM_outM1PredLit_sir_1_; '> - &scanJ_scanEx3hor_sir_1_; -'> @@ -308,7 +305,7 @@ &gaspM_fillScanControl_si_1_; '> + '> &scanM_scanEx3h_sin; @@ -353,14 +350,6 @@ &latchGroupsK_latchWscM2_sin; &latchGroupsK_latchWscM2_sin; '> - -'> - - - -'> '> @@ -440,7 +429,7 @@ &stagesM_mOneDockStage_sir_1_; &stagesM_outDockPredStage_sir_1_; - &stagesM_litDockStage_sir_1_; + &stagesM_litDandP_sir_1_; '> &stagesM_fillStage_sic_1_; @@ -475,6 +464,9 @@ &stageGroupsM_properStopper_sir_1_; &stagesM_tapStage_sir_1_; '> + &scanM_scanEx3h_sin; +'> &stagesM_weakStage_sir_1_; &stagesM_weakStage_sir_1_; @@ -498,7 +490,7 @@ &scanM_scanEx2_sir_1_; '> &scanJ_scanEx1vertA_sir_1_; + &scanM_scanEx1_sir_1_; '> &scanM_scanFx3_sic_1_; @@ -515,28 +507,28 @@ &scanM_scanEx2_sir_1_; '> - &scanJ_scanEx1vertA_sir_1_; + &scanM_scanEx1_sir_1_; '> &scanJ_scanEx1vertA_sir_1_; + &scanM_scanEx1_sir_1_; '> &scanM_scanEx2_sir_1_; '> - &loopCountM_olcWcont_sin; &predicateM_ohPredAll_sin; &moveM_ilcMoveOut_sin; '> &stagesM_outDockCenter_sin; + &stagesM_outDockCenter_sir_1_; '> &scanJ_scanEx1vertA_sir_1_; + &scanM_scanEx1_sir_1_; '> &scanJ_scanEx1vertA_sir_1_; + &scanM_scanEx1_sir_1_; &scanM_scanEx3plain_sin; '> &scanM_scanEx1_sir_1_; '> &scanJ_scanEx1vertA_sir_1_; + &scanM_scanEx1_sir_1_; '> ]> @@ -560,7 +552,7 @@ &stageGroupsM_southFifo_sir_1_; &dockM_outputDock_sir_1_; - &fifoL_tokenFIFO_sir_1_; + &stageGroupsM_tokenFIFO_sir_1_; &stageGroupsM_northFifo_sir_1_;