From: Adam Megacz Date: Tue, 28 Apr 2009 17:47:04 +0000 (+0000) Subject: update marina.{spi,v} X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=f2d844fdf8214d0d8e498aade28123d0806da201;p=fleet.git update marina.{spi,v} --- diff --git a/testCode/marina.spi b/testCode/marina.spi index bafbfb7..38ce8ee 100644 --- a/testCode/marina.spi +++ b/testCode/marina.spi @@ -1,7 +1,7 @@ *** SPICE deck for cell marinaOut{sch} from library aMarinaM *** Created on Mon Nov 17, 2008 08:47:24 *** Last revised on Mon Mar 30, 2009 06:59:15 -*** Written on Thu Apr 23, 2009 09:45:00 by Electric VLSI Design System, +*** Written on Tue Apr 28, 2009 10:46:28 by Electric VLSI Design System, *version 8.08k *** Layout tech: cmos90, foundry TSMC *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF @@ -5037,12 +5037,13 @@ Xins1in20@0 take[1] m1[10] m1[11] m1[12] m1[13] m1[14] m1[15] m1[16] m1[17] +ps[16] ps[17] ps[18] ps[19] ps[1] ps[20] ps[21] ps[22] ps[23] ps[24] ps[25] +ps[26] ps[27] ps[28] ps[29] ps[2] ps[30] ps[31] ps[32] ps[33] ps[34] ps[35] +ps[36] ps[3] ps[4] ps[5] ps[6] ps[7] ps[8] ps[9] ins1in20Bx36 +XlatchDri@0 fire[1] net@0 latchDriver60 XmuxForOD@0 ps[1] ps[2] ps[3] ps[4] ps[5] ps[6] ps[8] outLO[1] outLO[2] +outLO[3] outLO[4] outLO[5] outLO[6] outLO[7] ps[20] muxForPS Xtc[1] tranCap Xtc[2] tranCap Xtc[3] tranCap -Xwire90@0 fire[1] take[1] wire90-544_2-layer_1-width_3 +Xwire90@0 net@0 take[1] wire90-544_2-layer_1-width_3 .ENDS dockPSreg *** CELL: redFive:nand2n{sch} @@ -6859,12 +6860,14 @@ XpredCond@1 sel[rD] fire[do] mc flag[D][set] predCond20wMS +flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] flag[D][clr] flag[D][set] +mc ps[do] ps[skip] sel[Co] sel[Fl] sel[Ld] sel[Lt] sel[Mv] sel[Tp] sel[rD] XbitAssig@0 bitAssignments -XohPredDo@3 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] fire[do] sel[Co] sel[Ld] -+sel[Lt] sel[Mv] sel[Tp] predSucDri -XpredFlag@1 fire[do] flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] +Xinv@1 fire[do] net@125 inv-X_20 +Xinv@2 net@125 net@57 inv-X_20 +XohPredDo@3 do[Co] do[Ld] do[Lt] do[Mv] do[Tp] net@57 sel[Co] sel[Ld] sel[Lt] ++sel[Mv] sel[Tp] predSucDri +XpredFlag@1 net@57 flag[A][clr] flag[A][set] flag[B][clr] flag[B][set] +flag[D][clr] flag[D][set] mc sel[Fl] sel[rD] predFlagDri XsucDri20@0 net@55 ps[skip] sucDri20 -XsucDri20@1 fire[do] ps[do] sucDri20 +XsucDri20@1 net@57 ps[do] sucDri20 Xwire90@2 fire[skip] net@55 wire90-309-layer_1-width_3 .ENDS ohPredDo diff --git a/testCode/marina.v b/testCode/marina.v index a59f578..47a3385 100644 --- a/testCode/marina.v +++ b/testCode/marina.v @@ -1,7 +1,7 @@ /* Verilog for cell 'marinaOut{sch}' from library 'aMarinaM' */ /* Created on Mon Nov 17, 2008 08:47:24 */ /* Last revised on Mon Mar 30, 2009 06:59:15 */ -/* Written on Thu Apr 23, 2009 09:44:56 by Electric VLSI Design System, version 8.08k */ +/* Written on Tue Apr 28, 2009 10:01:36 by Electric VLSI Design System, version 8.08k */ module orangeTSMC090nm__wire(a); input a; @@ -4074,22 +4074,24 @@ module loopCountM__muxForPS(in, sel, out); orangeTSMC090nm__wire90 wire90_1(.a(sF)); endmodule /* loopCountM__muxForPS */ -module registersM__dockPSreg(fire, m1, outLO, ps); +module registersM__dockPSreg(fire, m1, outLO, ps, take); input [1:1] fire; input [1:36] m1; output [1:7] outLO; output [1:36] ps; + output [1:1] take; supply1 vdd; supply0 gnd; - registersM__ins1in20Bx36 ins1in20_0(.hcl(fire[1:1]), .in(m1[1:36]), + registersM__ins1in20Bx36 ins1in20_0(.hcl(take[1:1]), .in(m1[1:36]), .out(ps[1:36])); + driversJ__latchDriver60 latchDri_0(.in(fire[1]), .out(take[1])); loopCountM__muxForPS muxForOD_0(.in({ps[1], ps[2], ps[3], ps[4], ps[5], ps[6], ps[8]}), .sel(ps[20]), .out(outLO[1:7])); wiresL__tranCap tc_1_(); wiresL__tranCap tc_2_(); wiresL__tranCap tc_3_(); - orangeTSMC090nm__wire90 wire90_0(.a(fire[1])); + orangeTSMC090nm__wire90 wire90_0(.a(take[1])); endmodule /* registersM__dockPSreg */ module redFive__xor2(ina, inaB, inb, inbB, out); @@ -5168,18 +5170,26 @@ module predicateM__ohPredDo(fire_do_, fire_skip_, flag_A__clr_, flag_A__set_, supply1 vdd; supply0 gnd; + wire net_125, net_57; + wiresL__bitAssignments bitAssig_0(); - predicateM__predSucDri ohPredDo_3(.fire_do_(fire_do_), .sel_Co_(sel_Co_), + /* begin Verilog_template for redFive:inv{sch}*/ + not (strong0, strong1) #(100) inv_1 (net_125, fire_do_); + // end Verilog_template + /* begin Verilog_template for redFive:inv{sch}*/ + not (strong0, strong1) #(100) inv_2 (net_57, net_125); + // end Verilog_template + predicateM__predSucDri ohPredDo_3(.fire_do_(net_57), .sel_Co_(sel_Co_), .sel_Ld_(sel_Ld_), .sel_Lt_(sel_Lt_), .sel_Mv_(sel_Mv_), .sel_Tp_(sel_Tp_), .do_Co_(do_Co_), .do_Ld_(do_Ld_), .do_Lt_(do_Lt_), .do_Mv_(do_Mv_), .do_Tp_(do_Tp_)); - predicateM__predFlagDri predFlag_1(.fire_do_(fire_do_), + predicateM__predFlagDri predFlag_1(.fire_do_(net_57), .flag_A__clr_(flag_A__clr_), .flag_A__set_(flag_A__set_), .flag_B__clr_(flag_B__clr_), .flag_B__set_(flag_B__set_), .flag_D__clr_(flag_D__clr_), .flag_D__set_(flag_D__set_), .mc(mc), .sel_Fl_(sel_Fl_), .sel_rD_(sel_rD_)); driversL__sucDri20 sucDri20_0(.in(fire_skip_), .succ(ps_skip_)); - driversL__sucDri20 sucDri20_1(.in(fire_do_), .succ(ps_do_)); + driversL__sucDri20 sucDri20_1(.in(net_57), .succ(ps_do_)); orangeTSMC090nm__wire90 wire90_2(.a(fire_skip_)); endmodule /* predicateM__ohPredDo */ @@ -5662,6 +5672,9 @@ module driversL__sucDri20or(inA, inB, succ); supply0 gnd; wire net_94; + /* user-specified Verilog declarations */ + wor succ; + /* begin Verilog_template for redFive:inv{sch}*/ not (strong0, strong1) #(100) inv_1 (net_94, succ); // end Verilog_template @@ -6025,6 +6038,7 @@ module stagesM__outDockPredStage(epi_torp_, flag_C__T_, in, m1, m1cate_1__F_, supply1 vdd; supply0 gnd; wire net_6; + wire [1:1] dockPSre_0_take; wire \inLO[1] ; wire \inLO[2] ; wire \inLO[3] ; @@ -6040,7 +6054,7 @@ module stagesM__outDockPredStage(epi_torp_, flag_C__T_, in, m1, m1cate_1__F_, ps[9], ps[10], ps[11], ps[12], ps[13], ps[14], ps[15], ps[16], ps[17], ps[18], ps[19], ps[20], ps_1[21], ps_1[22], ps_1[23], ps_1[24], ps_1[25], ps_1[26], ps_1[27], ps_1[28], ps_1[29], ps_1[30], ps_1[31], ps_1[32], - ps_1[33], ps_1[34], ps_1[35], ps_1[36]})); + ps_1[33], ps_1[34], ps_1[35], ps_1[36]}), .take(dockPSre_0_take[1:1])); stagesM__outDockCenter outDockC_0(.bit(ps[18:20]), .epi_torp_(epi_torp_), .flag_C__T_(flag_C__T_), .in(in[1:6]), .\inLO[1] ( \inLO[1] ), .\inLO[2] ( \inLO[2] ), .\inLO[3] ( \inLO[3] ), .\inLO[4] ( \inLO[4] ), .\inLO[5] (