From: adam Date: Sun, 7 Sep 2008 03:11:46 +0000 (+0100) Subject: reduce use of verilog macro expansion in FpgaDock X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=f7736c488e578e71d63ad60ca086143097cd7019;p=fleet.git reduce use of verilog macro expansion in FpgaDock --- diff --git a/src/edu/berkeley/fleet/fpga/FpgaDock.java b/src/edu/berkeley/fleet/fpga/FpgaDock.java index 5315f78..5fa79c2 100644 --- a/src/edu/berkeley/fleet/fpga/FpgaDock.java +++ b/src/edu/berkeley/fleet/fpga/FpgaDock.java @@ -67,21 +67,21 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { super(inbox ? "inbox" : "outbox"); /* - Module horn = new HornModule(); - Module funnel = new FunnelModule(); - Module.SourcePort instruction = createInputPort("instruction", WIDTH_PACKET); - Module.SourcePort fabric_in = createInputPort("fabric_in", WIDTH_PACKET); - Module.SinkPort fabric_out = createOutputPort("fabric_out", WIDTH_PACKET, ""); - if (!inbox) { - FunnelModule.FunnelInstance f0 = new FunnelModule.FunnelInstance(this, instruction, fabric_in); - Module.SourcePort ship_out = createInputPort("ship", WIDTH_WORD); - FunnelModule.FunnelInstance f1 = new FunnelModule.FunnelInstance(this, f0.getOutputPort(), ship_out); - f1.addOutput(f0, fabric_out); - } else { - Module.SinkPort ship_in = createOutputPort("ship", WIDTH_PACKET, ""); - instruction.connect(fabric_out); - fabric_in.connect(ship_in); - } + Module horn = new HornModule(); + Module funnel = new FunnelModule(); + Module.SourcePort instruction = createInputPort("instruction", WIDTH_PACKET); + Module.SourcePort fabric_in = createInputPort("fabric_in", WIDTH_PACKET); + Module.SinkPort fabric_out = createOutputPort("fabric_out", WIDTH_PACKET, ""); + if (!inbox) { + FunnelModule.FunnelInstance f0 = new FunnelModule.FunnelInstance(this, instruction, fabric_in); + Module.SourcePort ship_out = createInputPort("ship", WIDTH_WORD); + FunnelModule.FunnelInstance f1 = new FunnelModule.FunnelInstance(this, f0.getOutputPort(), ship_out); + f1.addOutput(f0, fabric_out); + } else { + Module.SinkPort ship_in = createOutputPort("ship", WIDTH_PACKET, ""); + instruction.connect(fabric_out); + fabric_in.connect(ship_in); + } */ int dfifo_width = inbox ? WIDTH_WORD+1 : 1; @@ -163,7 +163,7 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { addPreCrap("assign "+efifo_in.getName()+" = `packet_data("+instruction.getName()+");"); addPreCrap("assign "+ififo_in.getName()+" = hatch ? "+efifo_out.getName()+" : ondeck;"); addPreCrap("assign ondeck = "+ififo_out.getName()+";"); - addPreCrap("assign decremented = (`instruction_is_decr_loop(ondeck) ? {1'b0, loop_counter} : repeat_counter)-1;"); + addPreCrap("assign decremented = ("+SET_OLC_FROM_OLC_MINUS_ONE.verilog("ondeck")+" ? {1'b0, loop_counter} : repeat_counter)-1;"); Assignable data_latch = new SimpleAssignable(inbox ? data_out.getName() : "`packet_data("+data_out.getName()+")"); String data_latch_input = "data_latch_input"; @@ -209,69 +209,63 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { new ConditionalTrigger("(`predicate_met(ondeck) && `instruction_bit_tokenin(ondeck))", token_in) }, new Action[] { - new ConditionalAction("`done_executing(ondeck) && `instruction_is_normal(ondeck)", - new AssignAction(repeat_counter, "1")), - new ConditionalAction("!`should_requeue(ondeck) && `done_executing(ondeck)", ififo_out), - new ConditionalAction("`should_requeue(ondeck) && `done_executing(ondeck)", ififo_in), - new ConditionalAction("`should_requeue(ondeck) && `done_executing(ondeck)", proceed.doFill()), - new ConditionalAction("!`done_executing(ondeck)", - new AssignAction(repeat_counter, - "repeat_counter==`magic_standing_value?`magic_standing_value:decremented")), - new ConditionalAction("`predicate_met(ondeck) && `instruction_is_load_data_to_loop(ondeck)", - new AssignAction(loop_counter, "data_latch_output")), - new ConditionalAction("`predicate_met(ondeck) && `instruction_is_load_immediate_to_loop(ondeck)", - new AssignAction(loop_counter, "`instruction_loop_count_immediate(ondeck)")), - new ConditionalAction("`predicate_met(ondeck) && `instruction_is_decr_loop(ondeck)", - new AssignAction(loop_counter, "loop_counter==0 ? 0 : decremented")), - new ConditionalAction("`predicate_met(ondeck) && `instruction_is_load_data_to_repeat(ondeck)", - new AssignAction(repeat_counter, "data_latch_output")), - new ConditionalAction("`predicate_met(ondeck) && `instruction_is_load_immediate_to_repeat(ondeck)", - new AssignAction(repeat_counter, "`instruction_repeat_count_immediate(ondeck)")), - new ConditionalAction("`predicate_met(ondeck) && `instruction_is_load_standing_to_repeat(ondeck)", - new AssignAction(repeat_counter, "`magic_standing_value")), - new ConditionalAction("`predicate_met(ondeck) &&"+SHIFT.verilog("ondeck"), - new AssignAction(data_latch, - "{ data_latch_output["+(WIDTH_WORD-1-SHIFT.valmaskwidth)+":0], "+ - SHIFT.verilogVal("ondeck")+"}")), - new ConditionalAction("`predicate_met(ondeck) && "+SET_IMMEDIATE.verilog("ondeck"), - new AssignAction(data_latch, - "{ {"+(WIDTH_WORD-FleetTwoFleet.DataLatch_WIDTH)+ - "{"+SET_IMMEDIATE_EXTEND.verilogVal("ondeck")+"}}, "+ - SET_IMMEDIATE.verilogVal("ondeck")+" }")), - new ConditionalAction("`predicate_met(ondeck) && `instruction_is_setflags(ondeck)", - new AssignAction(flag_a, "`new_flag_a(ondeck)")), - new ConditionalAction("`predicate_met(ondeck) && `instruction_is_setflags(ondeck)", - new AssignAction(flag_b, "`new_flag_b(ondeck)")), - (inbox - ? new ConditionalAction("`predicate_met(ondeck) && "+ - "(`instruction_bit_datain(ondeck) || `instruction_bit_tokenin(ondeck))", - new AssignAction(flag_c, dfifo_out.getBits(dfifo_width-1, dfifo_width-1))) - : new ConditionalAction("`predicate_met(ondeck) && "+ - "(!`instruction_bit_datain(ondeck) && `instruction_bit_tokenin(ondeck))", - new AssignAction(flag_c, dfifo_out.getBits(dfifo_width-1, dfifo_width-1))) - ), - inbox ? null : - new ConditionalAction("`predicate_met(ondeck) && "+ - "(`instruction_bit_datain(ondeck))", - new AssignAction(flag_c, "data_latch_input["+WIDTH_WORD+"]")), - new ConditionalAction("`predicate_met(ondeck) && `instruction_bit_datain(ondeck)", data_in), - new ConditionalAction("`predicate_met(ondeck) && `instruction_bit_dataout(ondeck)", data_out), - new ConditionalAction("`predicate_met(ondeck) && `instruction_bit_tokenin(ondeck)", token_in), - new ConditionalAction("`predicate_met(ondeck) && `instruction_bit_tokenout(ondeck)", token_out), - new ConditionalAction("`predicate_met(ondeck) && `instruction_bit_tokenout(ondeck)", - new AssignAction(new SimpleAssignable("`packet_token("+token_out.getName()+")"), - "1")), - new ConditionalAction("`predicate_met(ondeck) && !`instruction_bit_tokenout(ondeck)", - new AssignAction(new SimpleAssignable("`packet_token("+token_out.getName()+")"), - "0")), - new ConditionalAction("`predicate_met(ondeck) && `instruction_bit_latch(ondeck)", - new AssignAction(data_latch, data_latch_input)), - new ConditionalAction("`predicate_met(ondeck) && `instruction_path_from_data(ondeck)", - new AssignAction(new SimpleAssignable("`packet_signal_and_dest("+token_out.getName()+")"), - DISPATCH_PATH.verilogVal(data_latch_input))), - new ConditionalAction("`predicate_met(ondeck) && `instruction_path_from_immediate(ondeck)", - new AssignAction(new SimpleAssignable("`packet_signal_and_dest("+token_out.getName()+")"), - "`instruction_path_immediate(ondeck)")), + new ConditionalAction(" `done_executing(ondeck) && "+MOVE.verilog("ondeck"), new AssignAction(repeat_counter, "1")), + new ConditionalAction("!`should_requeue(ondeck) && `done_executing(ondeck)", ififo_out), + new ConditionalAction(" `should_requeue(ondeck) && `done_executing(ondeck)", ififo_in), + new ConditionalAction(" `should_requeue(ondeck) && `done_executing(ondeck)", proceed.doFill()), + new ConditionalAction("!`done_executing(ondeck)", + new AssignAction(repeat_counter, + "repeat_counter==`magic_standing_value?`magic_standing_value:decremented")) + }); + new Event( + new Object[] { ififo_out, + data_out, + token_out, + ififo_in, + proceed.isEmpty(), + "`predicate_met(ondeck)", + "("+OS.verilog("ondeck")+" || !hatch)", + new ConditionalTrigger("`instruction_bit_datain(ondeck)", data_in), + new ConditionalTrigger("`instruction_bit_tokenin(ondeck)", token_in) + }, + new Action[] { + new ConditionalAction(SET_OLC_FROM_DATA_LATCH.verilog("ondeck"), new AssignAction(loop_counter, "data_latch_output")), + new ConditionalAction(SET_OLC_FROM_IMMEDIATE.verilog("ondeck"), + new AssignAction(loop_counter, SET_OLC_FROM_IMMEDIATE.verilogVal("ondeck"))), + new ConditionalAction(SET_OLC_FROM_OLC_MINUS_ONE.verilog("ondeck"), + new AssignAction(loop_counter, "loop_counter==0 ? 0 : decremented")), + new ConditionalAction(SET_ILC_FROM_DATA_LATCH.verilog("ondeck"), new AssignAction(repeat_counter, "data_latch_output")), + new ConditionalAction(SET_ILC_FROM_IMMEDIATE.verilog("ondeck"), + new AssignAction(repeat_counter, SET_ILC_FROM_IMMEDIATE.verilogVal("ondeck"))), + new ConditionalAction(SET_ILC_FROM_INFINITY.verilog("ondeck"), new AssignAction(repeat_counter, "`magic_standing_value")), + new ConditionalAction(SHIFT.verilog("ondeck"), + new AssignAction(data_latch, + "{ data_latch_output["+(WIDTH_WORD-1-SHIFT.valmaskwidth)+":0], "+ + SHIFT.verilogVal("ondeck")+"}")), + new ConditionalAction(SET_IMMEDIATE.verilog("ondeck"), + new AssignAction(data_latch, + "{ {"+(WIDTH_WORD-FleetTwoFleet.DataLatch_WIDTH)+ + "{"+SET_IMMEDIATE_EXTEND.verilogVal("ondeck")+"}}, "+ + SET_IMMEDIATE.verilogVal("ondeck")+" }")), + new ConditionalAction(SET_FLAGS.verilog("ondeck"), new AssignAction(flag_a, "`new_flag_a(ondeck)")), + new ConditionalAction(SET_FLAGS.verilog("ondeck"), new AssignAction(flag_b, "`new_flag_b(ondeck)")), + new ConditionalAction(inbox + ? "(`instruction_bit_datain(ondeck) || `instruction_bit_tokenin(ondeck))" + : "(!`instruction_bit_datain(ondeck) && `instruction_bit_tokenin(ondeck))", + new AssignAction(flag_c, dfifo_out.getBits(dfifo_width-1, dfifo_width-1))), + inbox?null:new ConditionalAction("`instruction_bit_datain(ondeck)", new AssignAction(flag_c, "data_latch_input["+WIDTH_WORD+"]")), + new ConditionalAction("`instruction_bit_datain(ondeck)", data_in), + new ConditionalAction("`instruction_bit_dataout(ondeck)", data_out), + new ConditionalAction("`instruction_bit_tokenin(ondeck)", token_in), + new ConditionalAction("`instruction_bit_tokenout(ondeck)", token_out), + new ConditionalAction("`instruction_bit_latch(ondeck)", new AssignAction(data_latch, data_latch_input)), + new AssignAction(new SimpleAssignable("`packet_token("+token_out.getName()+")"), "`instruction_bit_tokenout(ondeck)?1:0"), + new ConditionalAction("`instruction_path_from_data(ondeck)", + new AssignAction(new SimpleAssignable("`packet_signal_and_dest("+token_out.getName()+")"), + DISPATCH_PATH.verilogVal(data_latch_input))), + new ConditionalAction("`instruction_path_from_immediate(ondeck)", + new AssignAction(new SimpleAssignable("`packet_signal_and_dest("+token_out.getName()+")"), + "`instruction_path_immediate(ondeck)")), } ); @@ -280,11 +274,6 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { public void dump(PrintWriter pw, boolean fix) { pw.println("`define packet_signal_and_dest(p) { "+PACKET_SIGNAL.verilogVal("p")+", "+PACKET_DEST.verilogVal("p")+" }"); - pw.println("`define instruction_is_load_data_to_repeat(i) "+SET_ILC_FROM_DATA_LATCH.verilog("i")); - pw.println("`define instruction_is_load_data_to_loop(i) "+SET_OLC_FROM_DATA_LATCH.verilog("i")); - pw.println("`define instruction_is_load_immediate_to_repeat(i) "+SET_ILC_FROM_IMMEDIATE.verilog("i")); - pw.println("`define instruction_is_load_immediate_to_loop(i) "+SET_OLC_FROM_IMMEDIATE.verilog("i")); - pw.println("`define instruction_is_load_standing_to_repeat(i) "+SET_ILC_FROM_INFINITY.verilog("i")); pw.println("`define instruction_repeat_count_immediate(i) "+SET_ILC_FROM_IMMEDIATE.verilogVal("i")); pw.println("`define instruction_loop_count_immediate(i) "+SET_OLC_FROM_IMMEDIATE.verilogVal("i")); @@ -292,21 +281,15 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { pw.println("`define instruction_path_from_immediate(i) "+PATH_IMMEDIATE.verilog("i")); pw.println("`define instruction_path_from_data(i) "+PATH_DATA.verilog("i")); - pw.println("`define instruction_is_tail(i) "+TAIL.verilog("i")); - pw.println("`define instruction_is_normal(i) "+MOVE.verilog("i")); - pw.println("`define instruction_is_setflags(i) "+SET_FLAGS.verilog("i")); - - pw.println("`define instruction_is_decr_loop(i) "+SET_OLC_FROM_OLC_MINUS_ONE.verilog("i")); - - pw.println("`define instruction_bit_tokenout(i) (`instruction_is_normal(i) && "+TO.verilog("i")+")"); - pw.println("`define instruction_bit_dataout(i) (`instruction_is_normal(i) && "+DO.verilog("i")+")"); - pw.println("`define instruction_bit_latch(i) (`instruction_is_normal(i) && "+DC.verilog("i")+")"); - pw.println("`define instruction_bit_datain(i) (`instruction_is_normal(i) && "+DI.verilog("i")+")"); - pw.println("`define instruction_bit_tokenin(i) (`instruction_is_normal(i) && "+TI.verilog("i")+")"); + pw.println("`define instruction_bit_tokenout(i) ("+MOVE.verilog("i")+" && "+TO.verilog("i")+")"); + pw.println("`define instruction_bit_dataout(i) ("+MOVE.verilog("i")+" && "+DO.verilog("i")+")"); + pw.println("`define instruction_bit_latch(i) ("+MOVE.verilog("i")+" && "+DC.verilog("i")+")"); + pw.println("`define instruction_bit_datain(i) ("+MOVE.verilog("i")+" && "+DI.verilog("i")+")"); + pw.println("`define instruction_bit_tokenin(i) ("+MOVE.verilog("i")+" && "+TI.verilog("i")+")"); pw.println("`define should_requeue(i) (loop_counter!=0 && !("+OS.verilog("i")+"))"); pw.println("`define predicate_met(i) ("+ "("+ - "!`instruction_is_normal(i) || repeat_counter!=0"+ + "!"+MOVE.verilog("i")+" || repeat_counter!=0"+ ") && ("+ "("+ P_ALWAYS.verilog("i")+ @@ -331,7 +314,7 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { ")"); pw.println("`define new_flag_a(i) `new_flag("+SET_FLAGS_A.verilogVal("i")+")"); pw.println("`define new_flag_b(i) `new_flag("+SET_FLAGS_B.verilogVal("i")+")"); - pw.println("`define done_executing(i) (repeat_counter==0 || repeat_counter==1 || !`instruction_is_normal(i))"); + pw.println("`define done_executing(i) (repeat_counter==0 || repeat_counter==1 || !"+MOVE.verilog("i")+")"); pw.println("`define magic_standing_value (1<<"+SET_ILC_FROM_IMMEDIATE.valmaskwidth+")");