From: adam Date: Thu, 16 Aug 2007 02:39:05 +0000 (+0100) Subject: complete overhaul of fpga code; use gasp-level simulation X-Git-Url: http://git.megacz.com/?a=commitdiff_plain;h=f780e83a8a56d61e3510b05d0e2e5ea5961ddf2f;p=fleet.git complete overhaul of fpga code; use gasp-level simulation --- diff --git a/src/edu/berkeley/fleet/slipway/Generator.java b/src/edu/berkeley/fleet/slipway/Generator.java index bc7f35a..35b606c 100644 --- a/src/edu/berkeley/fleet/slipway/Generator.java +++ b/src/edu/berkeley/fleet/slipway/Generator.java @@ -18,17 +18,21 @@ public class Generator { public static class Module { private int id = 0; - private HashSet instantiatedModules = - new HashSet(); private final String name; public String getName() { return name; } - private final HashSet actions = new HashSet(); + private HashSet instantiatedModules = new HashSet(); + private final ArrayList actions = new ArrayList(); // FIXME: always-alphabetical convention? private final HashMap ports = new HashMap(); private final ArrayList portorder = new ArrayList(); + private StringBuffer crap = new StringBuffer(); + private StringBuffer precrap = new StringBuffer(); + public void addCrap(String s) { crap.append(s); crap.append('\n'); } + public void addPreCrap(String s) { precrap.append(s); precrap.append('\n'); } + public Module(String name) { this.name = name; } @@ -45,9 +49,14 @@ public class Generator { } private abstract class Port { public final String name; + public String getName() { return name; } public final int width; public boolean hasLatch = false; + public boolean supress = false; + public boolean noAssignData = false; public boolean external; + public boolean pretendDriven = false; + public boolean noreg = false; public Port(String name, int width, boolean external) { this.width = width; this.name = name; @@ -67,6 +76,7 @@ public class Generator { private class InstantiatedModule { public final Module module; public final int id; + private final HashMap ports = new HashMap(); public String getName() { return module.getName()+"_"+id; } public InstantiatedModule(Module module) { this.module = module; @@ -81,16 +91,24 @@ public class Generator { } public Port getPort(String name, int width) { if (module.ports.get(name) instanceof SinkPort) - return getInputPort(name, width); - return getOutputPort(name, width, ""); + return getOutputPort(name, width, ""); + return getInputPort(name, width); } public SinkPort getInputPort(String name, int width) { - // FIXME: should not re-instantiate, but so what - return new SinkPort(getName()+"_"+name, width, false, ""); + SinkPort port = (SinkPort)ports.get(name); + if (port == null) { + port = new SinkPort(getName()+"_"+name, width, false, ""); + ports.put(name, port); + } + return port; } public SourcePort getOutputPort(String name, int width, String resetBehavior) { - // FIXME: should not re-instantiate, but so what - return new SourcePort(getName()+"_"+name, width, false); + SourcePort port = (SourcePort)ports.get(name); + if (port == null) { + port = new SourcePort(getName()+"_"+name, width, false); + ports.put(name, port); + } + return port; } } @@ -120,7 +138,7 @@ public class Generator { } public String getAssignments() { StringBuffer sb = new StringBuffer(); - if (external) { + if (external && !pretendDriven) { sb.append("assign " + name +"_a_ = " + name + "_a;\n"); } if (driven != null) { @@ -156,22 +174,27 @@ public class Generator { } else { sb.append("reg " + name +"_r;\n"); sb.append("initial " + name +"_r = 0;\n"); - sb.append("reg ["+(width-1)+":0]" + name +";\n"); - sb.append("initial " + name +" = 0;\n"); + if (!noreg) { + sb.append("reg ["+(width-1)+":0]" + name +";\n"); + sb.append("initial " + name +" = 0;\n"); + } } return sb.toString(); } public String getAssignments() { StringBuffer sb = new StringBuffer(); - if (external) { + if (external && !pretendDriven) { sb.append("assign " + name +"_r_ = " + name + "_r;\n"); - sb.append("assign " + name +"_ = " + name + ";\n"); + if (!noAssignData) { + sb.append("assign " + name +"_ = " + name + ";\n"); + } } return sb.toString(); } } public void dump(PrintWriter pw) { + pw.println("`include \"macros.v\""); pw.println("module "+name+"(clk"); for(String name : portorder) { Port p = ports.get(name); @@ -191,16 +214,16 @@ public class Generator { for(InstantiatedModule m : instantiatedModules) { m.dump(pw); } + pw.println(precrap); pw.println("always @(posedge clk) begin"); - for(String name : portorder) { - Port p = ports.get(name); + for(Port p : ports.values()) { if (p instanceof SourcePort) { SourcePort ip = (SourcePort)p; - if (ip.hasLatch) + if (ip.hasLatch && !ip.supress) pw.println("if (!"+ip.getReq()+" && "+ip.getAck()+") "+ip.getAck()+"<=0;"); } else { SinkPort op = (SinkPort)p; - if (op.hasLatch) + if (op.hasLatch && !op.supress) pw.println("if ("+op.getReq()+" && "+op.getAck()+") begin "+ op.getReq()+"<=0; "+ op.getResetBehavior()+" end"); @@ -210,6 +233,8 @@ public class Generator { for(Action a : actions) a.dump(pw); pw.println(" begin end"); pw.println("end"); + + pw.println(crap); pw.println("endmodule"); } @@ -264,46 +289,230 @@ public class Generator { public static final int WORD_WIDTH = 37; public static final int DESTINATION_WIDTH = 11; public static final int PACKET_WIDTH = WORD_WIDTH + DESTINATION_WIDTH; + public static final int INSTRUCTION_WIDTH = WORD_WIDTH; public static void main(String[] s) throws Exception { String prefix = "src/edu/berkeley/fleet/slipway/"; PrintWriter pw; - Module funnel = new Module("funnel"); - Module.SinkPort out = funnel.getOutputPort("out", PACKET_WIDTH, ""); + mkfunnel("funnel", prefix); + mkhorn( "horn", prefix, PACKET_WIDTH-1, DESTINATION_WIDTH-1, 0, 0); + mkhorn( "ihorn", prefix, PACKET_WIDTH-1, 34, 24, 0); + + Module fifostage = mkfifo("fifostage", 0, null, prefix); + Module fifo4 = mkfifo("fifo4", 4, fifostage, prefix); + Module fifoship = mkfifo("fifo", 4, fifo4, prefix); + mkoutbox("outbox", false, prefix, fifo4); + mkoutbox("inbox", true, prefix, fifo4); + + mkkill("kill", prefix); + } + + private static Module mkkill(String name, String prefix) throws Exception { + Module killm = new Module(name); + Module.SourcePort instr = killm.getInputPort("instr", INSTRUCTION_WIDTH); + Module.SinkPort kill = killm.getOutputPort("kill", INSTRUCTION_WIDTH+1, ""); + Module.SinkPort notkill = killm.getOutputPort("notkill", INSTRUCTION_WIDTH, ""); + killm.addPreCrap(" reg ifull;"); + killm.addPreCrap(" initial ifull = 0;"); + killm.new Action(new Object[] { "!ifull", instr, notkill }, + new Object[] { "notkill = instr;", instr, "ifull = 1;" } + ); + killm.new Action(new Object[] { kill, "ifull", "`instruction_is_kill(notkill)" }, + new Object[] { kill, "ifull=0;", + "kill = { `instruction_bit_kill_only_standing(notkill), `instruction_count(notkill) };" } + ); + killm.new Action(new Object[] { notkill, "ifull", "!`instruction_is_kill(notkill)" }, + new Object[] { notkill, "ifull=0;" } + ); + PrintWriter pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/"+name+".v"))); + killm.dump(pw); + pw.flush(); + return killm; + } + + private static Module mkfunnel(String name, String prefix) throws Exception { + Module funnel = new Module(name); + Module.SinkPort out = funnel.getOutputPort("out", PACKET_WIDTH, ""); Module.SourcePort in1 = funnel.getInputPort("in1", PACKET_WIDTH); Module.SourcePort in2 = funnel.getInputPort("in2", PACKET_WIDTH); funnel.new Action(new Object[] { in1, out }, new Object[] { in1, out, "out = in1;" }); funnel.new Action(new Object[] { in2, out }, new Object[] { in2, out, "out = in2;" }); - pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/funnel.v"))); + PrintWriter pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/"+name+".v"))); funnel.dump(pw); pw.flush(); + return funnel; + } + + private static Module mkoutbox(String name, boolean inbox, String prefix, Module fifo) throws Exception { + Module box = new Module(name); + Module.SourcePort instr = box.getInputPort("instr", INSTRUCTION_WIDTH); + //instr.hasLatch = true; + //instr.supress = true; + Module.SourcePort fabric_in = box.getInputPort("fabric_in", PACKET_WIDTH); + Module.SinkPort fabric_out = box.getOutputPort("fabric_out", PACKET_WIDTH, ""); + fabric_out.hasLatch = true; + //fabric_out.supress = true; - mkhorn( "horn", prefix, PACKET_WIDTH-1, DESTINATION_WIDTH-1, 0, 0); - mkhorn("ihorn", prefix, PACKET_WIDTH-1, 34, 24, 0); + Module.InstantiatedModule dfifo = box.new InstantiatedModule(fifo); + fabric_in.connect(dfifo.getInputPort("in", PACKET_WIDTH)); + + Module.SourcePort dfifo_out = dfifo.getOutputPort("out", PACKET_WIDTH, ""); + String fabric_in_d0 = dfifo_out.name; + String fabric_in_r0 = fabric_in_d0+"_r"; + String fabric_in_a0 = fabric_in_d0+"_a"; + dfifo_out.hasLatch = true; + + Module.SourcePort ship_out = null; + if (!inbox) { + ship_out = box.getInputPort("ship", WORD_WIDTH); + ship_out.hasLatch = true; + } + + Module.SinkPort ship_in = null; + if (inbox) { + ship_in = box.getOutputPort("ship", PACKET_WIDTH, ""); + ship_in.hasLatch = true; + } + + box.addPreCrap(" reg[(`INSTRUCTION_WIDTH-1):0] ondeck;"); + box.addPreCrap(" reg[(`COUNT_WIDTH-1):0] repcount;"); + box.addPreCrap(" initial ondeck=0;"); + box.addPreCrap(" reg ondeck_full; initial ondeck_full=0;"); + box.addPreCrap(" reg newmayproceed; initial newmayproceed=1;"); + box.addPreCrap(" reg dorepeat; initial dorepeat=0;"); + box.addPreCrap(" reg dorepeatkill; initial dorepeatkill=0;"); + box.addPreCrap(" reg dokill; initial dokill=0;"); + box.addPreCrap(" reg clogged; initial clogged=0;"); + + // FIXME: destination + Module.SinkPort token_out = fabric_out; + Module.SourcePort token_in = dfifo_out; + Module.SinkPort data_out = inbox ? ship_in : fabric_out; + Module.SourcePort data_in = inbox ? dfifo_out : ship_out; + + Module.InstantiatedModule ififo = box.new InstantiatedModule(fifo); + Module.SinkPort ififo_in = ififo.getInputPort("in", PACKET_WIDTH); + ififo_in.hasLatch = true; + Module.SourcePort ififo_out = ififo.getOutputPort("out", PACKET_WIDTH, ""); + + // Clog (must be first) + box.new Action( + new Object[] { ififo_out, "newmayproceed==1", "`instruction_is_clog("+ififo_out.getName()+")" }, + new Object[] { ififo_out, "clogged <= 1;", "newmayproceed<=0;" } + ); + + // UnClog + box.new Action( + new Object[] { instr, "clogged==1", "`instruction_is_unclog(instr)" }, + new Object[] { instr, "clogged <= 0;", "newmayproceed<=1;" } + ); + + // First Kill + box.new Action( + new Object[] { instr, ififo_out, "`instruction_is_kill(instr)", "!`instruction_is_unclog(instr)", "newmayproceed==1" }, + new Object[] { instr, ififo_out, + "if (`instruction_count(instr)!=0)"+ + " begin repcount <= `instruction_count(instr)-1; newmayproceed <= 0; "+ + " dorepeatkill <= 1; end else begin newmayproceed<=1; end" } + ); - Module fifostage = new Module("fifostage"); - Module.SourcePort in = fifostage.getInputPort("in", PACKET_WIDTH); - Module.SinkPort outf = fifostage.getOutputPort("out", PACKET_WIDTH, ""); - fifostage.new Action(new Object[] { in, outf }, new Object[] { in, outf, "out = in;" }); - pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/fifostage.v"))); - fifostage.dump(pw); + // Kill + box.new Action( + new Object[] { "dokill==1" }, + new Object[] { "dokill<=0;", + "if (`instruction_count(ondeck)!=0)"+ + " begin repcount <= `instruction_count(ondeck)-1;"+ + " dorepeatkill <= 1; end else begin newmayproceed<=1; end" } + ); + + // RepKill + box.new Action( + new Object[] { "dorepeatkill==1", ififo_out }, + new Object[] { "dorepeatkill<=0;", ififo_out, "dokill<=1;", "`instruction_count(ondeck)<=repcount;" } + ); + + // Enqueue + box.new Action( + new Object[] { instr, ififo_in, "!`instruction_is_kill(instr)" }, + new Object[] { instr, ififo_in, ififo_in.getName()+"<=instr;" } + ); + + // New + box.new Action( + new Object[] { ififo_out, "ondeck_full==0", "newmayproceed==1" }, + new Object[] { ififo_out, "ondeck_full<=1;", "newmayproceed<=0;", + "ondeck<="+ififo_out.getName()+";" } + ); + + // RepeatExecute + box.new Action( + new Object[] { "dorepeat==1", }, + new Object[] { "dorepeat<=0;", "ondeck_full<=1;", "`instruction_count(ondeck)<=repcount;" } + ); + + for(int di=0; di<=1; di++) + for(int dout=0; dout<=1; dout++) + for(int tout=0; tout<=1; tout++) + for(int ti=0; ti<=1; ti++) { + box.new Action( + new Object[] { "ondeck_full==1", + data_out, + token_out, + ififo_in, + (di==1 ? "" : "!")+"`instruction_bit_datain(ondeck)", + (di==1 ? data_in : "1"), + (ti==1 ? "" : "!")+"`instruction_bit_tokenin(ondeck)", + (ti==1 ? token_in : "1"), + (dout==1 ? "" : "!")+"`instruction_bit_dataout(ondeck)", + (tout==1 ? "" : "!")+"`instruction_bit_tokenout(ondeck)" + }, + new Object[] { "ondeck_full<=0;", + "if (`instruction_count(ondeck)==1 || `instruction_bit_recycle(ondeck)) newmayproceed<=1;", + "if (`instruction_bit_recycle(ondeck) && `instruction_count(ondeck)!=1) "+ + " begin "+ififo_in.getName()+"<=ondeck; "+ + " `instruction_count("+ififo_in.getName()+")<=(`instruction_count(ondeck)==0?0:`instruction_count(ondeck)-1);"+ + " "+ififo_in.getReq()+"<=1; end", + "if (!`instruction_bit_recycle(ondeck) && `instruction_count(ondeck)!=1) "+ + " dorepeat <= 1;", + "repcount <= (`instruction_count(ondeck)==0 ? 0 : (`instruction_count(ondeck)-1));", + (di==1 ? data_in : ""), + (dout==1 ? data_out : ""), + (ti==1 ? token_in : ""), + (tout==1 ? token_out : ""), + ("if (`instruction_bit_latch(ondeck)) "+ + (inbox ? data_out.getName() : "`packet_data("+data_out.getName()+")")+ + "<="+ + (inbox ? "`packet_data("+data_in.getName()+")" : data_in.getName())+";"), + (tout==1 ? "`packet_dest("+token_out.getName()+")<=`instruction_bit_dest(ondeck);" : ""), + (dout==1 && !inbox ? "`packet_dest("+data_out.getName()+")<=`instruction_bit_dest(ondeck);" : "") + } + ); + } + + PrintWriter pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/"+name+".v"))); + box.dump(pw); pw.flush(); + return box; + } - Module fifo4 = new Module("fifo4"); + private static Module mkfifo(String name, int len, Module instance, String prefix) throws Exception { + Module fifo4 = new Module(name); Module.SourcePort inx = fifo4.getInputPort("in", PACKET_WIDTH); Module.SinkPort outx = fifo4.getOutputPort("out", PACKET_WIDTH, ""); - int len = 4; Module.InstantiatedModule[] stages = new Module.InstantiatedModule[len]; - for(int i=0; i<=len; i++) { - if (i 0) && - (!kill_only_standing || `instruction_count(instruction)==0)) - begin - kill_count = kill_count - 1; - have_instruction = 0; - parse_instruction = 0; - end - - if (parse_instruction) begin - need_to_read_token = `instruction_bit_tokenin(instruction); - need_to_read_data = `instruction_bit_datain(instruction); - `packet_dest(`data_out_d) = `instruction_bit_dest(instruction); - `packet_dest(`token_out_d) = `instruction_bit_dest(instruction); - need_to_send_data = `instruction_bit_dataout(instruction); - need_to_send_token = `instruction_bit_tokenout(instruction); - have_instruction = 1; - parse_instruction = 0; - end - - // return to zero - if (!`token_in_r && `token_in_a) `token_in_a = 0; - if (!`data_in_r && `data_in_a) `data_in_a = 0; - - if (have_instruction && - (!need_to_read_token || (`token_in_r && !`token_in_a)) && - (!need_to_read_data || (`data_in_r && !`data_in_a)) - ) begin - if (need_to_read_token) begin - `token_in_a = 1; - need_to_read_token = 0; - end - if (need_to_read_data) begin - `data_in_a = 1; - need_to_read_data = 0; - end - if (`instruction_bit_latch(instruction)) begin - `packet_data(`data_out_d) = `data_in_d; - `extra - end - fire_ok = 1; - end - - end - end diff --git a/src/edu/berkeley/fleet/slipway/fifo4.v b/src/edu/berkeley/fleet/slipway/fifo4.v deleted file mode 100644 index 1f04561..0000000 --- a/src/edu/berkeley/fleet/slipway/fifo4.v +++ /dev/null @@ -1,97 +0,0 @@ -module fifo4(clk - , in_r, in_a_, in - , out_r_, out_a, out_ - ); - - input clk; - wire fifostage_3_in_a; -wire fifostage_3_in_r; -wire [47:0]fifostage_3_in; - - output out_r_; -input out_a; -output [47:0]out_; -wire out_r; -wire [47:0]out; - - wire fifostage_0_out_r; -wire [47:0]fifostage_0_out; -wire fifostage_0_out_a; - - wire fifostage_2_out_r; -wire [47:0]fifostage_2_out; -wire fifostage_2_out_a; - - wire fifostage_1_in_a; -wire fifostage_1_in_r; -wire [47:0]fifostage_1_in; - - wire fifostage_0_in_a; -wire fifostage_0_in_r; -wire [47:0]fifostage_0_in; - - wire fifostage_1_out_r; -wire [47:0]fifostage_1_out; -wire fifostage_1_out_a; - - wire fifostage_3_out_r; -wire [47:0]fifostage_3_out; -wire fifostage_3_out_a; - - input in_r; -output in_a_; -input [47:0]in; -wire in_a; - - wire fifostage_2_in_a; -wire fifostage_2_in_r; -wire [47:0]fifostage_2_in; - - - assign out_r_ = out_r; -assign out_ = out; - - assign fifostage_1_in_r = fifostage_0_out_r; -assign fifostage_0_out_a = fifostage_1_in_a; -assign fifostage_1_in = fifostage_0_out; - - assign fifostage_3_in_r = fifostage_2_out_r; -assign fifostage_2_out_a = fifostage_3_in_a; -assign fifostage_3_in = fifostage_2_out; - - - - assign fifostage_2_in_r = fifostage_1_out_r; -assign fifostage_1_out_a = fifostage_2_in_a; -assign fifostage_2_in = fifostage_1_out; - - assign out_r = fifostage_3_out_r; -assign fifostage_3_out_a = out_a; -assign out = fifostage_3_out; - - assign in_a_ = in_a; -assign fifostage_0_in_r = in_r; -assign in_a = fifostage_0_in_a; -assign fifostage_0_in = in; - - - fifostage fifostage_1(clk -, fifostage_1_in_r, fifostage_1_in_a, fifostage_1_in -, fifostage_1_out_r, fifostage_1_out_a, fifostage_1_out - ); - fifostage fifostage_2(clk -, fifostage_2_in_r, fifostage_2_in_a, fifostage_2_in -, fifostage_2_out_r, fifostage_2_out_a, fifostage_2_out - ); - fifostage fifostage_0(clk -, fifostage_0_in_r, fifostage_0_in_a, fifostage_0_in -, fifostage_0_out_r, fifostage_0_out_a, fifostage_0_out - ); - fifostage fifostage_3(clk -, fifostage_3_in_r, fifostage_3_in_a, fifostage_3_in -, fifostage_3_out_r, fifostage_3_out_a, fifostage_3_out - ); -always @(posedge clk) begin - begin end -end -endmodule diff --git a/src/edu/berkeley/fleet/slipway/fifostage.v b/src/edu/berkeley/fleet/slipway/fifostage.v deleted file mode 100644 index 1167016..0000000 --- a/src/edu/berkeley/fleet/slipway/fifostage.v +++ /dev/null @@ -1,36 +0,0 @@ -module fifostage(clk - , in_r, in_a_, in - , out_r_, out_a, out_ - ); - - input clk; - output out_r_; -input out_a; -output [47:0]out_; -reg out_r; -initial out_r = 0; -reg [47:0]out; -initial out = 0; - - input in_r; -output in_a_; -input [47:0]in; -reg in_a; -initial in_a = 0; - - assign out_r_ = out_r; -assign out_ = out; - - assign in_a_ = in_a; - -always @(posedge clk) begin -if (!in_r && in_a) in_a<=0; -if (out_r && out_a) begin out_r<=0; end -if (1 && in_r && !in_a && !out_r && !out_a) begin -in_a <= 1; -out_r <= 1; -out = in; -end else - begin end -end -endmodule diff --git a/src/edu/berkeley/fleet/slipway/funnel.v b/src/edu/berkeley/fleet/slipway/funnel.v deleted file mode 100644 index e2f5f62..0000000 --- a/src/edu/berkeley/fleet/slipway/funnel.v +++ /dev/null @@ -1,51 +0,0 @@ -module funnel(clk - , out_r_, out_a, out_ - , in1_r, in1_a_, in1 - , in2_r, in2_a_, in2 - ); - - input clk; - output out_r_; -input out_a; -output [47:0]out_; -reg out_r; -initial out_r = 0; -reg [47:0]out; -initial out = 0; - - input in2_r; -output in2_a_; -input [47:0]in2; -reg in2_a; -initial in2_a = 0; - - input in1_r; -output in1_a_; -input [47:0]in1; -reg in1_a; -initial in1_a = 0; - - assign out_r_ = out_r; -assign out_ = out; - - assign in2_a_ = in2_a; - - assign in1_a_ = in1_a; - -always @(posedge clk) begin -if (out_r && out_a) begin out_r<=0; end -if (!in1_r && in1_a) in1_a<=0; -if (!in2_r && in2_a) in2_a<=0; -if (1 && in2_r && !in2_a && !out_r && !out_a) begin -in2_a <= 1; -out_r <= 1; -out = in2; -end else -if (1 && in1_r && !in1_a && !out_r && !out_a) begin -in1_a <= 1; -out_r <= 1; -out = in1; -end else - begin end -end -endmodule diff --git a/src/edu/berkeley/fleet/slipway/horn.v b/src/edu/berkeley/fleet/slipway/horn.v deleted file mode 100644 index dea8115..0000000 --- a/src/edu/berkeley/fleet/slipway/horn.v +++ /dev/null @@ -1,54 +0,0 @@ -module horn(clk - , in_r, in_a_, in - , out0_r_, out0_a, out0_ - , out1_r_, out1_a, out1_ - ); - - input clk; - output out1_r_; -input out1_a; -output [47:0]out1_; -reg out1_r; -initial out1_r = 0; -reg [47:0]out1; -initial out1 = 0; - - input in_r; -output in_a_; -input [47:0]in; -reg in_a; -initial in_a = 0; - - output out0_r_; -input out0_a; -output [47:0]out0_; -reg out0_r; -initial out0_r = 0; -reg [47:0]out0; -initial out0 = 0; - - assign out1_r_ = out1_r; -assign out1_ = out1; - - assign in_a_ = in_a; - - assign out0_r_ = out0_r; -assign out0_ = out0; - -always @(posedge clk) begin -if (!in_r && in_a) in_a<=0; -if (out0_r && out0_a) begin out0_r<=0; end -if (out1_r && out1_a) begin out1_r<=0; end -if (1 && (in[0]==1) && in_r && !in_a && !out1_r && !out1_a && !out0_r && !out0_a) begin -in_a <= 1; -out1_r <= 1; -out1 = { in[47:11], (in[10:0] >> 1) }; -end else -if (1 && (in[0]==0) && in_r && !in_a && !out1_r && !out1_a && !out0_r && !out0_a) begin -in_a <= 1; -out0_r <= 1; -out0 = { in[47:11], (in[10:0] >> 1) }; -end else - begin end -end -endmodule diff --git a/src/edu/berkeley/fleet/slipway/ihorn.v b/src/edu/berkeley/fleet/slipway/ihorn.v deleted file mode 100644 index dcc6e68..0000000 --- a/src/edu/berkeley/fleet/slipway/ihorn.v +++ /dev/null @@ -1,54 +0,0 @@ -module ihorn(clk - , in_r, in_a_, in - , out0_r_, out0_a, out0_ - , out1_r_, out1_a, out1_ - ); - - input clk; - output out1_r_; -input out1_a; -output [47:0]out1_; -reg out1_r; -initial out1_r = 0; -reg [47:0]out1; -initial out1 = 0; - - input in_r; -output in_a_; -input [47:0]in; -reg in_a; -initial in_a = 0; - - output out0_r_; -input out0_a; -output [47:0]out0_; -reg out0_r; -initial out0_r = 0; -reg [47:0]out0; -initial out0 = 0; - - assign out1_r_ = out1_r; -assign out1_ = out1; - - assign in_a_ = in_a; - - assign out0_r_ = out0_r; -assign out0_ = out0; - -always @(posedge clk) begin -if (!in_r && in_a) in_a<=0; -if (out0_r && out0_a) begin out0_r<=0; end -if (out1_r && out1_a) begin out1_r<=0; end -if (1 && (in[24]==0) && in_r && !in_a && !out1_r && !out1_a && !out0_r && !out0_a) begin -in_a <= 1; -out0_r <= 1; -out0 = { in[47:35], (in[34:24] >> 1) , in[23:0] }; -end else -if (1 && (in[24]==1) && in_r && !in_a && !out1_r && !out1_a && !out0_r && !out0_a) begin -in_a <= 1; -out1_r <= 1; -out1 = { in[47:35], (in[34:24] >> 1) , in[23:0] }; -end else - begin end -end -endmodule diff --git a/src/edu/berkeley/fleet/slipway/inbox.v b/src/edu/berkeley/fleet/slipway/inbox.v deleted file mode 100644 index 5e041a5..0000000 --- a/src/edu/berkeley/fleet/slipway/inbox.v +++ /dev/null @@ -1,50 +0,0 @@ -`include "macros.v" - -module inbox(clk, - instr_r, instr_a_, instr_d, - fabric_in_r, fabric_in_a_, fabric_in_d, - fabric_out_r_, fabric_out_a, fabric_out_d_, - ship_r_, ship_a, ship_d_ - ); - - input clk; - - output fabric_in_a_; - input fabric_in_r; - input [(`PACKET_WIDTH-1):0] fabric_in_d; - `output(fabric_out_r, fabric_out_r_, fabric_out_a, [(`PACKET_WIDTH-1):0], fabric_out_d_) - `defreg(fabric_out_d_, [(`PACKET_WIDTH-1):0], fabric_out_d) - `output(ship_r, ship_r_, ship_a, [(`PACKET_WIDTH-1):0], ship_d_) - reg [(`PACKET_WIDTH-1):0] ship_d; - assign ship_d_ = { `packet_dest(ship_d), `packet_data(ship_d) }; - - `input(instr_r, instr_a, instr_a_, [(`INSTRUCTION_WIDTH-1):0], instr_d) - - wire fabric_in_a0_; - reg fabric_in_a0; - assign fabric_in_a0_ = fabric_in_a0; - - `define token_in_r fabric_in_r0 - `define token_in_a fabric_in_a0 - `define token_in_d fabric_in_d0 - - `define data_out_r ship_r - `define data_out_a ship_a - `define data_out_d ship_d - - `define token_out_r fabric_out_r - `define token_out_a fabric_out_a - `define token_out_d fabric_out_d - - `define data_in_d `packet_data(fabric_in_d0) - `define data_in_a fabric_in_a0 - `define data_in_r fabric_in_r0 - - wire [(`PACKET_WIDTH-1):0] fabric_in_d0; - - fifo4 dfifo(clk, fabric_in_r, fabric_in_a_, fabric_in_d, - fabric_in_r0, fabric_in_a0_, fabric_in_d0); - - `define extra `packet_dest(`data_out_d) = `packet_dest(fabric_in_d0); - `include "box.inc" -endmodule diff --git a/src/edu/berkeley/fleet/slipway/macros.v b/src/edu/berkeley/fleet/slipway/macros.v index 0f54310..b03fe7b 100644 --- a/src/edu/berkeley/fleet/slipway/macros.v +++ b/src/edu/berkeley/fleet/slipway/macros.v @@ -26,6 +26,9 @@ `define instruction_bit_kill_only_standing(i) (`instruction_bit_tokenin(i)) `define instruction_count(instruction) instruction[(1+`DESTINATION_ADDRESS_BITS+`COUNT_BITS-1):(1+`DESTINATION_ADDRESS_BITS)] +`define instruction_is_clog(instruction) (`instruction_count(instruction)==0 && !`instruction_bit_tokenin(instruction) && !`instruction_bit_datain(instruction) && !`instruction_bit_tokenout(instruction) && !`instruction_bit_dataout(instruction)) +`define instruction_is_unclog(instruction) (`instruction_bit_kill_only_standing(instruction) && `instruction_is_kill(instruction)) + `define defreg(signame,width,regname) reg width regname; wire width signame; assign signame = regname; initial regname = 0; `define input(r, a, a_, w, d) input r; output a_; reg a; assign a_=a; input w d; initial a=0; `define output(r, r_, a, w, d) output r_; input a; reg r; assign r_=r; output w d; initial r=0; diff --git a/src/edu/berkeley/fleet/slipway/outbox.v b/src/edu/berkeley/fleet/slipway/outbox.v deleted file mode 100644 index 4471881..0000000 --- a/src/edu/berkeley/fleet/slipway/outbox.v +++ /dev/null @@ -1,48 +0,0 @@ -`include "macros.v" - -module outbox(clk, - instr_r, instr_a_, instr_d, - fabric_in_r, fabric_in_a_, fabric_in_d, - fabric_out_r_, fabric_out_a, fabric_out_d_, - ship_r, ship_a_, ship_d - ); - - input clk; - - output fabric_in_a_; - input fabric_in_r; - input [(`DATAWIDTH-1):0] fabric_in_d; - //`input(fabric_in_r, fabric_in_a, fabric_in_a_, [(`DATAWIDTH-1):0], fabric_in_d) - `output(fabric_out_r, fabric_out_r_, fabric_out_a, [(`PACKET_WIDTH-1):0], fabric_out_d_) - `defreg(fabric_out_d_, [(`PACKET_WIDTH-1):0], fabric_out_d) - `input(ship_r, ship_a, ship_a_, [(`DATAWIDTH-1):0], ship_d) - `input(instr_r, instr_a, instr_a_, [(`INSTRUCTION_WIDTH-1):0], instr_d) - - wire fabric_in_a0_; - reg fabric_in_a0; - assign fabric_in_a0_ = fabric_in_a0; - - `define token_in_r fabric_in_r0 - `define token_in_a fabric_in_a0 - `define token_in_d fabric_in_d0 - - `define data_out_r fabric_out_r - `define data_out_a fabric_out_a - `define data_out_d fabric_out_d - - `define token_out_r fabric_out_r - `define token_out_a fabric_out_a - `define token_out_d fabric_out_d - - `define data_in_d ship_d - `define data_in_a ship_a - `define data_in_r ship_r - - wire [(`PACKET_WIDTH-1):0] fabric_in_d0; - - fifo4 dfifo(clk, fabric_in_r, fabric_in_a_, fabric_in_d, - fabric_in_r0, fabric_in_a0_, fabric_in_d0); - - `define extra - `include "box.inc" -endmodule