From 00a24804a149f806f1c9113bff11fd2f555e5c8a Mon Sep 17 00:00:00 2001 From: Adam Megacz Date: Tue, 10 Mar 2009 18:54:48 +0000 Subject: [PATCH] update marina.xml --- .../sun/vlsi/chips/marina/test/ChainControls.java | 2 +- .../vlsi/chips/marina/test/InstructionStopper.java | 5 +- .../com/sun/vlsi/chips/marina/test/Marina.java | 2 +- .../com/sun/vlsi/chips/marina/test/MarinaTest.java | 23 +- .../sun/vlsi/chips/marina/test/ProperStopper.java | 22 +- testCode/marina.xml | 925 +++++++++----------- 6 files changed, 446 insertions(+), 533 deletions(-) diff --git a/testCode/com/sun/vlsi/chips/marina/test/ChainControls.java b/testCode/com/sun/vlsi/chips/marina/test/ChainControls.java index cb366d3..1739500 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/ChainControls.java +++ b/testCode/com/sun/vlsi/chips/marina/test/ChainControls.java @@ -21,7 +21,7 @@ public class ChainControls { /** The path has the form: * chipName.chainName.instanceName1.instanceName2 ... */ - private ChainControl getChainControlFromPath(String path) { + public ChainControl getChainControlFromPath(String path) { for (String chainName : chainToControl.keySet()) { if (path.startsWith(chainName)) return chainToControl.get(chainName); } diff --git a/testCode/com/sun/vlsi/chips/marina/test/InstructionStopper.java b/testCode/com/sun/vlsi/chips/marina/test/InstructionStopper.java index 689ee9b..b9103c3 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/InstructionStopper.java +++ b/testCode/com/sun/vlsi/chips/marina/test/InstructionStopper.java @@ -23,7 +23,7 @@ public class InstructionStopper extends ProperStopper { BitVector d = new BitVector(37, "token"); d.setFromLong(0); BitVector t = new BitVector(1, "token"); t.setFromLong(0); BitVector a = new BitVector(14, "addr"); a.setFromLong(0); - TORPEDO = d.cat(t).cat(a); + TORPEDO = t.cat(a).cat(d); } // Convert a Berkeley BitVector into a Sun BitVector private BitVector berkToSun(edu.berkeley.fleet.api.BitVector berkBits) { @@ -66,7 +66,8 @@ public class InstructionStopper extends ProperStopper { } BitVector t = new BitVector(1, "token"); t.setFromLong(1); BitVector a = new BitVector(14, "addr"); a.setFromLong(0); - super.fill(instr.cat(t).cat(a)); + //super.fill(instr.cat(t).cat(a)); + super.fill(t.cat(a).cat(instr)); } @Override public BitVector drain() { diff --git a/testCode/com/sun/vlsi/chips/marina/test/Marina.java b/testCode/com/sun/vlsi/chips/marina/test/Marina.java index ee48a9c..8cf3e35 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/Marina.java +++ b/testCode/com/sun/vlsi/chips/marina/test/Marina.java @@ -76,7 +76,7 @@ public class Marina { // The name of the scan chain // The instance path, from the top cell of the netlist, of the instance of infinityWithCover - private final ChainControls cc; // specifies the scan chain + public final ChainControls cc; // specifies the scan chain private final ChipModel model; public final ProperStopper data; public final InstructionStopper instrIn; diff --git a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java index 320ef71..930f2e7 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java +++ b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java @@ -244,9 +244,11 @@ public class MarinaTest { ((SimulationModel)model).start("nanosim -c cfg", netListName, 0, !cmdArgs.jtagShift); + /* ctD.testAllChains("marina", Infrastructure.SEVERITY_WARNING); ctR.testAllChains("marina", Infrastructure.SEVERITY_WARNING); ctC.testAllChains("marina", Infrastructure.SEVERITY_WARNING); + */ ccs.addChain(Marina.DATA_CHAIN, ccD); ccs.addChain(Marina.REPORT_CHAIN, ccR); @@ -254,9 +256,11 @@ public class MarinaTest { marina = new Marina(ccs, model, !cmdArgs.jtagShift, indenter); - //System.out.println("launching"); - //ChainG.createAndShowGUI(marina.cc.getChainControlFromPath(Marina.REPORT_CHAIN)); - //System.out.println(" launched."); + /* + System.out.println("launching"); + ChainG.createAndShowGUI(marina.cc.getChainControlFromPath(Marina.REPORT_CHAIN)); + System.out.println(" launched."); + */ doOneTest(cmdArgs.testNum); @@ -1981,24 +1985,31 @@ public class MarinaTest { prln("Begin testSouthRecirculate"); adjustIndent(2); + //int AMOUNT = Marina.SOUTH_RING_CAPACITY; + int AMOUNT = 1; + marina.enableInstructionSend(false); marina.enableInstructionRecirculate(true); prln("Completely fill south ring"); - for (int i=0; i out = marina.instrIn.drainMany(); - for (int i=0; i - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + '> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - + + + + + + + + + + + + '> - - - - - - - - - - - - - + + + + + + + + + + + + + + '> @@ -279,11 +254,6 @@ '> - &countersL_cntScnThree_sin; - &countersL_cntScnThree_sin; - &countersL_cntScnThree_sin; -'> @@ -295,319 +265,235 @@ &countersL_cntScnFour_sin; '> + &countersL_cntScnFour_sin; &countersL_cntScnTwelve_sin; - &countersL_cntScnTwelve_sin; - &countersL_cntScnNine_sin; -'> - &dockPartOD_ringSkipMoveLit_si_1_; -'> - &stepsM_shortRing_sir_1_; - &dockPartOD_skipCountMoveLit_sin; -'> - &dockPartOD_skipCount_sin; - &dockPartsK_moveLit_sin; -'> - &scanK_scanKx2_sin; - &scanK_scanKx6_sin; - &scanK_scanKx9_sin; + &countersL_cntScnThree_sin; + &countersL_cntScnTwelve_sin; '> - &scanK_scanKhx5_sin; + &stageGroupsM_dockWagNine_sir_1_; + &stageGroupsM_centerFive_sir_1_; + &stagesM_litDockStage_sir_1_; '> &scanJ_scanEx3hor_sir_1_; '> - &scanJ_scanFx3hor_sic_1_; - &scanJ_scanFx1vert_sic_1_; -'> - &scanJ_scanEx2vert_sir_1_; -'> - &scanJ_scanFx2vert_sic_1_; -'> - &scanJ_scanEx2vert_sir_1_; -'> - &scanJ_scanFx2vert_sic_1_; -'> - &scanJ_scanEx1vertA_sir_1_; -'> - &scanK_scanEx1vertFdn_sor_8_; + + '> - &scanK_scanEx1vertFup_sir_1_; + &gaspM_fillScanControl_si_1_; '> - '> - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; -'> - ®istersJ_data1in38scan_sid_1_; - ®istersJ_addr1in14scan_sin; -'> - - - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; - &latchGroupsK_latchWscan_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; +'> + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; + &latchGroupsK_latchWscM2_sin; '> '> - - -'> '> - -'> - - + '> - - - + + '> - + + '> - + + '> - - - - - -'> - - -'> - - - - - - -'> - - - - - - - - - -'> - &stageGroupsL_properStopper_sic_1_; -'> - &stageGroupsL_properStopper_sid_1_; + + +'> + + + +'> + &stageGroupsM_epiRQod_sir_1_; + &stageGroupsM_m1predicate_sir_1_; +'> + &stagesM_altStartDockStage_sir_1_; + &stagesM_plainDockStage_sir_1_; + &stagesM_plainDockStage_sir_1_; + &stagesM_plainDockStage_sir_1_; + &stagesM_plainDockStage_sir_1_; + &stagesM_plainDockStage_sir_1_; + &stagesM_plainDockStage_sir_1_; + &stagesM_altEndDockStage_sir_1_; +'> + &stagesM_epiDockStage_sir_1_; + &stagesM_rqDockStage_sir_1_; + &stagesM_onDeckDockStage_sir_1_; +'> + &stageGroupsM_properStopper_sic_1_; +'> + &stageGroupsM_properStopper_sid_1_; &countersL_instructionCount_sid_1_; '> - &stageGroupsL_properStopper_sir_1_; + &stageGroupsM_properStopper_sir_1_; '> - &stageGroupsL_fillDrainCount_sic_1_; + &stagesM_mOneDockStage_sir_1_; + &stagesM_predDockStage_sir_1_; '> - &stageGroupsL_fillDrainCount_sid_1_; + &stageGroupsM_fillDrainCount_sic_1_; '> - &stageGroupsL_upDown8weak_sir_1_; - &stageGroupsL_fillDrainCount_sir_1_; - &stageGroupsL_upDown8weak_sor_8_; + &stageGroupsM_fillDrainCount_sid_1_; '> - &stagesL_fillStage_sic_1_; - &stagesL_drainStage_sic_1_; + &stageGroupsM_upDown8weak_sir_1_; + &stageGroupsM_fillDrainCount_sir_1_; '> - &stagesL_fillStage_sid_1_; + &stagesM_fillStage_sic_1_; + &stagesM_drainStage_sic_1_; '> - &stagesL_fillStage_sir_1_; - &stagesL_drainStage_sir_1_; + &stagesM_fillStage_sid_1_; '> - &stageGroupsL_tapPropStop_sic_1_; + &stagesM_fillStage_sir_1_; + &stagesM_drainStage_sir_1_; '> - &stageGroupsL_tapPropStop_sid_1_; + &stageGroupsM_tapPropStop_sic_1_; '> - &stageGroupsL_upDown8weak_sir_1_; - &stageGroupsL_tapPropStop_sir_1_; + &stageGroupsM_tapPropStop_sid_1_; '> - &stageGroupsL_upDown8weak_sor_8_; + &stageGroupsM_upDown8weak_sir_1_; + &stageGroupsM_tapPropStop_sir_1_; '> - &stageGroupsL_properStopper_sic_1_; - &stagesL_tapStage_sic_1_; + &stageGroupsM_properStopper_sic_1_; + &stagesM_tapStage_sic_1_; '> - &stageGroupsL_properStopper_sid_1_; + &stageGroupsM_properStopper_sid_1_; &countersL_instructionCount_sid_1_; '> - &stageGroupsL_properStopper_sir_1_; - &stagesL_tapStage_sir_1_; -'> - &stagesL_weakStageUp_sir_1_; - &stagesL_weakStageUp_sir_1_; - &stagesL_weakStageUp_sir_1_; - &stagesL_weakStageUp_sir_1_; + &stageGroupsM_properStopper_sir_1_; + &stagesM_tapStage_sir_1_; '> - &stagesL_weakStageDn_sor_8_; - &stagesL_weakStageDn_sor_8_; - &stagesL_weakStageDn_sor_8_; - &stagesL_weakStageDn_sor_8_; + &stagesM_weakStage_sir_1_; + &stagesM_weakStage_sir_1_; + &stagesM_weakStage_sir_1_; + &stagesM_weakStage_sir_1_; + &stagesM_weakStage_sir_1_; + &stagesM_weakStage_sir_1_; + &stagesM_weakStage_sir_1_; + &stagesM_weakStage_sir_1_; '> - &gaspL_gaspDrain_sic_1_; + &scanM_scanEx3_sir_1_; '> - &gaspL_gaspDrain_sir_1_; + &scanM_scanEx2_sir_1_; '> - &gaspL_gaspFill_sic_1_; + &scanM_scanFx3_sic_1_; '> - ®istersJ_all1in52scan_sid_1_; + &scanM_scanEx2_sir_1_; '> - &gaspL_gaspFill_sir_1_; -'> - &gaspL_gaspTap_sic_1_; + &scanJ_scanEx1vertA_sir_1_; '> - &gaspL_gaspTap_sir_1_; + &scanM_scanFx3_sic_1_; '> - &gaspL_gaspWeakDn_sor_8_; + &gaspM_gaspFill_si_1_; + &latchGroupsK_latchWscM2_sin; + ®istersM_addr1in60Cx7scan_sin; + ®istersM_addr1in60Cx7scan_sin; + ®istersM_data1in60Cx18scan_sin; + &latchGroupsK_latchWscM2_sin; + ®istersM_data1in60Cx18scan_sin; '> - &gaspL_gaspWeakUp_sir_1_; + &scanM_scanEx2_sir_1_; '> - &scanJ_scanEx3hor_sir_1_; -'> - &scanJ_scanEx1vertA_sir_1_; - &scanJ_scanEx1vertA_sir_1_; '> - &scanJ_scanEx1vertA_sir_1_; '> - &scanJ_scanEx2vert_sir_1_; + &scanM_scanEx2_sir_1_; '> - &scanJ_scanEx3hor_sir_1_; - &scanJ_scanEx1vertA_sir_1_; -'> - &scanJ_scanEx1vertA_sir_1_; '> - &stepsM_epiStep_sir_1_; - &stepsM_reQstep_sir_1_; - &stepsM_splitStep9_sir_1_; - &stepsM_m2m1step_sir_1_; - &stepsM_shortODstep_sir_1_; + &scanM_scanEx2_sir_1_; '> - &scanJ_scanEx1vertA_sir_1_; + &scanM_scanEx3plain_sin; '> - &stepsM_threeStepU_sir_1_; - &stepsM_altStartStep_sir_1_; - &stepsM_threeStepU_sir_1_; - &stepsM_altEndStep_sir_1_; + &scanM_scanFx2_sic_1_; '> - &stepsM_shortStep_sir_1_; - &stepsM_shortStep_sir_1_; - &stepsM_shortStep_sir_1_; + &scanM_scanEx1_sir_1_; +'> + &scanJ_scanEx1vertA_sir_1_; '> ]> @@ -615,19 +501,18 @@ - &stageGroupsL_southFifo_sid_1_; - &stageGroupsL_northFifo_sid_1_; + &stageGroupsM_southFifo_sid_1_; + &stageGroupsM_northFifo_sid_1_; - &stageGroupsL_southFifo_sir_1_; - &dockK_dataPath_si_1_; + &stageGroupsM_southFifo_sir_1_; + &dockM_inputDock_sir_1_; &fifoL_tokenFIFO_sir_1_; - &stageGroupsL_northFifo_sir_1_; - &stageGroupsL_southFifo_sor_8_; + &stageGroupsM_northFifo_sir_1_; - &stageGroupsL_southFifo_sic_1_; - &stageGroupsL_northFifo_sic_1_; + &stageGroupsM_southFifo_sic_1_; + &stageGroupsM_northFifo_sic_1_; -- 1.7.10.4