From 103ebd81737fd7dc3ea6ef11372e394d5016defa Mon Sep 17 00:00:00 2001 From: Adam Megacz Date: Tue, 19 May 2009 20:19:29 +0000 Subject: [PATCH] fixes to break apart layout cells --- testCode/marina.bsh | 1 + testCode/marina.v | 62 ++++++++++++++++++++++++++++++++++++++++++++------- testCode/marina.xml | 19 ++++++++++------ 3 files changed, 67 insertions(+), 15 deletions(-) diff --git a/testCode/marina.bsh b/testCode/marina.bsh index fd37d8f..3371b9a 100644 --- a/testCode/marina.bsh +++ b/testCode/marina.bsh @@ -19,6 +19,7 @@ import com.sun.electric.plugins.menus.ScanChainXML; gen.addScanChainElement("scanM", "scanCellE", "RW", "-", "sin", "sout", "dIn[1](R)", "latch2in@0.dataBar(WI)"); gen.addScanChainElement("scanM", "scanCellF", "RW", "L", "sin", "sout", "dout[1](R)", "latch2in@1.dataBar(WI)"); + gen.addScanChainElement("scanM", "scanCellFtall", "RW", "L", "sin", "sout", "dout[1](R)", "latch2in@1.dataBar(WI)"); // Add all the pass through elements: these pass scan data through, // like inverters or buffers diff --git a/testCode/marina.v b/testCode/marina.v index 94c354a..b7ab6e3 100644 --- a/testCode/marina.v +++ b/testCode/marina.v @@ -1,7 +1,7 @@ /* Verilog for cell 'marinaOutDock{sch}' from library 'aMarinaM' */ /* Created on Mon Nov 17, 2008 08:47:24 */ /* Last revised on Sat May 02, 2009 06:16:53 */ -/* Written on Tue May 12, 2009 17:07:57 by Electric VLSI Design System, version 8.08k */ +/* Written on Sat May 16, 2009 16:19:19 by Electric VLSI Design System, version 8.08k */ module orangeTSMC090nm__wire(a); input a; @@ -783,7 +783,29 @@ module scanM__scanCellF(mc, p1p, p2p, rd, sin, wr, dout, sout); orangeTSMC090nm__wire90 wire90_0(.a(net_2)); endmodule /* scanM__scanCellF */ -module scanM__scanFx3(dout, dout_1, dout_2, sic, soc); +module scanM__scanCellFtall(mc, p1p, p2p, rd, sin, wr, dout, sout); + input mc; + input p1p; + input p2p; + input rd; + input sin; + input wr; + output [1:1] dout; + output sout; + + supply1 vdd; + supply0 gnd; + wire net_2; + + latchesK__latch1in10A latch1in_0(.hcl(p2p), .in({sin}), .out({net_2})); + latchesK__latch2in10Alo latch2in_0(.hcl_A_(p1p), .hcl_B_(rd), .inA({net_2}), + .inB(dout[1:1]), .out({sout})); + latchesK__latch2in10Alomc latch2in_1(.hcl(wr), .inA({sout}), .mc(mc), + .out(dout[1:1])); + orangeTSMC090nm__wire90 wire90_0(.a(net_2)); +endmodule /* scanM__scanCellFtall */ + +module scanM__scanFx3tallL(dout, dout_1, dout_2, sic, soc); output [1:1] dout; output [2:2] dout_1; output [3:3] dout_2; @@ -794,18 +816,18 @@ module scanM__scanFx3(dout, dout_1, dout_2, sic, soc); supply0 gnd; wire net_30, net_31; - scanM__scanCellF scanCell_4(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]), - .rd(sic[5]), .sin(sic[1]), .wr(sic[4]), .dout(dout[1:1]), - .sout(net_30)); scanM__scanCellF scanCell_5(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]), .rd(sic[5]), .sin(net_30), .wr(sic[4]), .dout(dout_1[2:2]), .sout(net_31)); scanM__scanCellF scanCell_6(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]), .rd(sic[5]), .sin(net_31), .wr(sic[4]), .dout(dout_2[3:3]), .sout(soc[1])); + scanM__scanCellFtall scanCell_7(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]), + .rd(sic[5]), .sin(sic[1]), .wr(sic[4]), .dout(dout[1:1]), + .sout(net_30)); orangeTSMC090nm__wire90 wire90_0(.a(net_30)); orangeTSMC090nm__wire90 wire90_1(.a(net_31)); -endmodule /* scanM__scanFx3 */ +endmodule /* scanM__scanFx3tallL */ module stagesM__drainStage(ain, ain_TT_, in, pred, aout, aout_TT_, out, succ, sic, sir, soc, sor); @@ -840,8 +862,8 @@ module stagesM__drainStage(ain, ain_TT_, in, pred, aout, aout_TT_, out, succ, .succ(succ), .take(net_5)); scanM__scanEx2 scanEx2v_1(.dIn({net_17[1], net_17[0]}), .sir(sir[1:9]), .sor(sor[1:1])); - scanM__scanFx3 scanFx3_0(.dout({go}), .dout_1({clear}), .dout_2({silent}), - .sic(sic[1:9]), .soc(soc[1:1])); + scanM__scanFx3tallL scanFx3t_1(.dout({go}), .dout_1({clear}), + .dout_2({silent}), .sic(sic[1:9]), .soc(soc[1:1])); wiresL__tranCap tc_1_(); wiresL__tranCap tc_2_(); endmodule /* stagesM__drainStage */ @@ -1193,6 +1215,30 @@ module scanM__scanAMPx5(si, so); scanM__scanAmp sa_5_(.in({si[5]}), .out({so[5]})); endmodule /* scanM__scanAMPx5 */ +module scanM__scanFx3(dout, dout_1, dout_2, sic, soc); + output [1:1] dout; + output [2:2] dout_1; + output [3:3] dout_2; + inout [1:9] sic; + inout [1:1] soc; + + supply1 vdd; + supply0 gnd; + wire net_30, net_31; + + scanM__scanCellF scanCell_4(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]), + .rd(sic[5]), .sin(sic[1]), .wr(sic[4]), .dout(dout[1:1]), + .sout(net_30)); + scanM__scanCellF scanCell_5(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]), + .rd(sic[5]), .sin(net_30), .wr(sic[4]), .dout(dout_1[2:2]), + .sout(net_31)); + scanM__scanCellF scanCell_6(.mc(sic[9]), .p1p(sic[3]), .p2p(sic[2]), + .rd(sic[5]), .sin(net_31), .wr(sic[4]), .dout(dout_2[3:3]), + .sout(soc[1])); + orangeTSMC090nm__wire90 wire90_0(.a(net_30)); + orangeTSMC090nm__wire90 wire90_1(.a(net_31)); +endmodule /* scanM__scanFx3 */ + module stagesM__fillStage(ain, ain_TT_, \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , \in[15] , \in[16] , \in[17] , \in[18] , \in[20] , diff --git a/testCode/marina.xml b/testCode/marina.xml index 5afa3af..7789e17 100644 --- a/testCode/marina.xml +++ b/testCode/marina.xml @@ -258,17 +258,17 @@ - - - + + + - - - + + + '> @@ -397,6 +397,11 @@ '> + + + +'> &stagesM_altStartDockStage_sir_1_; &stagesM_plainDockStage_sir_1_; @@ -489,7 +494,7 @@ &scanM_scanEx2_sir_1_; '> &scanM_scanFx3_sic_1_; + &scanM_scanFx3tallL_sic_1_; '> &scanM_scanEx2_sir_1_; -- 1.7.10.4