From 11aaca11a14ba1f6826fadb7bac37be21370d9bf Mon Sep 17 00:00:00 2001 From: rkao Date: Thu, 6 Nov 2008 18:34:35 +0000 Subject: [PATCH] test to count the outer loop counter --- .../sun/vlsi/chips/marina/test/IsolatedInDock.java | 6 ++ .../com/sun/vlsi/chips/marina/test/MarinaTest.java | 101 ++++++++++++++++++-- testCode/isolatedInDock.spi | 90 +++++++++++------ 3 files changed, 161 insertions(+), 36 deletions(-) diff --git a/testCode/com/sun/vlsi/chips/marina/test/IsolatedInDock.java b/testCode/com/sun/vlsi/chips/marina/test/IsolatedInDock.java index 056498d..89f1703 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/IsolatedInDock.java +++ b/testCode/com/sun/vlsi/chips/marina/test/IsolatedInDock.java @@ -92,6 +92,12 @@ public class IsolatedInDock implements Design { shiftReport(true, false); return (int) cc.getOutBits(REPORT_CHAIN+"."+ILC_PATH).bitReverse().not().toLong(); } + public boolean getIlcZero() { + return (getILC() & 0x40) != 0; + } + public int getIlcCount() { + return getILC() & 0x3f; + } public boolean getFlagA() { shiftReport(true, false); return cc.getOutBits(REPORT_CHAIN+"."+FLAGS_PATH).get(2); diff --git a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java index 7a9d3a3..562bc36 100644 --- a/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java +++ b/testCode/com/sun/vlsi/chips/marina/test/MarinaTest.java @@ -24,9 +24,9 @@ import com.sun.vlsi.chips.marina.test.MarinaUtils.CmdArgs.Mode; import edu.berkeley.fleet.api.Dock; import edu.berkeley.fleet.api.Instruction; -import edu.berkeley.fleet.api.Instruction.Set.SetDest; import edu.berkeley.fleet.api.Predicate; -import edu.berkeley.fleet.marina.MarinaFleet; +import edu.berkeley.fleet.api.Instruction.Set.SetDest; +import edu.berkeley.fleet.api.Instruction.Set.SetSource; /** * Tests for Marina @@ -39,6 +39,9 @@ public class MarinaTest { // COLUMN_LATENCY is a delay that is larger than the latency through an Infinity column private static final int COLUMN_LATENCY = 10; // nanoseconds + + // Nominal cycle time assuming 4 GHz throughput + private static final double CYCLE_TIME_NS = 0.250; //-------------------------------- types --------------------------------- @@ -393,11 +396,8 @@ public class MarinaTest { int olc = inDock.getOLC(); prln("OLC="+olc); - int ilc = inDock.getILC(); - int infinity = (ilc>>7) & 1; - int zero = (ilc>>6) & 1; - int count = ilc & 0x3f; - prln("ILC.infinity="+infinity+" ILC.zero="+zero+" ILC.count="+count); + prln(" ILC.zero="+inDock.getIlcZero()+ + " ILC.count="+inDock.getIlcCount()); boolean a = inDock.getFlagA(); prln("flagA="+a); @@ -422,6 +422,84 @@ public class MarinaTest { adjustIndent(-2); prln("End walkOneOLC"); } + private void walkOneILC(IsolatedInDock inDock) { + prln("Begin walkOneILC"); + adjustIndent(2); + for (int i=0; i<7; i++) { + // Mask off the "zero" bit position + int inIlc = 0x20 >> i; + prln("inIlc="+inIlc); + + inDock.instrIn.fill(new + Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.InnerLoopCounter, inIlc)); + + int outIlc = inDock.getIlcCount(); + fatal(outIlc!=inIlc, "bad ILC count: "+outIlc+" expected: "+outIlc); + + boolean inZero = inIlc==0; + boolean outZero = inDock.getIlcZero(); + fatal(outZero!=inZero, "bad ILC zero: "+outZero); + } + adjustIndent(-2); + prln("End walkOneILC"); + } + private void countIlc(IsolatedInDock inDock) { + final int maxIlc = 63; + prln("Begin countIlc"); + adjustIndent(2); + + inDock.instrIn.fill(new + Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.InnerLoopCounter, maxIlc)); + + int ilc = inDock.getIlcCount(); + fatal(ilc!=maxIlc, "bad ILC count: "+ilc+" expected: "+maxIlc); + + // execute a move instruction that does nothing except decrement the ILC to zero + inDock.instrIn.fill( + new Instruction.Move(DOCK, + false, /* requeueing */ + Predicate.IgnoreOLC, /* predicate */ + false, /* torpedoable */ + null, /* path */ + false, /* tokenIn */ + false, /* dataIn */ + false, /* latchData */ + false, /* latchPath */ + false, /* dataOut */ + false /* tokenOut */ + )); + + // wait for ILC to count from 63 to 0 + model.waitNS(64 * CYCLE_TIME_NS); + + ilc = inDock.getIlcCount(); + fatal(ilc!=0, "bad ILC count: "+ilc+" expected: "+0); + + adjustIndent(-2); + prln("End countIlc"); + } + // Note: countOlc takes 44 minutes to run on nanosim + private void countOlc(IsolatedInDock inDock) { + final int maxOlc = 63; + prln("Begin countOlc"); + adjustIndent(2); + + inDock.instrIn.fill(new + Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, maxOlc)); + for (int i=maxOlc; i>=0; i--) { + prln("OLC should be: "+i); + int olc = inDock.getOLC(); + fatal(olc!=i, "bad OLC: "+olc+" expected: "+i); + inDock.instrIn.fill(new + Instruction.Set(DOCK,false,Predicate.IgnoreOLC,SetDest.OuterLoopCounter, SetSource.Decrement)); + } + + adjustIndent(-2); + prln("End countOlc"); + } + private void testFlagAB(IsolatedInDock inDock) { + + } private void doOneTest(int testNum) { prln("MarinaTest: performing test: "+testNum); design.masterClear(tester); @@ -433,6 +511,15 @@ public class MarinaTest { case 3: sendToken((IsolatedInDock)design); break; case 4: getCtrsFlags((IsolatedInDock)design); break; case 5: walkOneOLC((IsolatedInDock)design); break; + + // Russell's tests begin with 1000 + case 1000: walkOneILC((IsolatedInDock)design); break; + case 1001: countIlc((IsolatedInDock)design); break; + case 1002: countOlc((IsolatedInDock)design); break; + + // Bill's tests begin with 2000 + case 2000: break; + default: fatal(true, "Test number: "+testNum+" doesn't exist."); break; diff --git a/testCode/isolatedInDock.spi b/testCode/isolatedInDock.spi index 27fbb4c..4d63bf8 100644 --- a/testCode/isolatedInDock.spi +++ b/testCode/isolatedInDock.spi @@ -1,7 +1,7 @@ *** SPICE deck for cell isolatedInDock{sch} from library marina *** Created on Fri Sep 05, 2008 15:05:59 *** Last revised on Tue Nov 04, 2008 12:48:55 -*** Written on Wed Nov 05, 2008 10:17:53 by Electric VLSI Design System, +*** Written on Thu Nov 06, 2008 07:34:41 by Electric VLSI Design System, *version 8.08k *** Layout tech: cmos90, foundry TSMC *** UC SPICE *** , MIN_RESIST 50.0, MIN_CAPAC 0.04FF @@ -8751,36 +8751,68 @@ XtriInv@1 s[F] s[T] inB[1] out[1] triInv-X_10 .ENDS mux10 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1400_9-R_34_667m a b -Ccap@0 gnd net@14 5.137f -Ccap@1 gnd net@8 5.137f -Ccap@2 gnd net@11 5.137f -Rres@0 net@14 a 8.094 -Rres@1 net@11 net@14 16.188 -Rres@2 b net@8 8.094 -Rres@3 net@8 net@11 16.188 -.ENDS wire-C_0_011f-1400_9-R_34_667m +.SUBCKT wire-C_0_011f-2740_3-R_34_667m a b +Ccap@0 gnd net@14 10.048f +Ccap@1 gnd net@8 10.048f +Ccap@2 gnd net@11 10.048f +Rres@0 net@14 a 15.833 +Rres@1 net@11 net@14 31.666 +Rres@2 b net@8 15.833 +Rres@3 net@8 net@11 31.666 +.ENDS wire-C_0_011f-2740_3-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1400_9-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1400_9-R_34_667m -.ENDS wire90-1400_9-layer_1-width_3 +.SUBCKT wire90-2740_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-2740_3-R_34_667m +.ENDS wire90-2740_3-layer_1-width_3 *** CELL: orangeTSMC090nm:wire{sch} -.SUBCKT wire-C_0_011f-1_401-R_34_667m a b -Ccap@0 gnd net@14 0.00514f -Ccap@1 gnd net@8 0.00514f -Ccap@2 gnd net@11 0.00514f -Rres@0 net@14 a 8.094m -Rres@1 net@11 net@14 16.188m -Rres@2 b net@8 8.094m -Rres@3 net@8 net@11 16.188m -.ENDS wire-C_0_011f-1_401-R_34_667m +.SUBCKT wire-C_0_011f-2463-R_34_667m a b +Ccap@0 gnd net@14 9.031f +Ccap@1 gnd net@8 9.031f +Ccap@2 gnd net@11 9.031f +Rres@0 net@14 a 14.231 +Rres@1 net@11 net@14 28.461 +Rres@2 b net@8 14.231 +Rres@3 net@8 net@11 28.461 +.ENDS wire-C_0_011f-2463-R_34_667m *** CELL: orangeTSMC090nm:wire90{sch} -.SUBCKT wire90-1_4009-layer_1-width_3 a b -Xwire@0 a b wire-C_0_011f-1_401-R_34_667m -.ENDS wire90-1_4009-layer_1-width_3 +.SUBCKT wire90-2463-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-2463-R_34_667m +.ENDS wire90-2463-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-406_3-R_34_667m a b +Ccap@0 gnd net@14 1.49f +Ccap@1 gnd net@8 1.49f +Ccap@2 gnd net@11 1.49f +Rres@0 net@14 a 2.348 +Rres@1 net@11 net@14 4.695 +Rres@2 b net@8 2.348 +Rres@3 net@8 net@11 4.695 +.ENDS wire-C_0_011f-406_3-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-406_3-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-406_3-R_34_667m +.ENDS wire90-406_3-layer_1-width_3 + +*** CELL: orangeTSMC090nm:wire{sch} +.SUBCKT wire-C_0_011f-381_8-R_34_667m a b +Ccap@0 gnd net@14 1.4f +Ccap@1 gnd net@8 1.4f +Ccap@2 gnd net@11 1.4f +Rres@0 net@14 a 2.206 +Rres@1 net@11 net@14 4.412 +Rres@2 b net@8 2.206 +Rres@3 net@8 net@11 4.412 +.ENDS wire-C_0_011f-381_8-R_34_667m + +*** CELL: orangeTSMC090nm:wire90{sch} +.SUBCKT wire90-381_8-layer_1-width_3 a b +Xwire@0 a b wire-C_0_011f-381_8-R_34_667m +.ENDS wire90-381_8-layer_1-width_3 *** CELL: loopCountL:inMux{sch} .SUBCKT inMux inA[1] inA[2] inA[3] inA[4] inA[5] inA[6] inB[1] inB[2] inB[3] @@ -8798,10 +8830,10 @@ Xmux[8] gnd inB[8] out[8] s[F] s[T] mux10 Xnand3@1 out[1] out[2] out[5] net@25 nand3-X_6_667 Xnand3@2 out[3] out[4] out[6] net@24 nand3-X_6_667 Xnor2n_sy@0 net@18 net@20 out[7] nor2n_sy-X_10 -Xwire90@0 net@10 s[F] wire90-1400_9-layer_1-width_3 -Xwire90@1 net@12 s[T] wire90-1400_9-layer_1-width_3 -Xwire90@2 net@24 net@20 wire90-1_4009-layer_1-width_3 -Xwire90@3 net@18 net@25 wire90-1_4009-layer_1-width_3 +Xwire90@0 net@10 s[F] wire90-2740_3-layer_1-width_3 +Xwire90@1 net@12 s[T] wire90-2463-layer_1-width_3 +Xwire90@2 net@24 net@20 wire90-406_3-layer_1-width_3 +Xwire90@3 net@18 net@25 wire90-381_8-layer_1-width_3 .ENDS inMux *** CELL: orangeTSMC090nm:wire{sch} -- 1.7.10.4