From 1a56fc08ec179e03f09260c431a9627cdcb5ca46 Mon Sep 17 00:00:00 2001 From: adam Date: Sat, 26 Jan 2008 19:14:36 +0100 Subject: [PATCH] updates for ml410 board --- Makefile | 13 +- src/edu/berkeley/fleet/fpga/Client.java | 2 +- src/edu/berkeley/fleet/fpga/Server.java | 22 +- src/edu/berkeley/fleet/fpga/async_fifo_8_8_128.edn | 402 ----------- src/edu/berkeley/fleet/fpga/async_fifo_8_8_128.v | 155 ----- ...sync_fifo_8_8_128_fifo_generator_v2_2_xst_1.ngc | 3 - ...fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst.edn | 576 ---------------- src/edu/berkeley/fleet/fpga/main.ucf | 721 +++++++++++++++++++- src/edu/berkeley/fleet/fpga/main.ut | 48 +- src/edu/berkeley/fleet/fpga/main.v | 585 ++++------------ src/edu/berkeley/fleet/fpga/main.xst | 2 +- src/edu/berkeley/fleet/fpga/sasc_brg.v | 163 +++++ src/edu/berkeley/fleet/fpga/sasc_fifo4.v | 139 ++++ src/edu/berkeley/fleet/fpga/sasc_top.v | 316 +++++++++ src/edu/berkeley/fleet/fpga/timescale.v | 1 + 15 files changed, 1481 insertions(+), 1667 deletions(-) delete mode 100644 src/edu/berkeley/fleet/fpga/async_fifo_8_8_128.edn delete mode 100644 src/edu/berkeley/fleet/fpga/async_fifo_8_8_128.v delete mode 100644 src/edu/berkeley/fleet/fpga/async_fifo_8_8_128_fifo_generator_v2_2_xst_1.ngc delete mode 100644 src/edu/berkeley/fleet/fpga/async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst.edn create mode 100644 src/edu/berkeley/fleet/fpga/sasc_brg.v create mode 100644 src/edu/berkeley/fleet/fpga/sasc_fifo4.v create mode 100644 src/edu/berkeley/fleet/fpga/sasc_top.v create mode 100644 src/edu/berkeley/fleet/fpga/timescale.v diff --git a/Makefile b/Makefile index df5384b..d0f496f 100644 --- a/Makefile +++ b/Makefile @@ -49,6 +49,8 @@ xilinx += XILINX=$(XILINX) xilinx += PATH=$$PATH:$(XILINX)/bin/lin xilinx += $(XILINX)/bin/lin/ +device = xc4vfx60-ff1152 + remote_run = skill a.out; remote_run += user_unprogram 1; remote_run += user_program 1 main.bit; @@ -63,9 +65,12 @@ verilog_files += $(shell find src -name \*.inc) runfpga: fleet.jar $(java) -jar fleet.jar target=fpga run +program: upload + ssh root@goliath.megacz.com 'cd /afs/megacz.com/work/ml410/; ./program.sh ./main.bit' + upload: fleet.jar build/fpga/main.bit mkdir -p build - rsync -zare ssh --progress --verbose build/fpga/main.bit root@bee441.megacz.com:/var/slipway/megacz.bit + rsync -zare ssh --progress --verbose build/fpga/main.bit root@goliath.megacz.com:/afs/megacz.com/work/ml410/ uploadtest: make upload @@ -90,15 +95,15 @@ build/fpga/main.bit: build/fpga/fabric.v $(verilog_files) scp ${host}:${remote_dir}/build/fpga/main.bit build/fpga/ synth: - cd build/fpga; ln -sf ../src/edu/berkeley/fleet/fpga/* . + cd build/fpga; ln -sf ../../src/edu/berkeley/fleet/fpga/* . cd build/fpga; echo work > main.lso cd build/fpga; for A in *.v; do echo verilog work \""$$A"\"; done > main.prj cd build/fpga; mkdir -p tmp cd build/fpga; mkdir -p xst rm -rf build/fpga/_ngo $(xilinx)xst -intstyle xflow -ifn main.xst -ofn main.syr < main.xst - $(xilinx)ngdbuild -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p xc2vp70-ff1704-6 main.ngc main.ngd - $(xilinx)map -intstyle xflow -p xc2vp70-ff1704-6 -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf + $(xilinx)ngdbuild -aul -intstyle xflow -dd _ngo -nt timestamp -uc main.ucf -p $(device) main.ngc main.ngd + $(xilinx)map -intstyle xflow -p $(device) -cm speed -l -pr b -k 4 -c 100 -tx off -o main_map.ncd main.ngd main.pcf $(xilinx)par -w -intstyle xflow -pl std -ol std -t 99 main_map.ncd main.ncd main.pcf $(xilinx)bitgen -intstyle xflow -d -f main.ut main.ncd # $(xilinx)trce -intstyle xflow -e 3 -l 3 -s 6 -xml main main.ncd -o main.twr main.pcf diff --git a/src/edu/berkeley/fleet/fpga/Client.java b/src/edu/berkeley/fleet/fpga/Client.java index a4257ee..0ff6da1 100644 --- a/src/edu/berkeley/fleet/fpga/Client.java +++ b/src/edu/berkeley/fleet/fpga/Client.java @@ -36,7 +36,7 @@ public class Client extends FleetProcess { } public Client(String bitfile, byte[] program) throws IOException { - s = new Socket(InetAddress.getByName("bee441.megacz.com"), 3133); + s = new Socket(InetAddress.getByName("goliath.megacz.com"), 3133); OutputStream os = s.getOutputStream(); PrintWriter pw = new PrintWriter(new OutputStreamWriter(os)); pw.print(Server.pass_string+" "+bitfile+"\n"); diff --git a/src/edu/berkeley/fleet/fpga/Server.java b/src/edu/berkeley/fleet/fpga/Server.java index 417df5f..dfc8b22 100644 --- a/src/edu/berkeley/fleet/fpga/Server.java +++ b/src/edu/berkeley/fleet/fpga/Server.java @@ -9,10 +9,13 @@ public class Server { public static ServerSocket ss; public static void main(String[] args) throws Exception { ss = new ServerSocket(3133); + /* new Listener(3).start(); new Listener(4).start(); new Listener(1).start(); new Listener(2).start(); + */ + new Listener(0).start(); } public static String pass_string = "password=security_is_for_wimps "; @@ -58,12 +61,19 @@ public class Server { if (!sb.toString().startsWith(pass_string)) return; String file = sb.toString().substring(pass_string.length()).trim(); - System.err.println("unprogramming..."); - int ret = Runtime.getRuntime().exec(new String[] { "/usr/bin/user_unprogram", ""+devnum }).waitFor(); + System.err.println("programming..."); + Process proc = Runtime.getRuntime().exec(new String[] { "/afs/megacz.com/work/ml410/program.sh", "/afs/megacz.com/work/ml410/main.bit" }); + BufferedReader br = new BufferedReader(new InputStreamReader(proc.getInputStream())); + String s = null; + while((s = br.readLine()) != null) { + System.err.println(" " + s); + } + int ret = proc.waitFor(); if (ret != 0) { System.err.println("programming error: " + ret); return; } + /* System.err.println("programming..."); ret = Runtime.getRuntime().exec(new String[] { "/usr/bin/user_program", ""+devnum, "/var/slipway/"+file }).waitFor(); @@ -71,11 +81,12 @@ public class Server { System.err.println("programming error: " + ret); return; } + */ System.err.println("done programming."); try { Thread.sleep(2000); } catch(Exception e) { } final OutputStream os = socket.getOutputStream(); System.err.println("sending instructions..."); - raf = new RandomAccessFile("/dev/selectmap"+devnum, "rw"); + raf = new RandomAccessFile("/dev/ttyS"+devnum, "rw"); final RandomAccessFile raf2 = raf; @@ -95,9 +106,9 @@ public class Server { } finally { if (raf2 != null) { System.err.println("closing..."); + closed = true; try { raf2.close(); } catch (Throwable t) { t.printStackTrace(); } try { fos.close(); } catch (Throwable t) { t.printStackTrace(); } - closed = true; } } } @@ -110,7 +121,7 @@ public class Server { int val = 0; for(int i=0; i<6; i++) { int k = 0; - while(fis.available()==0) { + while(!closed && fis.available()==0) { if (closed) return; k++; if (k >= 100) { @@ -119,6 +130,7 @@ public class Server { } Thread.sleep(10); } + if (closed) return; val = fis.read(); if (val==-1) break; os.write((byte)val); diff --git a/src/edu/berkeley/fleet/fpga/async_fifo_8_8_128.edn b/src/edu/berkeley/fleet/fpga/async_fifo_8_8_128.edn deleted file mode 100644 index 5562d7c..0000000 --- a/src/edu/berkeley/fleet/fpga/async_fifo_8_8_128.edn +++ /dev/null @@ -1,402 +0,0 @@ -(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) -(status (written (timeStamp 2006 2 18 19 6 14) - (author "Xilinx, Inc.") - (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 7.1.04i; Cores Update # 3")))) - (comment " - This file is owned and controlled by Xilinx and must be used - solely for design, simulation, implementation and creation of - design files limited to Xilinx devices or technologies. Use - with non-Xilinx devices or technologies is expressly prohibited - and immediately terminates your license. - - XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS' - SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR - XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION - AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION - OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS - IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, - AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE - FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY - WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE - IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR - REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF - INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - FOR A PARTICULAR PURPOSE. - - Xilinx products are not intended for use in life support - appliances, devices, or systems. Use in such applications are - expressly prohibited. - - (c) Copyright 1995-2005 Xilinx, Inc. - All rights reserved. - - ") - (comment "Core parameters: ") - (comment "c_wr_response_latency = 1 ") - (comment "c_has_rd_data_count = 1 ") - (comment "c_din_width = 8 ") - (comment "c_has_wr_data_count = 1 ") - (comment "InstanceName = async_fifo_8_8_128 ") - (comment "c_implementation_type = 2 ") - (comment "c_family = virtex2p ") - (comment "c_has_wr_rst = 0 ") - (comment "c_underflow_low = 0 ") - (comment "c_has_meminit_file = 0 ") - (comment "c_has_overflow = 0 ") - (comment "c_preload_latency = 0 ") - (comment "c_dout_width = 8 ") - (comment "c_rd_depth = 128 ") - (comment "c_default_value = BlankString ") - (comment "c_mif_file_name = BlankString ") - (comment "c_has_underflow = 0 ") - (comment "c_has_rd_rst = 0 ") - (comment "c_has_almost_full = 0 ") - (comment "c_has_rst = 1 ") - (comment "c_data_count_width = 2 ") - (comment "c_has_wr_ack = 0 ") - (comment "c_wr_ack_low = 0 ") - (comment "c_common_clock = 0 ") - (comment "c_rd_pntr_width = 7 ") - (comment "c_has_almost_empty = 0 ") - (comment "c_rd_data_count_width = 8 ") - (comment "c_enable_rlocs = 0 ") - (comment "c_wr_pntr_width = 7 ") - (comment "c_overflow_low = 0 ") - (comment "c_prog_empty_type = 0 ") - (comment "c_optimization_mode = 0 ") - (comment "c_wr_data_count_width = 8 ") - (comment "c_preload_regs = 1 ") - (comment "c_dout_rst_val = 0 ") - (comment "c_has_data_count = 0 ") - (comment "c_prog_full_thresh_negate_val = 96 ") - (comment "c_wr_depth = 128 ") - (comment "c_prog_empty_thresh_negate_val = 32 ") - (comment "c_prog_empty_thresh_assert_val = 32 ") - (comment "c_has_valid = 0 ") - (comment "c_init_wr_pntr_val = 0 ") - (comment "c_prog_full_thresh_assert_val = 96 ") - (comment "c_use_fifo16_flags = 0 ") - (comment "c_has_backup = 0 ") - (comment "c_valid_low = 0 ") - (comment "c_prim_fifo_type = 512 ") - (comment "c_count_type = 0 ") - (comment "c_prog_full_type = 0 ") - (comment "c_memory_type = 1 ") - (external xilinxun (edifLevel 0) - (technology (numberDefinition)) - (cell VCC (cellType GENERIC) - (view view_1 (viewType NETLIST) - (interface - (port P (direction OUTPUT)) - ) - ) - ) - (cell GND (cellType GENERIC) - (view view_1 (viewType NETLIST) - (interface - (port G (direction OUTPUT)) - ) - ) - ) - ) - (external async_fifo_8_8_128_fifo_generator_v2_2_xst_1_lib (edifLevel 0) - (technology (numberDefinition)) - (cell async_fifo_8_8_128_fifo_generator_v2_2_xst_1 (cellType GENERIC) - (view view_1 (viewType NETLIST) - (interface - (port clk (direction INPUT)) - (port backup (direction INPUT)) - (port backup_marker (direction INPUT)) - (port ( array ( rename din "din<7:0>") 8 ) (direction INPUT)) - (port ( array ( rename prog_empty_thresh "prog_empty_thresh<6:0>") 7 ) (direction INPUT)) - (port ( array ( rename prog_empty_thresh_assert "prog_empty_thresh_assert<6:0>") 7 ) (direction INPUT)) - (port ( array ( rename prog_empty_thresh_negate "prog_empty_thresh_negate<6:0>") 7 ) (direction INPUT)) - (port ( array ( rename prog_full_thresh "prog_full_thresh<6:0>") 7 ) (direction INPUT)) - (port ( array ( rename prog_full_thresh_assert "prog_full_thresh_assert<6:0>") 7 ) (direction INPUT)) - (port ( array ( rename prog_full_thresh_negate "prog_full_thresh_negate<6:0>") 7 ) (direction INPUT)) - (port rd_clk (direction INPUT)) - (port rd_en (direction INPUT)) - (port rd_rst (direction INPUT)) - (port rst (direction INPUT)) - (port wr_clk (direction INPUT)) - (port wr_en (direction INPUT)) - (port wr_rst (direction INPUT)) - (port almost_empty (direction OUTPUT)) - (port almost_full (direction OUTPUT)) - (port ( array ( rename data_count "data_count<1:0>") 2 ) (direction OUTPUT)) - (port ( array ( rename dout "dout<7:0>") 8 ) (direction OUTPUT)) - (port empty (direction OUTPUT)) - (port full (direction OUTPUT)) - (port overflow (direction OUTPUT)) - (port prog_empty (direction OUTPUT)) - (port prog_full (direction OUTPUT)) - (port valid (direction OUTPUT)) - (port ( array ( rename rd_data_count "rd_data_count<7:0>") 8 ) (direction OUTPUT)) - (port underflow (direction OUTPUT)) - (port wr_ack (direction OUTPUT)) - (port ( array ( rename wr_data_count "wr_data_count<7:0>") 8 ) (direction OUTPUT)) - ) - ) - ) - ) -(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time)))) -(cell async_fifo_8_8_128 - (cellType GENERIC) (view view_1 (viewType NETLIST) - (interface - (port ( array ( rename din "din<7:0>") 8 ) (direction INPUT)) - (port ( rename rd_clk "rd_clk") (direction INPUT)) - (port ( rename rd_en "rd_en") (direction INPUT)) - (port ( rename rst "rst") (direction INPUT)) - (port ( rename wr_clk "wr_clk") (direction INPUT)) - (port ( rename wr_en "wr_en") (direction INPUT)) - (port ( array ( rename dout "dout<7:0>") 8 ) (direction OUTPUT)) - (port ( rename empty "empty") (direction OUTPUT)) - (port ( rename full "full") (direction OUTPUT)) - (port ( array ( rename rd_data_count "rd_data_count<7:0>") 8 ) (direction OUTPUT)) - (port ( array ( rename wr_data_count "wr_data_count<7:0>") 8 ) (direction OUTPUT)) - ) - (contents - (instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun)))) - (instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun)))) - (instance BU2 - (viewRef view_1 (cellRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1 (libraryRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_lib))) - ) - (net (rename N5 "din<7>") - (joined - (portRef (member din 0)) - (portRef (member din 0) (instanceRef BU2)) - ) - ) - (net (rename N6 "din<6>") - (joined - (portRef (member din 1)) - (portRef (member din 1) (instanceRef BU2)) - ) - ) - (net (rename N7 "din<5>") - (joined - (portRef (member din 2)) - (portRef (member din 2) (instanceRef BU2)) - ) - ) - (net (rename N8 "din<4>") - (joined - (portRef (member din 3)) - (portRef (member din 3) (instanceRef BU2)) - ) - ) - (net (rename N9 "din<3>") - (joined - (portRef (member din 4)) - (portRef (member din 4) (instanceRef BU2)) - ) - ) - (net (rename N10 "din<2>") - (joined - (portRef (member din 5)) - (portRef (member din 5) (instanceRef BU2)) - ) - ) - (net (rename N11 "din<1>") - (joined - (portRef (member din 6)) - (portRef (member din 6) (instanceRef BU2)) - ) - ) - (net (rename N12 "din<0>") - (joined - (portRef (member din 7)) - (portRef (member din 7) (instanceRef BU2)) - ) - ) - (net (rename N55 "rd_clk") - (joined - (portRef rd_clk) - (portRef rd_clk (instanceRef BU2)) - ) - ) - (net (rename N56 "rd_en") - (joined - (portRef rd_en) - (portRef rd_en (instanceRef BU2)) - ) - ) - (net (rename N58 "rst") - (joined - (portRef rst) - (portRef rst (instanceRef BU2)) - ) - ) - (net (rename N59 "wr_clk") - (joined - (portRef wr_clk) - (portRef wr_clk (instanceRef BU2)) - ) - ) - (net (rename N60 "wr_en") - (joined - (portRef wr_en) - (portRef wr_en (instanceRef BU2)) - ) - ) - (net (rename N66 "dout<7>") - (joined - (portRef (member dout 0)) - (portRef (member dout 0) (instanceRef BU2)) - ) - ) - (net (rename N67 "dout<6>") - (joined - (portRef (member dout 1)) - (portRef (member dout 1) (instanceRef BU2)) - ) - ) - (net (rename N68 "dout<5>") - (joined - (portRef (member dout 2)) - (portRef (member dout 2) (instanceRef BU2)) - ) - ) - (net (rename N69 "dout<4>") - (joined - (portRef (member dout 3)) - (portRef (member dout 3) (instanceRef BU2)) - ) - ) - (net (rename N70 "dout<3>") - (joined - (portRef (member dout 4)) - (portRef (member dout 4) (instanceRef BU2)) - ) - ) - (net (rename N71 "dout<2>") - (joined - (portRef (member dout 5)) - (portRef (member dout 5) (instanceRef BU2)) - ) - ) - (net (rename N72 "dout<1>") - (joined - (portRef (member dout 6)) - (portRef (member dout 6) (instanceRef BU2)) - ) - ) - (net (rename N73 "dout<0>") - (joined - (portRef (member dout 7)) - (portRef (member dout 7) (instanceRef BU2)) - ) - ) - (net (rename N74 "empty") - (joined - (portRef empty) - (portRef empty (instanceRef BU2)) - ) - ) - (net (rename N75 "full") - (joined - (portRef full) - (portRef full (instanceRef BU2)) - ) - ) - (net (rename N80 "rd_data_count<7>") - (joined - (portRef (member rd_data_count 0)) - (portRef (member rd_data_count 0) (instanceRef BU2)) - ) - ) - (net (rename N81 "rd_data_count<6>") - (joined - (portRef (member rd_data_count 1)) - (portRef (member rd_data_count 1) (instanceRef BU2)) - ) - ) - (net (rename N82 "rd_data_count<5>") - (joined - (portRef (member rd_data_count 2)) - (portRef (member rd_data_count 2) (instanceRef BU2)) - ) - ) - (net (rename N83 "rd_data_count<4>") - (joined - (portRef (member rd_data_count 3)) - (portRef (member rd_data_count 3) (instanceRef BU2)) - ) - ) - (net (rename N84 "rd_data_count<3>") - (joined - (portRef (member rd_data_count 4)) - (portRef (member rd_data_count 4) (instanceRef BU2)) - ) - ) - (net (rename N85 "rd_data_count<2>") - (joined - (portRef (member rd_data_count 5)) - (portRef (member rd_data_count 5) (instanceRef BU2)) - ) - ) - (net (rename N86 "rd_data_count<1>") - (joined - (portRef (member rd_data_count 6)) - (portRef (member rd_data_count 6) (instanceRef BU2)) - ) - ) - (net (rename N87 "rd_data_count<0>") - (joined - (portRef (member rd_data_count 7)) - (portRef (member rd_data_count 7) (instanceRef BU2)) - ) - ) - (net (rename N90 "wr_data_count<7>") - (joined - (portRef (member wr_data_count 0)) - (portRef (member wr_data_count 0) (instanceRef BU2)) - ) - ) - (net (rename N91 "wr_data_count<6>") - (joined - (portRef (member wr_data_count 1)) - (portRef (member wr_data_count 1) (instanceRef BU2)) - ) - ) - (net (rename N92 "wr_data_count<5>") - (joined - (portRef (member wr_data_count 2)) - (portRef (member wr_data_count 2) (instanceRef BU2)) - ) - ) - (net (rename N93 "wr_data_count<4>") - (joined - (portRef (member wr_data_count 3)) - (portRef (member wr_data_count 3) (instanceRef BU2)) - ) - ) - (net (rename N94 "wr_data_count<3>") - (joined - (portRef (member wr_data_count 4)) - (portRef (member wr_data_count 4) (instanceRef BU2)) - ) - ) - (net (rename N95 "wr_data_count<2>") - (joined - (portRef (member wr_data_count 5)) - (portRef (member wr_data_count 5) (instanceRef BU2)) - ) - ) - (net (rename N96 "wr_data_count<1>") - (joined - (portRef (member wr_data_count 6)) - (portRef (member wr_data_count 6) (instanceRef BU2)) - ) - ) - (net (rename N97 "wr_data_count<0>") - (joined - (portRef (member wr_data_count 7)) - (portRef (member wr_data_count 7) (instanceRef BU2)) - ) - ) -)))) -(design async_fifo_8_8_128 (cellRef async_fifo_8_8_128 (libraryRef test_lib)) - (property X_CORE_INFO (string "fifo_generator_v2_2, Coregen 7.1.04i_ip3")) - (property PART (string "xc2vp70-ff1704-7") (owner "Xilinx"))) -) diff --git a/src/edu/berkeley/fleet/fpga/async_fifo_8_8_128.v b/src/edu/berkeley/fleet/fpga/async_fifo_8_8_128.v deleted file mode 100644 index ce27aa2..0000000 --- a/src/edu/berkeley/fleet/fpga/async_fifo_8_8_128.v +++ /dev/null @@ -1,155 +0,0 @@ -/******************************************************************************* -* This file is owned and controlled by Xilinx and must be used * -* solely for design, simulation, implementation and creation of * -* design files limited to Xilinx devices or technologies. Use * -* with non-Xilinx devices or technologies is expressly prohibited * -* and immediately terminates your license. * -* * -* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * -* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * -* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * -* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * -* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * -* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * -* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * -* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * -* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * -* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * -* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * -* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * -* FOR A PARTICULAR PURPOSE. * -* * -* Xilinx products are not intended for use in life support * -* appliances, devices, or systems. Use in such applications are * -* expressly prohibited. * -* * -* (c) Copyright 1995-2005 Xilinx, Inc. * -* All rights reserved. * -*******************************************************************************/ -// The synopsys directives "translate_off/translate_on" specified below are -// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis -// tools. Ensure they are correct for your synthesis tool(s). - -// You must compile the wrapper file async_fifo_8_8_128.v when simulating -// the core, async_fifo_8_8_128. When compiling the wrapper file, be sure to -// reference the XilinxCoreLib Verilog simulation library. For detailed -// instructions, please refer to the "CORE Generator Help". - -`timescale 1ns/1ps - -module async_fifo_8_8_128( - din, - rd_clk, - rd_en, - rst, - wr_clk, - wr_en, - dout, - empty, - full, - rd_data_count, - wr_data_count); - - -input [7 : 0] din; -input rd_clk; -input rd_en; -input rst; -input wr_clk; -input wr_en; -output [7 : 0] dout; -output empty; -output full; -output [7 : 0] rd_data_count; -output [7 : 0] wr_data_count; - -// synopsys translate_off - - FIFO_GENERATOR_V2_2 #( - 0, // c_common_clock - 0, // c_count_type - 2, // c_data_count_width - "BlankString", // c_default_value - 8, // c_din_width - "0", // c_dout_rst_val - 8, // c_dout_width - 0, // c_enable_rlocs - "virtex2p", // c_family - 0, // c_has_almost_empty - 0, // c_has_almost_full - 0, // c_has_backup - 0, // c_has_data_count - 0, // c_has_meminit_file - 0, // c_has_overflow - 1, // c_has_rd_data_count - 0, // c_has_rd_rst - 1, // c_has_rst - 0, // c_has_underflow - 0, // c_has_valid - 0, // c_has_wr_ack - 1, // c_has_wr_data_count - 0, // c_has_wr_rst - 2, // c_implementation_type - 0, // c_init_wr_pntr_val - 1, // c_memory_type - "BlankString", // c_mif_file_name - 0, // c_optimization_mode - 0, // c_overflow_low - 0, // c_preload_latency - 1, // c_preload_regs - 512, // c_prim_fifo_type - 32, // c_prog_empty_thresh_assert_val - 32, // c_prog_empty_thresh_negate_val - 0, // c_prog_empty_type - 96, // c_prog_full_thresh_assert_val - 96, // c_prog_full_thresh_negate_val - 0, // c_prog_full_type - 8, // c_rd_data_count_width - 128, // c_rd_depth - 7, // c_rd_pntr_width - 0, // c_underflow_low - 0, // c_use_fifo16_flags - 0, // c_valid_low - 0, // c_wr_ack_low - 8, // c_wr_data_count_width - 128, // c_wr_depth - 7, // c_wr_pntr_width - 1) // c_wr_response_latency - inst ( - .DIN(din), - .RD_CLK(rd_clk), - .RD_EN(rd_en), - .RST(rst), - .WR_CLK(wr_clk), - .WR_EN(wr_en), - .DOUT(dout), - .EMPTY(empty), - .FULL(full), - .RD_DATA_COUNT(rd_data_count), - .WR_DATA_COUNT(wr_data_count), - .CLK(), - .BACKUP(), - .BACKUP_MARKER(), - .PROG_EMPTY_THRESH(), - .PROG_EMPTY_THRESH_ASSERT(), - .PROG_EMPTY_THRESH_NEGATE(), - .PROG_FULL_THRESH(), - .PROG_FULL_THRESH_ASSERT(), - .PROG_FULL_THRESH_NEGATE(), - .RD_RST(), - .WR_RST(), - .ALMOST_EMPTY(), - .ALMOST_FULL(), - .DATA_COUNT(), - .OVERFLOW(), - .PROG_EMPTY(), - .PROG_FULL(), - .VALID(), - .UNDERFLOW(), - .WR_ACK()); - - -// synopsys translate_on - -endmodule - diff --git a/src/edu/berkeley/fleet/fpga/async_fifo_8_8_128_fifo_generator_v2_2_xst_1.ngc b/src/edu/berkeley/fleet/fpga/async_fifo_8_8_128_fifo_generator_v2_2_xst_1.ngc deleted file mode 100644 index dc18c6b..0000000 --- a/src/edu/berkeley/fleet/fpga/async_fifo_8_8_128_fifo_generator_v2_2_xst_1.ngc +++ /dev/null @@ -1,3 +0,0 @@ -XILINX-XDB 0.1 STUB 0.1 ASCII -XILINX-XDM V1.4e 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(direction INPUT)) - (port (rename DIA_1_ "DIA<1>") (direction INPUT)) - (port (rename DIA_2_ "DIA<2>") (direction INPUT)) - (port (rename DIA_3_ "DIA<3>") (direction INPUT)) - (port (rename DIA_4_ "DIA<4>") (direction INPUT)) - (port (rename DIA_5_ "DIA<5>") (direction INPUT)) - (port (rename DIA_6_ "DIA<6>") (direction INPUT)) - (port (rename DIA_7_ "DIA<7>") (direction INPUT)) - (port (rename DOA_0_ "DOA<0>") (direction OUTPUT)) - (port (rename DOA_1_ "DOA<1>") (direction OUTPUT)) - (port (rename DOA_2_ "DOA<2>") (direction OUTPUT)) - (port (rename DOA_3_ "DOA<3>") (direction OUTPUT)) - (port (rename DOA_4_ "DOA<4>") (direction OUTPUT)) - (port (rename DOA_5_ "DOA<5>") (direction OUTPUT)) - (port (rename DOA_6_ "DOA<6>") (direction OUTPUT)) - (port (rename DOA_7_ "DOA<7>") (direction OUTPUT)) - (port (rename ADDRA_0_ "ADDRA<0>") (direction INPUT)) - (port (rename ADDRA_1_ "ADDRA<1>") (direction INPUT)) - (port (rename ADDRA_2_ "ADDRA<2>") (direction INPUT)) - (port (rename ADDRA_3_ "ADDRA<3>") (direction INPUT)) - (port (rename ADDRA_4_ "ADDRA<4>") (direction INPUT)) - (port (rename ADDRA_5_ "ADDRA<5>") (direction INPUT)) - (port (rename ADDRA_6_ "ADDRA<6>") (direction INPUT)) - (port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT)) - (port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT)) - (port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT)) - (port (rename ADDRA_10_ "ADDRA<10>") (direction INPUT)) - (port (rename DIPA_0_ "DIPA<0>") (direction INPUT)) - (port (rename DOPA_0_ "DOPA<0>") (direction OUTPUT)) - (port WEB (direction INPUT)) - (port ENB (direction INPUT)) - (port SSRB (direction INPUT)) - (port CLKB (direction INPUT)) - (port (rename DIB_0_ "DIB<0>") (direction INPUT)) - (port (rename DIB_1_ "DIB<1>") (direction INPUT)) - (port (rename DIB_2_ "DIB<2>") (direction INPUT)) - (port (rename DIB_3_ "DIB<3>") (direction INPUT)) - (port (rename DIB_4_ "DIB<4>") (direction INPUT)) - (port (rename DIB_5_ "DIB<5>") (direction INPUT)) - (port (rename DIB_6_ "DIB<6>") (direction INPUT)) - (port (rename DIB_7_ "DIB<7>") (direction INPUT)) - (port (rename DOB_0_ "DOB<0>") (direction OUTPUT)) - (port (rename DOB_1_ "DOB<1>") (direction OUTPUT)) - (port (rename DOB_2_ "DOB<2>") (direction OUTPUT)) - (port (rename DOB_3_ "DOB<3>") (direction OUTPUT)) - (port (rename DOB_4_ "DOB<4>") (direction OUTPUT)) - (port (rename DOB_5_ "DOB<5>") (direction OUTPUT)) - (port (rename DOB_6_ "DOB<6>") (direction OUTPUT)) - (port (rename DOB_7_ "DOB<7>") (direction OUTPUT)) - (port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT)) - (port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT)) - (port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT)) - (port (rename ADDRB_3_ "ADDRB<3>") (direction INPUT)) - (port (rename ADDRB_4_ "ADDRB<4>") (direction INPUT)) - (port (rename ADDRB_5_ "ADDRB<5>") (direction INPUT)) - (port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT)) - (port (rename ADDRB_7_ "ADDRB<7>") (direction INPUT)) - (port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT)) - (port (rename ADDRB_9_ "ADDRB<9>") (direction INPUT)) - (port (rename ADDRB_10_ "ADDRB<10>") (direction INPUT)) - (port (rename DIPB_0_ "DIPB<0>") (direction INPUT)) - (port (rename DOPB_0_ "DOPB<0>") (direction OUTPUT)) - ) - ) - ) - ) -(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time)))) -(cell async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst - (cellType GENERIC) (view view_1 (viewType NETLIST) - (interface - (port ( rename dina_7_ "dina<7>") (direction INPUT)) - (port ( rename dina_6_ "dina<6>") (direction INPUT)) - (port ( rename dina_5_ "dina<5>") (direction INPUT)) - (port ( rename dina_4_ "dina<4>") (direction INPUT)) - (port ( rename dina_3_ "dina<3>") (direction INPUT)) - (port ( rename dina_2_ "dina<2>") (direction INPUT)) - (port ( rename dina_1_ "dina<1>") (direction INPUT)) - (port ( rename dina_0_ "dina<0>") (direction INPUT)) - (port ( rename dinb_7_ "dinb<7>") (direction INPUT)) - (port ( rename dinb_6_ "dinb<6>") (direction INPUT)) - (port ( rename dinb_5_ "dinb<5>") (direction INPUT)) - (port ( rename dinb_4_ "dinb<4>") (direction INPUT)) - (port ( rename dinb_3_ "dinb<3>") (direction INPUT)) - (port ( rename dinb_2_ "dinb<2>") (direction INPUT)) - (port ( rename dinb_1_ "dinb<1>") (direction INPUT)) - (port ( rename dinb_0_ "dinb<0>") (direction INPUT)) - (port ( rename ena "ena") (direction INPUT)) - (port ( rename enb "enb") (direction INPUT)) - (port ( rename wea "wea") (direction INPUT)) - (port ( rename web "web") (direction INPUT)) - (port ( rename sinita "sinita") (direction INPUT)) - (port ( rename sinitb "sinitb") (direction INPUT)) - (port ( rename nda "nda") (direction INPUT)) - (port ( rename ndb "ndb") (direction INPUT)) - (port ( rename clka "clka") (direction INPUT)) - (port ( rename clkb "clkb") (direction INPUT)) - (port ( rename addra_6_ "addra<6>") (direction INPUT)) - (port ( rename addra_5_ "addra<5>") (direction INPUT)) - (port ( rename addra_4_ "addra<4>") (direction INPUT)) - (port ( rename addra_3_ "addra<3>") (direction INPUT)) - (port ( rename addra_2_ "addra<2>") (direction INPUT)) - (port ( rename addra_1_ "addra<1>") (direction INPUT)) - (port ( rename addra_0_ "addra<0>") (direction INPUT)) - (port ( rename addrb_6_ "addrb<6>") (direction INPUT)) - (port ( rename addrb_5_ "addrb<5>") (direction INPUT)) - (port ( rename addrb_4_ "addrb<4>") (direction INPUT)) - (port ( rename addrb_3_ "addrb<3>") (direction INPUT)) - (port ( rename addrb_2_ "addrb<2>") (direction INPUT)) - (port ( rename addrb_1_ "addrb<1>") (direction INPUT)) - (port ( rename addrb_0_ "addrb<0>") (direction INPUT)) - (port ( rename rdya "rdya") (direction OUTPUT)) - (port ( rename rdyb "rdyb") (direction OUTPUT)) - (port ( rename rfda "rfda") (direction OUTPUT)) - (port ( rename rfdb "rfdb") (direction OUTPUT)) - (port ( rename douta_7_ "douta<7>") (direction OUTPUT)) - (port ( rename douta_6_ "douta<6>") (direction OUTPUT)) - (port ( rename douta_5_ "douta<5>") (direction OUTPUT)) - (port ( rename douta_4_ "douta<4>") (direction OUTPUT)) - (port ( rename douta_3_ "douta<3>") (direction OUTPUT)) - (port ( rename douta_2_ "douta<2>") (direction OUTPUT)) - (port ( rename douta_1_ "douta<1>") (direction OUTPUT)) - (port ( rename douta_0_ "douta<0>") (direction OUTPUT)) - (port ( rename doutb_7_ "doutb<7>") (direction OUTPUT)) - (port ( rename doutb_6_ "doutb<6>") (direction OUTPUT)) - (port ( rename doutb_5_ "doutb<5>") (direction OUTPUT)) - (port ( rename doutb_4_ "doutb<4>") (direction OUTPUT)) - (port ( rename doutb_3_ "doutb<3>") (direction OUTPUT)) - (port ( rename doutb_2_ "doutb<2>") (direction OUTPUT)) - (port ( rename doutb_1_ "doutb<1>") (direction OUTPUT)) - (port ( rename doutb_0_ "doutb<0>") (direction OUTPUT)) - ) - (contents - (instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun)))) - (instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun)))) - (instance (rename async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8 "async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst/bm/mem/arch_v2/prim/3/b1/chk0/col/0/b2/mextd/arch_v2/c1/ram1/v2/d2048/by9/newSim8") - (viewRef view_1 (cellRef RAMB16_S9_S9 (libraryRef xilinxun))) - (property INIT_00 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_01 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_02 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_03 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_04 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_05 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_06 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_07 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_08 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_09 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_0A (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_0B (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_0C (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_0D (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_0E (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_0F (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_10 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_11 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_12 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_13 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_14 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_15 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_16 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_17 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_18 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_19 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_1A (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_1B (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_1C (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_1D (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_1E (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_1F (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_20 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_21 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_22 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_23 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_24 (string 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"0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_30 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_31 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_32 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_33 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_34 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_35 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_36 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_37 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_38 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_39 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INITP_00 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INITP_01 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INITP_02 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INITP_03 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INITP_04 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INITP_05 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INITP_06 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property INITP_07 (string "0000000000000000000000000000000000000000000000000000000000000000")) - (property WRITE_MODE_A (string "WRITE_FIRST")) - (property INIT_A (string "000")) - (property SRVAL_A (string "000")) - (property WRITE_MODE_B (string "WRITE_FIRST")) - (property INIT_B (string "000")) - (property SRVAL_B (string "000")) - ) - (net (rename N0 "Gnd") - (joined - (portRef G (instanceRef GND)) - (portRef WEB (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef ADDRA_7_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef ADDRA_8_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef ADDRA_9_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef ADDRA_10_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef DIPA_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef ADDRB_7_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef ADDRB_8_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef ADDRB_9_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef ADDRB_10_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef DIB_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef DIB_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef DIB_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef DIB_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef DIB_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef DIB_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef DIB_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef DIB_7_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - (portRef DIPB_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N1 "Vcc") - (joined - (portRef P (instanceRef VCC)) - (portRef ENA (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N2 "dina<7>") - (joined - (portRef dina_7_) - (portRef DIA_7_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N3 "dina<6>") - (joined - (portRef dina_6_) - (portRef DIA_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N4 "dina<5>") - (joined - (portRef dina_5_) - (portRef DIA_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N5 "dina<4>") - (joined - (portRef dina_4_) - (portRef DIA_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N6 "dina<3>") - (joined - (portRef dina_3_) - (portRef DIA_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N7 "dina<2>") - (joined - (portRef dina_2_) - (portRef DIA_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N8 "dina<1>") - (joined - (portRef dina_1_) - (portRef DIA_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N9 "dina<0>") - (joined - (portRef dina_0_) - (portRef DIA_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N19 "enb") - (joined - (portRef enb) - (portRef ENB (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N20 "wea") - (joined - (portRef wea) - (portRef WEA (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N22 "sinita") - (joined - (portRef sinita) - (portRef SSRA (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N23 "sinitb") - (joined - (portRef sinitb) - (portRef SSRB (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N26 "clka") - (joined - (portRef clka) - (portRef CLKA (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N27 "clkb") - (joined - (portRef clkb) - (portRef CLKB (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N28 "addra<6>") - (joined - (portRef addra_6_) - (portRef ADDRA_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N29 "addra<5>") - (joined - (portRef addra_5_) - (portRef ADDRA_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N30 "addra<4>") - (joined - (portRef addra_4_) - (portRef ADDRA_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N31 "addra<3>") - (joined - (portRef addra_3_) - (portRef ADDRA_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N32 "addra<2>") - (joined - (portRef addra_2_) - (portRef ADDRA_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N33 "addra<1>") - (joined - (portRef addra_1_) - (portRef ADDRA_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N34 "addra<0>") - (joined - (portRef addra_0_) - (portRef ADDRA_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N35 "addrb<6>") - (joined - (portRef addrb_6_) - (portRef ADDRB_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N36 "addrb<5>") - (joined - (portRef addrb_5_) - (portRef ADDRB_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N37 "addrb<4>") - (joined - (portRef addrb_4_) - (portRef ADDRB_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N38 "addrb<3>") - (joined - (portRef addrb_3_) - (portRef ADDRB_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N39 "addrb<2>") - (joined - (portRef addrb_2_) - (portRef ADDRB_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N40 "addrb<1>") - (joined - (portRef addrb_1_) - (portRef ADDRB_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N41 "addrb<0>") - (joined - (portRef addrb_0_) - (portRef ADDRB_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N54 "doutb<7>") - (joined - (portRef doutb_7_) - (portRef DOB_7_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N55 "doutb<6>") - (joined - (portRef doutb_6_) - (portRef DOB_6_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N56 "doutb<5>") - (joined - (portRef doutb_5_) - (portRef DOB_5_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N57 "doutb<4>") - (joined - (portRef doutb_4_) - (portRef DOB_4_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N58 "doutb<3>") - (joined - (portRef doutb_3_) - (portRef DOB_3_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N59 "doutb<2>") - (joined - (portRef doutb_2_) - (portRef DOB_2_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N60 "doutb<1>") - (joined - (portRef doutb_1_) - (portRef DOB_1_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) - (net (rename N61 "doutb<0>") - (joined - (portRef doutb_0_) - (portRef DOB_0_ (instanceRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst_bm_mem_arch_v2_prim_3_b1_chk0_col_0_b2_mextd_arch_v2_c1_ram1_v2_d2048_by9_newSim8)) - ) - ) -)))) -(design async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst (cellRef async_fifo_8_8_128_fifo_generator_v2_2_xst_1_blkmemdp_v6_2_xst (libraryRef test_lib)) - (property X_CORE_INFO (string "null")) - (property PART (string "XC2VP20-6-ff896") (owner "Xilinx"))) -) diff --git a/src/edu/berkeley/fleet/fpga/main.ucf b/src/edu/berkeley/fleet/fpga/main.ucf index 59d4b9a..60dfc53 100644 --- a/src/edu/berkeley/fleet/fpga/main.ucf +++ b/src/edu/berkeley/fleet/fpga/main.ucf @@ -1,33 +1,696 @@ -###################################### -## System clock pins -###################################### +############################################################################ +## This system.ucf file is generated by Base System Builder based on the +## settings in the selected Xilinx Board Definition file. Please add other +## user constraints to this file based on customer design specifications. +############################################################################ -NET User_Clk PERIOD=100MHz; +#Net fpga_0_PCI32_BRIDGE_PCI_INTA LOC=P5; +#Net fpga_0_PCI32_BRIDGE_PCI_INTA IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_PCI_INTA TIG; +#Net fpga_0_PCI32_BRIDGE_PCI_INTB LOC=R8; +#Net fpga_0_PCI32_BRIDGE_PCI_INTB IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_PCI_INTB TIG; +#Net fpga_0_PCI32_BRIDGE_PCI_INTC LOC=P9; +#Net fpga_0_PCI32_BRIDGE_PCI_INTC IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_PCI_INTC TIG; +#Net fpga_0_PCI32_BRIDGE_PCI_INTD LOC=V4; +#Net fpga_0_PCI32_BRIDGE_PCI_INTD IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_PCI_INTD TIG; +#Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT LOC=AE21; +#Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT IOSTANDARD = LVCMOS25; +#Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT TIG; +Net sys_clk_pin LOC=J16; +Net sys_clk_pin IOSTANDARD = LVCMOS25; +Net sys_rst_pin LOC=H7; +Net sys_rst_pin PULLUP; +Net sys_rst_pin IOSTANDARD = LVCMOS33; +### System level constraints +#Net sys_clk_pin TNM_NET = sys_clk_pin; +#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; +#Net sys_rst_pin TIG; +#NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP"; +#NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP"; +#NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP"; +#TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; +#Net fpga_0_PCI_CLK_FB LOC=H17; +#Net fpga_0_PCI_CLK_FB IOSTANDARD = LVCMOS25; +#Net fpga_0_PCI_CLK_FB TNM_NET = PCI_CLK; +#Net PCI32_BRIDGE/OPB_Clk TNM_NET = SYS_CLK; +##TIMESPEC TS_PCI_BUS = FROM PCI_CLK TO SYS_CLK 10000 ps; +#TIMESPEC "TS_PCI_BUS" = FROM "PCI_CLK" TO "SYS_CLK" 9.9ns datapathonly; +#TIMESPEC TS_BUS_PCI = FROM SYS_CLK TO PCI_CLK 30000 ps; +#Net fpga_0_PCI_CLK_OUT0 LOC=V5; +#Net fpga_0_PCI_CLK_OUT0 IOSTANDARD = PCI33_3; +#Net fpga_0_PCI_CLK_OUT1 LOC=T11; +#Net fpga_0_PCI_CLK_OUT1 IOSTANDARD = PCI33_3; +#Net fpga_0_PCI_CLK_OUT2 LOC=U6; +#Net fpga_0_PCI_CLK_OUT2 IOSTANDARD = PCI33_3; +#Net fpga_0_PCI_CLK_OUT3 LOC=U7; +#Net fpga_0_PCI_CLK_OUT3 IOSTANDARD = PCI33_3; +#Net fpga_0_PCI_CLK_OUT4 LOC=U3; +#Net fpga_0_PCI_CLK_OUT4 IOSTANDARD = PCI33_3; +#Net fpga_0_PCI_CLK_OUT5 LOC=U5; +#Net fpga_0_PCI_CLK_OUT5 IOSTANDARD = PCI33_3; +#Net fpga_0_DDR_CLK_FB LOC=K18; +#Net fpga_0_DDR_CLK_FB IOSTANDARD = LVCMOS25; +# +### IO Devices constraints +# +##### Module RS232_Uart_1 constraints +# +Net fpga_0_RS232_Uart_1_ctsN_pin LOC=G6; +Net fpga_0_RS232_Uart_1_ctsN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_RS232_Uart_1_ctsN_pin TIG; +Net fpga_0_RS232_Uart_1_rtsN_pin LOC=F6; +Net fpga_0_RS232_Uart_1_rtsN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_RS232_Uart_1_rtsN_pin TIG; -NET Clkin_p LOC = AP21 | IOSTANDARD = LVDS_25; -NET Clkin_m LOC = AN21 | IOSTANDARD = LVDS_25; +Net fpga_0_RS232_Uart_1_sin_pin LOC=E6; +Net fpga_0_RS232_Uart_1_sin_pin IOSTANDARD = LVCMOS33; +Net fpga_0_RS232_Uart_1_sin_pin TIG; +Net fpga_0_RS232_Uart_1_sin_pin PULLUP; -###################################### -## SelectMAP interface pins -###################################### +Net fpga_0_RS232_Uart_1_sout_pin LOC=D6; +Net fpga_0_RS232_Uart_1_sout_pin IOSTANDARD = LVCMOS33; +Net fpga_0_RS232_Uart_1_sout_pin TIG; +Net fpga_0_RS232_Uart_1_sout_pin PULLUP; -NET D_I<0> LOC = AU9 | IOSTANDARD = LVCMOS25; -NET D_I<1> LOC = AV9 | IOSTANDARD = LVCMOS25; -NET D_I<2> LOC = AY9 | IOSTANDARD = LVCMOS25; -NET D_I<3> LOC = AW9 | IOSTANDARD = LVCMOS25; -NET D_I<4> LOC = AW34 | IOSTANDARD = LVCMOS25; -NET D_I<5> LOC = AY34 | IOSTANDARD = LVCMOS25; -NET D_I<6> LOC = AV34 | IOSTANDARD = LVCMOS25; -NET D_I<7> LOC = AU34 | IOSTANDARD = LVCMOS25; - -NET RDWR_B LOC = AR34 | IOSTANDARD = LVCMOS25; -NET CS_B LOC = AT34 | IOSTANDARD = LVCMOS25; -NET INIT_B LOC = AR9 | IOSTANDARD = LVCMOS25; -NET CCLK LOC = C14 | IOSTANDARD = LVCMOS25; - -NET gpleds<1> LOC = AB6 | IOSTANDARD = LVCMOS18 | DRIVE = 24; -NET gpleds<2> LOC = AB7 | IOSTANDARD = LVCMOS18 | DRIVE = 24; -NET gpleds<3> LOC = AB9 | IOSTANDARD = LVCMOS18 | DRIVE = 24; -NET gpleds<4> LOC = AB10 | IOSTANDARD = LVCMOS18 | DRIVE = 24; -NET gpleds<5> LOC = AD7 | IOSTANDARD = LVCMOS18 | DRIVE = 24; -NET gpleds<6> LOC = AF1 | IOSTANDARD = LVCMOS18 | DRIVE = 24; +##### Module DDR_SDRAM_32Mx64 constraints +# +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<12> LOC=P24; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<11> LOC=P22; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<10> LOC=N22; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<9> LOC=N23; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<8> LOC=N24; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<7> LOC=M23; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<6> LOC=L24; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<5> LOC=L25; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<4> LOC=L26; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<3> LOC=K23; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<2> LOC=K24; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<1> LOC=K26; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<0> LOC=J24; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<1> LOC=J25; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<0> LOC=J26; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin LOC=D26; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin LOC=H14; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin LOC=C27; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin LOC=D27; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin LOC=E27; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<0> LOC=G23; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<0> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<1> LOC=E23; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<1> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<2> LOC=G22; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<2> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<3> LOC=F21; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<3> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<0> LOC=F25; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<1> LOC=G25; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<2> LOC=G20; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<3> LOC=F20; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<0> LOC=E22; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<1> LOC=E24; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<2> LOC=H24; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<3> LOC=H25; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<4> LOC=G26; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<5> LOC=F26; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<6> LOC=F24; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<7> LOC=F23; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<8> LOC=C28; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<9> LOC=D25; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<10> LOC=D24; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<11> LOC=D22; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<12> LOC=C25; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<13> LOC=C24; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<14> LOC=C23; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<15> LOC=C22; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<16> LOC=H22; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<17> LOC=J22; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<18> LOC=L21; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<19> LOC=K21; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<20> LOC=J21; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<21> LOC=J20; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<22> LOC=H20; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<23> LOC=G21; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<24> LOC=E21; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<25> LOC=D21; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<26> LOC=E19; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<27> LOC=F19; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<28> LOC=G18; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<29> LOC=F18; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<30> LOC=E18; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<31> LOC=E17; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin LOC=F28; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin IOSTANDARD = SSTL2_I; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin LOC=E28; +#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin IOSTANDARD = SSTL2_I; +# +##### Module SPI_EEPROM constraints +# +#Net fpga_0_SPI_EEPROM_SCK_pin LOC=AF21; +#Net fpga_0_SPI_EEPROM_SCK_pin IOSTANDARD = LVCMOS25; +#Net fpga_0_SPI_EEPROM_SCK_pin TIG; +#Net fpga_0_SPI_EEPROM_SCK_pin PULLUP; +#Net fpga_0_SPI_EEPROM_MOSI_pin LOC=AH22; +#Net fpga_0_SPI_EEPROM_MOSI_pin TIG; +#Net fpga_0_SPI_EEPROM_MOSI_pin PULLUP; +#Net fpga_0_SPI_EEPROM_MISO_pin LOC=AJ22; +#Net fpga_0_SPI_EEPROM_MISO_pin TIG; +#Net fpga_0_SPI_EEPROM_MISO_pin PULLUP; +#Net fpga_0_SPI_EEPROM_SS_pin<0> LOC=AG22; +#Net fpga_0_SPI_EEPROM_SS_pin<0> TIG; +#Net fpga_0_SPI_EEPROM_SS_pin<0> PULLUP; +# +##### Module LEDs_8Bit constraints +# +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC=AF19; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> TIG; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC=AD5; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS33; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> TIG; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC=AD6; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS33; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> TIG; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC=AD7; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS33; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> TIG; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC=AB8; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS33; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> TIG; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC=AC7; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS33; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> TIG; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC=AC9; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS33; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> TIG; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC=AC10; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS33; +#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> TIG; +# +##### Module LCD_OPTIONAL constraints +# +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> LOC=AH19; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> LOC=AJ19; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> LOC=AK19; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> LOC=AG20; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> LOC=AH20; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> LOC=AJ20; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> LOC=AG21; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> LOC=AJ21; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> LOC=AK17; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> LOC=AH18; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> LOC=AK18; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> TIG; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> LOC=AJ17; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> IOSTANDARD = LVCMOS25; +#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> TIG; +# +##### Module pci_arbiter_0 constraints +# +#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<1> LOC=T4; +#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<1> IOSTANDARD = PCI33_3; +#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<2> LOC=T5; +#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<2> IOSTANDARD = PCI33_3; +#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<3> LOC=U8; +#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<3> IOSTANDARD = PCI33_3; +#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<4> LOC=V3; +#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<4> IOSTANDARD = PCI33_3; +#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<5> LOC=T6; +#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<5> IOSTANDARD = PCI33_3; +#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<1> LOC=T3; +#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<1> IOSTANDARD = PCI33_3; +#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<2> LOC=R7; +#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<2> IOSTANDARD = PCI33_3; +#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<3> LOC=T8; +#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<3> IOSTANDARD = PCI33_3; +#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<4> LOC=T9; +#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<4> IOSTANDARD = PCI33_3; +#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<5> LOC=R9; +#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<5> IOSTANDARD = PCI33_3; +# +##### Module PCI32_BRIDGE constraints +# +#Net fpga_0_PCI32_BRIDGE_PAR LOC=L8; +#Net fpga_0_PCI32_BRIDGE_PAR IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_PAR BYPASS; +#Net fpga_0_PCI32_BRIDGE_PERR_N LOC=M6; +#Net fpga_0_PCI32_BRIDGE_PERR_N IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_PERR_N BYPASS; +#Net fpga_0_PCI32_BRIDGE_SERR_N LOC=M7; +#Net fpga_0_PCI32_BRIDGE_SERR_N IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_SERR_N BYPASS; +#Net fpga_0_PCI32_BRIDGE_IRDY_N LOC=N5; +#Net fpga_0_PCI32_BRIDGE_IRDY_N IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_IRDY_N BYPASS; +#Net fpga_0_PCI32_BRIDGE_FRAME_N LOC=N8; +#Net fpga_0_PCI32_BRIDGE_FRAME_N IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_FRAME_N BYPASS; +#Net fpga_0_PCI32_BRIDGE_DEVSEL_N LOC=R3; +#Net fpga_0_PCI32_BRIDGE_DEVSEL_N IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_DEVSEL_N BYPASS; +#Net fpga_0_PCI32_BRIDGE_STOP_N LOC=P11; +#Net fpga_0_PCI32_BRIDGE_STOP_N IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_STOP_N BYPASS; +#Net fpga_0_PCI32_BRIDGE_TRDY_N LOC=M3; +#Net fpga_0_PCI32_BRIDGE_TRDY_N IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_TRDY_N BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<31> LOC=P7; +#Net fpga_0_PCI32_BRIDGE_AD<31> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<31> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<30> LOC=P6; +#Net fpga_0_PCI32_BRIDGE_AD<30> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<30> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<29> LOC=K7; +#Net fpga_0_PCI32_BRIDGE_AD<29> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<29> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<28> LOC=K6; +#Net fpga_0_PCI32_BRIDGE_AD<28> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<28> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<27> LOC=L3; +#Net fpga_0_PCI32_BRIDGE_AD<27> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<27> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<26> LOC=K8; +#Net fpga_0_PCI32_BRIDGE_AD<26> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<26> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<25> LOC=M10; +#Net fpga_0_PCI32_BRIDGE_AD<25> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<25> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<24> LOC=M8; +#Net fpga_0_PCI32_BRIDGE_AD<24> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<24> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<23> LOC=J7; +#Net fpga_0_PCI32_BRIDGE_AD<23> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<23> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<22> LOC=J6; +#Net fpga_0_PCI32_BRIDGE_AD<22> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<22> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<21> LOC=K4; +#Net fpga_0_PCI32_BRIDGE_AD<21> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<21> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<20> LOC=K3; +#Net fpga_0_PCI32_BRIDGE_AD<20> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<20> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<19> LOC=N10; +#Net fpga_0_PCI32_BRIDGE_AD<19> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<19> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<18> LOC=N9; +#Net fpga_0_PCI32_BRIDGE_AD<18> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<18> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<17> LOC=H5; +#Net fpga_0_PCI32_BRIDGE_AD<17> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<17> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<16> LOC=H4; +#Net fpga_0_PCI32_BRIDGE_AD<16> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<16> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<15> LOC=J5; +#Net fpga_0_PCI32_BRIDGE_AD<15> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<15> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<14> LOC=J4; +#Net fpga_0_PCI32_BRIDGE_AD<14> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<14> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<13> LOC=L10; +#Net fpga_0_PCI32_BRIDGE_AD<13> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<13> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<12> LOC=L9; +#Net fpga_0_PCI32_BRIDGE_AD<12> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<12> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<11> LOC=G3; +#Net fpga_0_PCI32_BRIDGE_AD<11> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<11> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<10> LOC=F5; +#Net fpga_0_PCI32_BRIDGE_AD<10> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<10> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<9> LOC=F3; +#Net fpga_0_PCI32_BRIDGE_AD<9> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<9> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<8> LOC=G5; +#Net fpga_0_PCI32_BRIDGE_AD<8> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<8> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<7> LOC=N4; +#Net fpga_0_PCI32_BRIDGE_AD<7> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<7> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<6> LOC=N3; +#Net fpga_0_PCI32_BRIDGE_AD<6> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<6> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<5> LOC=E4; +#Net fpga_0_PCI32_BRIDGE_AD<5> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<5> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<4> LOC=E3; +#Net fpga_0_PCI32_BRIDGE_AD<4> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<4> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<3> LOC=F4; +#Net fpga_0_PCI32_BRIDGE_AD<3> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<3> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<2> LOC=H3; +#Net fpga_0_PCI32_BRIDGE_AD<2> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<2> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<1> LOC=L5; +#Net fpga_0_PCI32_BRIDGE_AD<1> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<1> BYPASS; +#Net fpga_0_PCI32_BRIDGE_AD<0> LOC=L4; +#Net fpga_0_PCI32_BRIDGE_AD<0> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_AD<0> BYPASS; +#Net fpga_0_PCI32_BRIDGE_CBE<3> LOC=R6; +#Net fpga_0_PCI32_BRIDGE_CBE<3> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_CBE<3> BYPASS; +#Net fpga_0_PCI32_BRIDGE_CBE<2> LOC=R4; +#Net fpga_0_PCI32_BRIDGE_CBE<2> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_CBE<2> BYPASS; +#Net fpga_0_PCI32_BRIDGE_CBE<1> LOC=L6; +#Net fpga_0_PCI32_BRIDGE_CBE<1> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_CBE<1> BYPASS; +#Net fpga_0_PCI32_BRIDGE_CBE<0> LOC=M5; +#Net fpga_0_PCI32_BRIDGE_CBE<0> IOSTANDARD = PCI33_3; +#Net fpga_0_PCI32_BRIDGE_CBE<0> BYPASS; +# +##### Module SysACE_CompactFlash constraints +# +#Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF16; +#Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 29000 ps; +#Net fpga_0_SysACE_CompactFlash_clk_enable_n_pin LOC=AD4; +#Net fpga_0_SysACE_CompactFlash_clk_enable_n_pin IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=AE6; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AE4; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AE3; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AF6; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AF5; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AF4; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=AF3; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AG6; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AG5; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AG3; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AH5; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AH4; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AH3; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AJ6; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AJ5; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AJ4; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AK6; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AK4; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AK3; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AL6; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AL5; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AL4; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA3; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AB6; +#Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AM5; +#Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AB3; +#Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AM6; +#Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33; +# +##### Module IIC_Bus constraints +# +#Net fpga_0_IIC_Bus_Scl_pin LOC=E7; +#Net fpga_0_IIC_Bus_Scl_pin IOSTANDARD = LVCMOS33; +#Net fpga_0_IIC_Bus_Sda_pin LOC=D7; +#Net fpga_0_IIC_Bus_Sda_pin IOSTANDARD = LVCMOS33; +# +##### Module ORGate_1 constraints +# +#Net fpga_0_ORGate_1_Res_pin LOC=AE18; +#Net fpga_0_ORGate_1_Res_pin TIG; +#Net fpga_0_ORGate_1_Res_1_pin LOC=AE17; +#Net fpga_0_ORGate_1_Res_1_pin TIG; +#Net fpga_0_ORGate_1_Res_2_pin LOC=R11; +#Net fpga_0_ORGate_1_Res_2_pin IOSTANDARD = PCI33_3; +# +##### Module TriMode_MAC_GMII constraints +# +#Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin LOC = M12; +#Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin IOSTANDARD=LVCMOS33; +#Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin TIG; +# +##### Module Hard_Temac_0 constraints +# +#Net fpga_0_Hard_Temac_0_MII_TXD_0<3> LOC = K9; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<3> IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<3> SLEW=FAST; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<2> LOC = K11; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<2> IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<2> SLEW=FAST; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<1> LOC = K12; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<1> IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<1> SLEW=FAST; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<0> LOC = K13; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<0> IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MII_TXD_0<0> SLEW=FAST; +#Net fpga_0_Hard_Temac_0_MII_TX_EN_0 LOC = L11; +#Net fpga_0_Hard_Temac_0_MII_TX_EN_0 IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MII_TX_EN_0 SLEW=FAST; +#Net fpga_0_Hard_Temac_0_MII_TX_ER_0 LOC = L14; +#Net fpga_0_Hard_Temac_0_MII_TX_ER_0 IOSTANDARD=LVCMOS25; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<3> LOC = J9; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<3> IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<3> IOBDELAY = NONE; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<2> LOC = J10; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<2> IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<2> IOBDELAY = NONE; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<1> LOC = J11; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<1> IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<1> IOBDELAY = NONE; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<0> LOC = J12; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<0> IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MII_RXD_0<0> IOBDELAY = NONE; +#Net fpga_0_Hard_Temac_0_MII_RX_DV_0 LOC = H12; +#Net fpga_0_Hard_Temac_0_MII_RX_DV_0 IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MII_RX_DV_0 IOBDELAY = NONE; +#Net fpga_0_Hard_Temac_0_MII_RX_ER_0 LOC = H18; +#Net fpga_0_Hard_Temac_0_MII_RX_ER_0 IOSTANDARD=LVCMOS25; +#Net fpga_0_Hard_Temac_0_MII_RX_ER_0 IOBDELAY = NONE; +#Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 LOC=J14; +#Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 MAXSKEW= 2.0 ns; +#Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 IOSTANDARD=LVCMOS25; +#Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 LOC=K19; +#Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 MAXSKEW= 2.0 ns; +#Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 IOSTANDARD=LVCMOS25; +#Net fpga_0_Hard_Temac_0_MDIO_0_pin LOC = L13; +#Net fpga_0_Hard_Temac_0_MDIO_0_pin IOSTANDARD=LVCMOS33; +#Net fpga_0_Hard_Temac_0_MDC_0_pin LOC = M13; +#Net fpga_0_Hard_Temac_0_MDC_0_pin IOSTANDARD=LVCMOS33; +# +#Net fpga_0_DDR_CLK_FB TNM_NET = fpga_0_DDR_CLK_FB; +#TIMESPEC TS_fpga_0_DDR_CLK_FB = PERIOD fpga_0_DDR_CLK_FB 10000 ps; +# +##### AR 22677 +# +#AREA_GROUP "opb2plb" RANGE=SLICE_X20Y104:SLICE_X33Y139, SLICE_X34Y96:SLICE_X51Y139; +#INST "opb2plb" AREA_GROUP = "opb2plb"; +#AREA_GROUP "pblock_spi_eeprom" RANGE=SLICE_X54Y92:SLICE_X67Y111; +#INST "spi_eeprom" AREA_GROUP = "pblock_spi_eeprom"; +#AREA_GROUP "pblock_plb2opb" RANGE= SLICE_X34Y140:SLICE_X51Y191; +#INST "plb2opb" AREA_GROUP = "pblock_plb2opb"; +## These two items here no longer exist in 8.2i +## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CARRY_MUX*" AREA_GROUP = "pblock_plb2opb"; +## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CYMUX_FIRST*" AREA_GROUP = "pblock_plb2opb"; +# +## The path "I_PLB_ADDRPATH/I_PLBADDR_MUX" doesn't exist either; using *? to replace it +## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/_n*" AREA_GROUP = "pblock_plb2opb"; +#INST "plb/plb/*?/_n*" AREA_GROUP = "pblock_plb2opb"; +#INST "plb/plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/*" AREA_GROUP = "pblock_plb2opb"; +# +################################### +#### Virtex-4 FX60-FF1152 MGT Null Tile LOCs ### +################################### +##MGT113A +#INST MGT113AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y7; +#NET "MGT113AB_TXN<1>" LOC = "A3"; #TXN +#NET "MGT113AB_TXP<1>" LOC = "A4"; #TXP +#NET "MGT113AB_RXN<1>" LOC = "A6"; #RXN +#NET "MGT113AB_RXP<1>" LOC = "A7"; #RXP +##MGT113B +#INST MGT113AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y6; +#NET "MGT113AB_TXN<0>" LOC = "D1"; #TXN +#NET "MGT113AB_TXP<0>" LOC = "C1"; #TXP +#NET "MGT113AB_RXN<0>" LOC = "G1"; #RXN +#NET "MGT113AB_RXP<0>" LOC = "F1"; #RXP +##MGT112A +#INST MGT112AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y5; +#NET "MGT112AB_TXN<1>" LOC = "T1"; #TXN +#NET "MGT112AB_TXP<1>" LOC = "R1"; #TXP +#NET "MGT112AB_RXN<1>" LOC = "N1"; #RXN +#NET "MGT112AB_RXP<1>" LOC = "M1"; #RXP +##MGT112B +#INST MGT112AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y4; +#NET "MGT112AB_TXN<0>" LOC = "V1"; #TXN +#NET "MGT112AB_TXP<0>" LOC = "U1"; #TXP +#NET "MGT112AB_RXN<0>" LOC = "AA1"; #RXN +#NET "MGT112AB_RXP<0>" LOC = "Y1"; #RXP +##MGT110A +#INST MGT110AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y3; +#NET "MGT110AB_TXN<1>" LOC = "AG1"; #TXN +#NET "MGT110AB_TXP<1>" LOC = "AF1"; #TXP +#NET "MGT110AB_RXN<1>" LOC = "AD1"; #RXN +#NET "MGT110AB_RXP<1>" LOC = "AC1"; #RXP +##MGT110B +#INST MGT110AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y2; +#NET "MGT110AB_TXN<0>" LOC = "AJ1"; #TXN +#NET "MGT110AB_TXP<0>" LOC = "AH1"; #TXP +#NET "MGT110AB_RXN<0>" LOC = "AM1"; #RXN +#NET "MGT110AB_RXP<0>" LOC = "AL1"; #RXP +##MGT109A +#INST MGT109AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y1; +#NET "MGT109AB_TXN<1>" LOC = "AP10"; #TXN +#NET "MGT109AB_TXP<1>" LOC = "AP9"; #TXP +#NET "MGT109AB_RXN<1>" LOC = "AP7"; #RXN +#NET "MGT109AB_RXP<1>" LOC = "AP6"; #RXP +##MGT109B +#INST MGT109AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y0; +#NET "MGT109AB_TXN<0>" LOC = "AP12"; #TXN +#NET "MGT109AB_TXP<0>" LOC = "AP11"; #TXP +#NET "MGT109AB_RXN<0>" LOC = "AP15"; #RXN +#NET "MGT109AB_RXP<0>" LOC = "AP14"; #RXP +##MGT102A +#INST MGT102AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y7; +#NET "MGT102AB_TXN<1>" LOC = "E34"; #TXN +#NET "MGT102AB_TXP<1>" LOC = "D34"; #TXP +#NET "MGT102AB_RXN<1>" LOC = "A32"; #RXN +#NET "MGT102AB_RXP<1>" LOC = "A31"; #RXP +# +##MGT102B +#INST MGT102AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y6; +#NET "MGT102AB_TXN<0>" LOC = "G34"; #TXN +#NET "MGT102AB_TXP<0>" LOC = "F34"; #TXP +#NET "MGT102AB_RXN<0>" LOC = "K34"; #RXN +#NET "MGT102AB_RXP<0>" LOC = "J34"; #RXP +##MGT103A +#INST MGT103AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y5; +#NET "MGT103AB_TXN<1>" LOC = "W34"; #TXN +#NET "MGT103AB_TXP<1>" LOC = "V34"; #TXP +#NET "MGT103AB_RXN<1>" LOC = "T34"; #RXN +#NET "MGT103AB_RXP<1>" LOC = "R34"; #RXP +##MGT103B +#INST MGT103AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y4; +#NET "MGT103AB_TXN<0>" LOC = "AA34"; #TXN +#NET "MGT103AB_TXP<0>" LOC = "Y34"; #TXP +#NET "MGT103AB_RXN<0>" LOC = "AD34"; #RXN +#NET "MGT103AB_RXP<0>" LOC = "AC34"; #RXP +##MGT105A +#INST MGT105AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y3; +#NET "MGT105AB_TXN<1>" LOC = "AK34"; #TXN +#NET "MGT105AB_TXP<1>" LOC = "AJ34"; #TXP +#NET "MGT105AB_RXN<1>" LOC = "AG34"; #RXN +#NET "MGT105AB_RXP<1>" LOC = "AF34"; #RXP +##MGT105B +#INST MGT105AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y2; +#NET "MGT105AB_TXN<0>" LOC = "AM34"; #TXN +#NET "MGT105AB_TXP<0>" LOC = "AL34"; #TXP +#NET "MGT105AB_RXN<0>" LOC = "AP31"; #RXN +#NET "MGT105AB_RXP<0>" LOC = "AP32"; #RXP +##MGT106A +#INST MGT106AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y1; +#NET "MGT106AB_TXN<1>" LOC = "AP22"; #TXN +#NET "MGT106AB_TXP<1>" LOC = "AP23"; #TXP +#NET "MGT106AB_RXN<1>" LOC = "AP25"; #RXN +#NET "MGT106AB_RXP<1>" LOC = "AP26"; #RXP +##MGT106B +#INST MGT106AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y0; +#NET "MGT106AB_TXN<0>" LOC = "AP20"; #TXN +#NET "MGT106AB_TXP<0>" LOC = "AP21"; #TXP +#NET "MGT106AB_RXN<0>" LOC = "AP17"; #RXN +#NET "MGT106AB_RXP<0>" LOC = "AP18"; #RXP +# diff --git a/src/edu/berkeley/fleet/fpga/main.ut b/src/edu/berkeley/fleet/fpga/main.ut index 8ea3a85..4641f0d 100644 --- a/src/edu/berkeley/fleet/fpga/main.ut +++ b/src/edu/berkeley/fleet/fpga/main.ut @@ -1,37 +1,21 @@ -w --g DebugBitstream:No --g Binary:no --g CRC:Enable --g ConfigRate:4 --g CclkPin:PullUp --g M0Pin:PullUp --g M1Pin:PullUp --g M2Pin:PullUp --g ProgPin:PullUp --g DonePin:PullUp --g PowerdownPin:PullUp --g TckPin:PullUp --g TdiPin:PullUp --g TdoPin:PullNone --g TmsPin:PullUp --g UnusedPin:PullDown --g UserID:0xFFFFFFFF --g DCMShutdown:Disable --g DisableBandgap:No --g DCIUpdateMode:AsRequired --g StartUpClk:CClk +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g DriveDone:No +-g StartUpClk:JTAGCLK -g DONE_cycle:4 -g GTS_cycle:5 +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No -g GWE_cycle:6 -g LCK_cycle:NoWait --g Security:None --g DonePipe:No --g DriveDone:No --g Encrypt:No - - - - - - - +-g Security:NONE +#-m +-g Persist:No diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v index e00f5e5..e3ae759 100644 --- a/src/edu/berkeley/fleet/fpga/main.v +++ b/src/edu/berkeley/fleet/fpga/main.v @@ -1,319 +1,86 @@ -`timescale 1ps / 1ps - -// Copyright (c) 2005-2006, Regents of the University of California -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// -// - Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer -// in the documentation and/or other materials provided with the -// distribution. -// - Neither the name of the University of California, Berkeley nor the -// names of its contributors may be used to endorse or promote -// products derived from this software without specific prior -// written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -//---------------------------------------------------------------------------- -// user_fifo.v -//---------------------------------------------------------------------------- - -`timescale 1ps / 1ps - -module user_fifo - ( - // FIFO interface ports - WrFifo_Din, // Write FIFO data-in - WrFifo_WrEn, // Write FIFO write enable - WrFifo_Full, // Write FIFO full - WrFifo_WrCnt, // Write FIFO write count - RdFifo_Dout, // Read FIFO data-out - RdFifo_RdEn, // Read FIFO read enable - RdFifo_Empty, // Read FIFO empty - RdFifo_RdCnt, // Read FIFO read count - User_Rst, // User reset - User_Clk, // User clock - Sys_Rst, // System clock reset - Sys_Clk, // 100MHz system clock for CCLK generation - - // SelectMAP interface ports - D_I, // Data bus input - D_O, // Data bus output - D_T, // Data bus tristate enable - RDWR_B, // Read/write signal - CS_B, // Chip select - INIT_B, // Initialization/interrupt signal - CCLK // CCLK output - ); - - // FIFO interface ports - input [0:7] WrFifo_Din; - input WrFifo_WrEn; - output WrFifo_Full; - output [0:7] WrFifo_WrCnt; - output [0:7] RdFifo_Dout; - input RdFifo_RdEn; - output RdFifo_Empty; - output [0:7] RdFifo_RdCnt; - input User_Rst; - input User_Clk; - input Sys_Rst; - input Sys_Clk; - - // SelectMAP protocol ports - input [0:7] D_I; - output [0:7] D_O; - output [0:7] D_T; - input RDWR_B; - input CS_B; - output INIT_B; - output CCLK; - - // ____ __ _ _ _ _ // - // | _ \ ___ / _(_)_ __ (_) |_(_) ___ _ __ ___ // - // | | | |/ _ \ |_| | '_ \| | __| |/ _ \| '_ \/ __| // - // | |_| | __/ _| | | | | | |_| | (_) | | | \__ \ // - // |____/ \___|_| |_|_| |_|_|\__|_|\___/|_| |_|___/ // - // // - - //---------------------------------------------------------------------------- - // Signal definitions - //---------------------------------------------------------------------------- - // Write FIFO signals - wire [0:7] WrFifo_Dout; - wire WrFifo_Empty; - wire WrFifo_RdEn; - wire [0:7] WrFifo_RdCnt; - wire [0:7] WrFifo_RdCnt_int; - wire [0:7] WrFifo_WrCnt_int; - - // Read FIFO signals - wire [0:7] RdFifo_Din; - wire RdFifo_Full; - wire RdFifo_WrEn; - wire [0:7] RdFifo_WrCnt; - wire [0:7] RdFifo_WrCnt_int; - wire [0:7] RdFifo_RdCnt_int; - - //---------------------------------------------------------------------------- - // IO Registers - //---------------------------------------------------------------------------- - reg CCLK; - - reg [0:7] D_I_reg; // synthesis attribute iob of D_I_reg is true; - reg [0:7] D_O_reg; // synthesis attribute iob of D_O_reg is true; - reg RDWR_B_reg; // synthesis attribute iob of RDWR_B_reg is true; - reg CS_B_reg; // synthesis attribute iob of CS_B_reg is true; - reg INIT_B_reg; // synthesis attribute iob of INIT_B_reg is true; - - // Outputs - assign D_O = D_O_reg; - assign INIT_B = INIT_B_reg; - - // Inputs - always @( posedge Sys_Clk ) - begin - D_I_reg <= D_I; - RDWR_B_reg <= RDWR_B; - CS_B_reg <= CS_B; - end - - //---------------------------------------------------------------------------- - // Generate CCLK and associated reset - //---------------------------------------------------------------------------- - reg SYNC_done; - reg SYNC_done_dly; - reg CS_B_reg_dly; - - always @( posedge Sys_Clk ) - begin - CS_B_reg_dly <= CS_B_reg; - end - - always @( posedge Sys_Clk ) - begin - if (Sys_Rst) - SYNC_done <= 1'b0; - else if (RDWR_B_reg && ~CS_B_reg) - SYNC_done <= 1'b1; - end - - always @( posedge Sys_Clk ) - begin - if (Sys_Rst) - SYNC_done_dly <= 1'b0; - else - SYNC_done_dly <= SYNC_done; - end - - always @( posedge Sys_Clk ) - begin - if (Sys_Rst) - CCLK <= 1'b0; - else if (~CS_B_reg && CS_B_reg_dly && CCLK) - CCLK <= 1'b1; - else - CCLK <= ~CCLK; - end - - // _____ ___ _____ ___ // - // | ___|_ _| ___/ _ \ ___ // - // | |_ | || |_ | | | / __| // - // | _| | || _|| |_| \__ \ // - // |_| |___|_| \___/|___/ // - // // - // Write FIFO: The write is with respect to the user. The user writes data to this - // FIFO and the control side of SelectMAP reads the data. - // - // Read FIFO: The read is with respect to the user. The user reads data sent from the - // control side of SelectMAP. - // - - //---------------------------------------------------------------------------- - // Read FIFO - //---------------------------------------------------------------------------- - assign RdFifo_WrEn = SYNC_done_dly && ~RDWR_B_reg && ~CS_B_reg && ~RdFifo_Full && CCLK; - assign RdFifo_Din = D_I_reg; - - async_fifo_8_8_128 RdFifo( .din( RdFifo_Din ), - .dout( RdFifo_Dout ), - .rd_clk( User_Clk ), - .rd_en( RdFifo_RdEn ), - .wr_clk( Sys_Clk ), - .wr_en( RdFifo_WrEn ), - .rst( User_Rst ), - .empty( RdFifo_Empty ), - .full( RdFifo_Full ), - .rd_data_count( RdFifo_RdCnt_int ), - .wr_data_count( RdFifo_WrCnt_int ) ); - - assign RdFifo_WrCnt = 8'd129 - RdFifo_WrCnt_int; - assign RdFifo_RdCnt = RdFifo_RdCnt_int; - - //---------------------------------------------------------------------------- - // Write FIFO - //---------------------------------------------------------------------------- - assign WrFifo_RdEn = SYNC_done_dly && RDWR_B_reg && ~CS_B_reg && ~WrFifo_Empty && CCLK; - - async_fifo_8_8_128 WrFifo( .din( WrFifo_Din ), - .dout( WrFifo_Dout ), - .rd_clk( Sys_Clk ), - .rd_en( WrFifo_RdEn ), - .wr_clk( User_Clk ), - .wr_en( WrFifo_WrEn ), - .rst( User_Rst ), - .empty( WrFifo_Empty ), - .full( WrFifo_Full ), - .rd_data_count( WrFifo_RdCnt_int ), - .wr_data_count( WrFifo_WrCnt_int ) ); - - assign WrFifo_WrCnt = 8'd129 - WrFifo_WrCnt_int; - assign WrFifo_RdCnt = WrFifo_RdCnt_int; - - // ____ _ _ __ __ _ ____ // - // / ___| ___| | ___ ___| |_| \/ | / \ | _ \ // - // \___ \ / _ \ |/ _ \/ __| __| |\/| | / _ \ | |_) | // - // ___) | __/ | __/ (__| |_| | | |/ ___ \| __/ // - // |____/ \___|_|\___|\___|\__|_| |_/_/ \_\_| // - // // - - //---------------------------------------------------------------------------- - // SelectMAP control outputs - //---------------------------------------------------------------------------- - wire [0:7] DataCnt = RDWR_B_reg ? WrFifo_RdCnt : RdFifo_WrCnt; - - assign D_T = {8{(~RDWR_B & ~CS_B)}}; // stop driving if master is sending - - always @( posedge Sys_Clk ) - begin - D_O_reg <= CS_B_reg ? DataCnt : WrFifo_Dout; - INIT_B_reg <= WrFifo_Empty; - end - - //---------------------------------------------------------------------------- - -endmodule - module main - ( - // User clock ports - Clkin_p, - Clkin_m, - - // SelectMAP interface ports - D, // Data bus - RDWR_B, // Read/write signal - CS_B, // Chip select - INIT_B, // Initialization/interrupt signal - CCLK, // Local CCLK output - gpleds - ); - - // User clock/reset ports - input Clkin_p; - input Clkin_m; - - // SelectMAP protocol ports - inout [0:7] D; - input RDWR_B; - input CS_B; - output INIT_B; - output CCLK; - output [6:1] gpleds; - - - // Wires - wire CCLK_int; - - wire [0:31] LoopData; - wire [0:31] LoopDataW; - wire LoopEmpty; - wire LoopFull; - - wire [0:7] D_I; - wire [0:7] D_O; - wire [0:7] D_T; - - wire User_Clk; - wire User_Rst; - - reg [6:1] gpleds_reg; - - // synthesis attribute tig of activate_r is yes; - wire activate_r; - // synthesis attribute tig of activate_a is yes; - wire activate_a; - - wire [7:0] write_data; - wire write_enable; - wire write_full; - - wire [7:0] read_data; - wire read_empty; - wire [7:0] read_wire; - - reg [7:0] write_reg; - reg [7:0] read_reg; - - reg [7:0] read_in; - wire read_enable; - reg read_enable_reg; - reg write_enable_reg; + (sys_clk_pin, /* I think this is 100Mhz */ + sys_rst_pin, + fpga_0_RS232_Uart_1_ctsN_pin, + fpga_0_RS232_Uart_1_rtsN_pin, + fpga_0_RS232_Uart_1_sin_pin, + fpga_0_RS232_Uart_1_sout_pin + ); + + input sys_clk_pin; + input sys_rst_pin; + input fpga_0_RS232_Uart_1_ctsN_pin; + output fpga_0_RS232_Uart_1_rtsN_pin; + input fpga_0_RS232_Uart_1_sin_pin; + output fpga_0_RS232_Uart_1_sout_pin; + + wire clk; + assign clk = sys_clk_pin; + wire rst; + assign rst = sys_rst_pin; + + wire data_to_host_full; + wire data_to_host_write_enable; + wire [7:0] data_to_host; + + wire data_to_fleet_empty; + wire data_to_fleet_read_enable; + wire [7:0] data_to_fleet; + + reg we; + reg re; + reg [7:0] data_to_host_r; + +/* + assign data_to_host = data_to_host_r; + assign data_to_host_write_enable = we; + assign data_to_fleet_read_enable = re; + + reg [7:0] count; + initial count = 0; + initial we = 0; + initial re = 0; + initial data_to_host_r = 107; + always @(posedge clk) begin + if (re && !data_to_fleet_empty) begin + data_to_host_r <= data_to_fleet; + we <= 1; + end else begin + we <= 0; + end + if (data_to_host_full || data_to_fleet_empty) begin + re <= 0; + end else begin + re <= 1; + end + end +*/ + + wire ser_rst; + reg ser_rst_r; + initial ser_rst_r = 0; + assign ser_rst = rst & ser_rst_r; + + wire sio_ce; + wire sio_ce_x4; + sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4); + sasc_top sasc_top(clk, ser_rst, + fpga_0_RS232_Uart_1_sin_pin, + fpga_0_RS232_Uart_1_sout_pin, + fpga_0_RS232_Uart_1_ctsN_pin, + fpga_0_RS232_Uart_1_rtsN_pin, + sio_ce, + sio_ce_x4, + data_to_host, + data_to_fleet, + data_to_fleet_read_enable, + data_to_host_write_enable, + data_to_host_full, + data_to_fleet_empty); + + reg data_to_host_write_enable_reg; + reg data_to_fleet_read_enable_reg; reg root_out_a_reg; reg root_in_r_reg; @@ -324,171 +91,71 @@ module main wire root_out_r; wire [7:0] root_in_d; - root my_root(User_Clk, root_in_r, root_in_a, root_in_d, - root_out_r, root_out_a, write_data); - - assign root_out_a = root_out_a_reg; - assign root_in_r = root_in_r_reg; - assign read_enable = read_enable_reg; - assign write_enable = write_enable_reg; - assign root_in_d = root_in_d_reg; + root my_root(clk, + root_in_r, root_in_a, root_in_d, + root_out_r, root_out_a, data_to_host); +/* + fifo4 my_root(clk, + root_in_r, root_in_a, root_in_d, + root_out_r, root_out_a, data_to_host); +*/ + assign root_out_a = root_out_a_reg; + assign root_in_r = root_in_r_reg; + assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg; + assign data_to_host_write_enable = data_to_host_write_enable_reg; + assign root_in_d = root_in_d_reg; // fpga -> host - always @(posedge User_Clk) + always @(posedge clk) begin - write_enable_reg = 0; - if (root_out_r && !root_out_a_reg && !write_full) begin - write_enable_reg = 1; + data_to_host_write_enable_reg = 0; + if (root_out_r && !root_out_a_reg && !data_to_host_full) begin + data_to_host_write_enable_reg = 1; root_out_a_reg = 1; end else if (root_out_a_reg && !root_out_r) begin root_out_a_reg = 0; end - gpleds_reg[4] = write_enable_reg; - gpleds_reg[5] = root_out_r; - gpleds_reg[6] = root_out_a_reg; end + // awful hack to flush the superfluous null byte that seems to appear on bootup + reg [15:0] boot_counter; + // host -> fpga - always @(posedge User_Clk) + always @(posedge clk) begin - read_enable_reg = 0; - if (!read_empty && !root_in_r_reg && !root_in_a) begin - root_in_r_reg = 1; - root_in_d_reg = read_data; - read_enable_reg = 1; + ser_rst_r <= 1; +/* + if (boot_counter != 500) begin + data_to_fleet_read_enable_reg = 1; + if (sio_ce) begin + boot_counter <= boot_counter + 1; + end end else begin - if (root_in_a) begin - root_in_r_reg = 0; - end +*/ + data_to_fleet_read_enable_reg = 0; + if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin + root_in_r_reg = 1; + root_in_d_reg = data_to_fleet; + data_to_fleet_read_enable_reg = 1; + end else begin + if (root_in_a) begin + root_in_r_reg = 0; + end + end +/* end - gpleds_reg[1] = read_enable_reg; - gpleds_reg[2] = root_in_r_reg; - gpleds_reg[3] = root_in_a; +*/ end - assign gpleds = gpleds_reg; - initial begin - gpleds_reg = 0; + boot_counter = 0; root_in_r_reg = 0; root_in_d_reg = 0; root_out_a_reg = 0; - root_in_r_reg = 0; - read_enable_reg = 0; - read_reg = 0; - read_in = 255; + data_to_fleet_read_enable_reg = 0; + data_to_host_write_enable_reg = 0; end - - // IO buffers - OBUF obuf_cclk( .I( CCLK_int ), - .O( CCLK ) - ); - - IOBUF iobuf_d0( .I( D_O[0] ), - .IO( D[0] ), - .O( D_I[0] ), - .T( D_T[0] ) - ); - - IOBUF iobuf_d1( .I( D_O[1] ), - .IO( D[1] ), - .O( D_I[1] ), - .T( D_T[1] ) - ); - - IOBUF iobuf_d2( .I( D_O[2] ), - .IO( D[2] ), - .O( D_I[2] ), - .T( D_T[2] ) - ); - - IOBUF iobuf_d3( .I( D_O[3] ), - .IO( D[3] ), - .O( D_I[3] ), - .T( D_T[3] ) - ); - - IOBUF iobuf_d4( .I( D_O[4] ), - .IO( D[4] ), - .O( D_I[4] ), - .T( D_T[4] ) - ); - - IOBUF iobuf_d5( .I( D_O[5] ), - .IO( D[5] ), - .O( D_I[5] ), - .T( D_T[5] ) - ); - - IOBUF iobuf_d6( .I( D_O[6] ), - .IO( D[6] ), - .O( D_I[6] ), - .T( D_T[6] ) - ); - - IOBUF iobuf_d7( .I( D_O[7] ), - .IO( D[7] ), - .O( D_I[7] ), - .T( D_T[7] ) - ); - - // Clock buffer and reset - IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ), - .IB( Clkin_m ), - .O( User_Clk ) - ); - - wire [0:3] rst; - - FD rst0( .D( 1'b0 ), - .Q( rst[0] ), - .C( User_Clk ) - ); - defparam rst0.INIT = 1'b1; - - FD rst1( .D( rst[0] ), - .Q( rst[1] ), - .C( User_Clk ) - ); - defparam rst1.INIT = 1'b1; - - FD rst2( .D( rst[1] ), - .Q( rst[2] ), - .C( User_Clk ) - ); - defparam rst2.INIT = 1'b1; - - FD rst3( .D( rst[2] ), - .Q( rst[3] ), - .C( User_Clk ) - ); - defparam rst3.INIT = 1'b1; - - assign User_Rst = |rst; +endmodule - // FIFO module instantiation - user_fifo test_fifo( - .WrFifo_Din( write_data ), - .WrFifo_WrEn( write_enable ), - .WrFifo_Full( write_full ), - .WrFifo_WrCnt( ), - .RdFifo_Dout( read_data ), - .RdFifo_RdEn( read_enable ), - .RdFifo_Empty( read_empty ), - .RdFifo_RdCnt( ), - .User_Rst( User_Rst ), - .User_Clk( User_Clk ), - .Sys_Rst( User_Rst ), - .Sys_Clk( User_Clk ), - .D_I( D_I ), - .D_O( D_O ), - .D_T( D_T ), - .RDWR_B( RDWR_B ), - .CS_B( CS_B ), - .INIT_B( INIT_B ), - .CCLK( CCLK_int ) - ); - -endmodule diff --git a/src/edu/berkeley/fleet/fpga/main.xst b/src/edu/berkeley/fleet/fpga/main.xst index 2c77f83..2b62de5 100644 --- a/src/edu/berkeley/fleet/fpga/main.xst +++ b/src/edu/berkeley/fleet/fpga/main.xst @@ -1,4 +1,4 @@ set -tmpdir ./tmp set -xsthdpdir ./xst run --ifn main.prj -ifmt mixed -ofn main -ofmt NGC -p xc2vp70-6-ff1704 -top main -opt_mode Speed -opt_level 1 -iuc NO -lso main.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract Yes -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 1 -register_duplication YES -register_balancing No -slice_packing Yes -optimize_primitives Yes -tristate2logic Yes -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 +-ifn main.prj -ifmt mixed -ofn main -ofmt NGC -p xc4vfx60 -top main -opt_mode Speed -opt_level 1 -iuc NO -lso main.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract Yes -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 1 -register_duplication YES -register_balancing No -slice_packing Yes -optimize_primitives Yes -tristate2logic Yes -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 diff --git a/src/edu/berkeley/fleet/fpga/sasc_brg.v b/src/edu/berkeley/fleet/fpga/sasc_brg.v new file mode 100644 index 0000000..8dde36c --- /dev/null +++ b/src/edu/berkeley/fleet/fpga/sasc_brg.v @@ -0,0 +1,163 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Simple Baud Rate Generator //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/sasc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: sasc_brg.v,v 1.2 2002/11/08 15:22:49 rudi Exp $ +// +// $Date: 2002/11/08 15:22:49 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: sasc_brg.v,v $ +// Revision 1.2 2002/11/08 15:22:49 rudi +// +// Fixed a typo in brg +// +// Revision 1.1.1.1 2002/09/16 16:16:40 rudi +// Initial Checkin +// +// +// +// +// +// +// +// + +`include "timescale.v" + +/* + Baud rate Generator + ================== + + div0 - is the first stage divider + Set this to the desired number of cycles less two + div1 - is the second stage divider + Set this to the actual number of cycles + + Remember you have to generate a baud rate that is 4 higher than what + you really want. This is because of the DPLL in the RX section ... + + Example: + If your system clock is 50MHz and you want to generate a 9.6 Kbps baud rate: + 9600*4 = 38400KHz + 50MHz/38400KHz=1302 or 6*217 + set div0=4 (6-2) and set div1=217 + + 100MHz/38400KHz=2604 or 12*217 + set div0=10 (12-2) and set div1=217 + +*/ + +module sasc_brg(clk, rst, div0, div1, sio_ce, sio_ce_x4); +input clk; +input rst; +input [7:0] div0, div1; +output sio_ce, sio_ce_x4; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg [7:0] ps; +reg ps_clr; +reg [7:0] br_cnt; +reg br_clr; +reg sio_ce_x4_r; +reg [1:0] cnt; +reg sio_ce, sio_ce_x4; +reg sio_ce_r ; +reg sio_ce_x4_t; + +/////////////////////////////////////////////////////////////////// +// +// Boud Rate Generator +// + +// ----------------------------------------------------- +// Prescaler +always @(posedge clk) + if(!rst) ps <= #1 8'h0; + else + if(ps_clr) ps <= #1 8'h0; + else ps <= #1 ps + 8'h1; + +always @(posedge clk) + ps_clr <= #1 (ps == div0); // Desired number of cycles less 2 + +// ----------------------------------------------------- +// Oversampled Boud Rate (x4) +always @(posedge clk) + if(!rst) br_cnt <= #1 8'h0; + else + if(br_clr) br_cnt <= #1 8'h0; + else + if(ps_clr) br_cnt <= #1 br_cnt + 8'h1; + +always @(posedge clk) + br_clr <= #1 (br_cnt == div1); // Prciese number of PS cycles + +always @(posedge clk) + sio_ce_x4_r <= #1 br_clr; + +always @(posedge clk) + sio_ce_x4_t <= #1 !sio_ce_x4_r & br_clr; + +always @(posedge clk) + sio_ce_x4 <= #1 sio_ce_x4_t; + +// ----------------------------------------------------- +// Actual Boud rate +always @(posedge clk) + if(!rst) cnt <= #1 2'h0; + else + if(!sio_ce_x4_r & br_clr) cnt <= #1 cnt + 2'h1; + +always @(posedge clk) + sio_ce_r <= #1 (cnt == 2'h0); + +always @(posedge clk) + sio_ce <= #1 !sio_ce_r & (cnt == 2'h0); + +endmodule + diff --git a/src/edu/berkeley/fleet/fpga/sasc_fifo4.v b/src/edu/berkeley/fleet/fpga/sasc_fifo4.v new file mode 100644 index 0000000..6729f18 --- /dev/null +++ b/src/edu/berkeley/fleet/fpga/sasc_fifo4.v @@ -0,0 +1,139 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// FIFO 4 entries deep //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/sasc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: sasc_fifo4.v,v 1.1.1.1 2002/09/16 16:16:41 rudi Exp $ +// +// $Date: 2002/09/16 16:16:41 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: sasc_fifo4.v,v $ +// Revision 1.1.1.1 2002/09/16 16:16:41 rudi +// Initial Checkin +// +// +// +// +// +// + +`include "timescale.v" + +// 4 entry deep fast fifo +module sasc_fifo4(clk, rst, clr, din, we, dout, re, full, empty); + +input clk, rst; +input clr; +input [7:0] din; +input we; +output [7:0] dout; +input re; +output full, empty; + + +//////////////////////////////////////////////////////////////////// +// +// Local Wires +// + +reg [7:0] mem[0:3]; +reg [1:0] wp; +reg [1:0] rp; +wire [1:0] wp_p1; +wire [1:0] wp_p2; +wire [1:0] rp_p1; +wire full, empty; +reg gb; + +initial wp = 0; +initial rp = 0; +initial gb = 0; + +//////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk or negedge rst) + if(!rst) wp <= #1 2'h0; + else + if(clr) wp <= #1 2'h0; + else + if(we) wp <= #1 wp_p1; + +assign wp_p1 = wp + 2'h1; +assign wp_p2 = wp + 2'h2; + +always @(posedge clk or negedge rst) + if(!rst) rp <= #1 2'h0; + else + if(clr) rp <= #1 2'h0; + else + if(re) rp <= #1 rp_p1; + +assign rp_p1 = rp + 2'h1; + +// Fifo Output +assign dout = mem[ rp ]; + +// Fifo Input +always @(posedge clk) + if(we) mem[ wp ] <= #1 din; + +// Status +assign empty = (wp == rp) & !gb; +assign full = (wp == rp) & gb; + +// Guard Bit ... +always @(posedge clk) + if(!rst) gb <= #1 1'b0; + else + if(clr) gb <= #1 1'b0; + else + if((wp_p1 == rp) & we) gb <= #1 1'b1; + else + if(re) gb <= #1 1'b0; + +endmodule + + diff --git a/src/edu/berkeley/fleet/fpga/sasc_top.v b/src/edu/berkeley/fleet/fpga/sasc_top.v new file mode 100644 index 0000000..5fb2b52 --- /dev/null +++ b/src/edu/berkeley/fleet/fpga/sasc_top.v @@ -0,0 +1,316 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Simple Asynchronous Serial Comm. Device //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/sasc/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: sasc_top.v,v 1.2 2006/03/30 02:47:07 rudi Exp $ +// +// $Date: 2006/03/30 02:47:07 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: sasc_top.v,v $ +// Revision 1.2 2006/03/30 02:47:07 rudi +// Thanks to Darren O'Connor of SPEC, Inc. for fixing a bug +// with the DPLL and data alignment: +// +// You were right that it was a problem with the dpll. I found +// that it was possible to get two baud clocks (rx_sio_ce) during +// one bit period. I fixed the problem by delaying the input data +// signal with a shift register and using that in the equations +// for the "change" variable that controls the DPLL FSM. +// +// Revision 1.1.1.1 2002/09/16 16:16:42 rudi +// Initial Checkin +// +// +// +// +// +// +// +// + +`include "timescale.v" + +/* +Serial IO Interface +=============================== +RTS I Request To Send +CTS O Clear to send +TD I Transmit Data +RD O Receive Data +*/ + +module sasc_top( clk, rst, + + // SIO + rxd_i, txd_o, cts_i, rts_o, + + // External Baud Rate Generator + sio_ce, sio_ce_x4, + + // Internal Interface + din_i, dout_o, re_i, we_i, full_o, empty_o); + +input clk; +input rst; +input rxd_i; +output txd_o; +input cts_i; +output rts_o; +input sio_ce; +input sio_ce_x4; +input [7:0] din_i; +output [7:0] dout_o; +input re_i, we_i; +output full_o, empty_o; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter START_BIT = 1'b0, + STOP_BIT = 1'b1, + IDLE_BIT = 1'b1; + +wire [7:0] txd_p; +reg load; +reg load_r; +wire load_e; +reg [9:0] hold_reg; +wire txf_empty; +reg txd_o; +reg shift_en; +reg [3:0] tx_bit_cnt; +reg rxd_s, rxd_r; +wire start; +reg [3:0] rx_bit_cnt; +reg rx_go; +reg [9:0] rxr; +reg rx_valid, rx_valid_r; +wire rx_we; +wire rxf_full; +reg rts_o; +reg txf_empty_r; +reg shift_en_r; +reg rxd_r1, rxd_r2; +wire lock_en; +reg change; +reg rx_sio_ce_d, rx_sio_ce_r1, rx_sio_ce_r2, rx_sio_ce; +reg [1:0] dpll_state, dpll_next_state; +reg [5:0] rxd_dly; //New input delay used to ensure no baud clocks + // occur twice in one baud period +/////////////////////////////////////////////////////////////////// +// +// IO Fifo's +// + +sasc_fifo4 tx_fifo( .clk( clk ), + .rst( rst ), + .clr( 1'b0 ), + .din( din_i ), + .we( we_i ), + .dout( txd_p ), + .re( load_e ), + .full( full_o ), + .empty( txf_empty ) + ); + +sasc_fifo4 rx_fifo( .clk( clk ), + .rst( rst ), + .clr( 1'b0 ), + .din( rxr[9:2] ), + .we( rx_we ), + .dout( dout_o ), + .re( re_i ), + .full( rxf_full ), + .empty( empty_o ) + ); + +/////////////////////////////////////////////////////////////////// +// +// Transmit Logic +// +always @(posedge clk) + if(!rst) txf_empty_r <= #1 1'b1; + else + if(sio_ce) txf_empty_r <= #1 txf_empty; + +always @(posedge clk) + load <= #1 !txf_empty_r & !shift_en & !cts_i; + +always @(posedge clk) + load_r <= #1 load; + +assign load_e = load & sio_ce; + +always @(posedge clk) + if(load_e) hold_reg <= #1 {STOP_BIT, txd_p, START_BIT}; + else + if(shift_en & sio_ce) hold_reg <= #1 {IDLE_BIT, hold_reg[9:1]}; + +always @(posedge clk) + if(!rst) txd_o <= #1 IDLE_BIT; + else + if(sio_ce) + if(shift_en | shift_en_r) txd_o <= #1 hold_reg[0]; + else txd_o <= #1 IDLE_BIT; + +always @(posedge clk) + if(!rst) tx_bit_cnt <= #1 4'h9; + else + if(load_e) tx_bit_cnt <= #1 4'h0; + else + if(shift_en & sio_ce) tx_bit_cnt <= #1 tx_bit_cnt + 4'h1; + +always @(posedge clk) + shift_en <= #1 (tx_bit_cnt != 4'h9); + +always @(posedge clk) + if(!rst) shift_en_r <= #1 1'b0; + else + if(sio_ce) shift_en_r <= #1 shift_en; + +/////////////////////////////////////////////////////////////////// +// +// Recieve Logic +// + +always @(posedge clk) +begin + rxd_dly[5:1] <= #1 rxd_dly[4:0]; + rxd_dly[0] <= #1rxd_i; + rxd_s <= #1rxd_dly[5]; // rxd_s = delay 1 + rxd_r <= #1 rxd_s; // rxd_r = delay 2 +end + + +assign start = (rxd_r == IDLE_BIT) & (rxd_s == START_BIT); + +always @(posedge clk) + if(!rst) rx_bit_cnt <= #1 4'ha; + else + if(!rx_go & start) rx_bit_cnt <= #1 4'h0; + else + if(rx_go & rx_sio_ce) rx_bit_cnt <= #1 rx_bit_cnt + 4'h1; + +always @(posedge clk) + rx_go <= #1 (rx_bit_cnt != 4'ha); + +always @(posedge clk) + rx_valid <= #1 (rx_bit_cnt == 4'h9); + +always @(posedge clk) + rx_valid_r <= #1 rx_valid; + +assign rx_we = !rx_valid_r & rx_valid & !rxf_full; + +always @(posedge clk) + if(rx_go & rx_sio_ce) rxr <= {rxd_s, rxr[9:1]}; + +always @(posedge clk) + rts_o <= #1 rxf_full; + +/////////////////////////////////////////////////////////////////// +// +// Reciever DPLL +// + +// Uses 4x baud clock to lock to incoming stream + +// Edge detector +always @(posedge clk) + if(sio_ce_x4) rxd_r1 <= #1 rxd_s; + +always @(posedge clk) + if(sio_ce_x4) rxd_r2 <= #1 rxd_r1; + +always @(posedge clk) + if(!rst) + change <= #1 1'b0; + else if ((rxd_dly[1] != rxd_r1) || (rxd_dly[1] != rxd_s)) + change <= #1 1'b1; + else if(sio_ce_x4) + change <= #1 1'b0; + +// DPLL FSM +always @(posedge clk or negedge rst) + if(!rst) dpll_state <= #1 2'h1; + else + if(sio_ce_x4) dpll_state <= #1 dpll_next_state; + +always @(dpll_state or change) + begin + rx_sio_ce_d = 1'b0; + case(dpll_state) + 2'h0: + if(change) dpll_next_state = 3'h0; + else dpll_next_state = 3'h1; + 2'h1:begin + rx_sio_ce_d = 1'b1; + if(change) dpll_next_state = 3'h3; + else dpll_next_state = 3'h2; + end + 2'h2: + if(change) dpll_next_state = 3'h0; + else dpll_next_state = 3'h3; + 2'h3: + if(change) dpll_next_state = 3'h0; + else dpll_next_state = 3'h0; + endcase + end + +// Compensate for sync registers at the input - allign sio +// clock enable to be in the middle between two bit changes ... +always @(posedge clk) + rx_sio_ce_r1 <= #1 rx_sio_ce_d; + +always @(posedge clk) + rx_sio_ce_r2 <= #1 rx_sio_ce_r1; + +always @(posedge clk) + rx_sio_ce <= #1 rx_sio_ce_r1 & !rx_sio_ce_r2; + +endmodule + + diff --git a/src/edu/berkeley/fleet/fpga/timescale.v b/src/edu/berkeley/fleet/fpga/timescale.v new file mode 100644 index 0000000..ff9e265 --- /dev/null +++ b/src/edu/berkeley/fleet/fpga/timescale.v @@ -0,0 +1 @@ +`timescale 1ns / 10ps -- 1.7.10.4