From 30f7bb5b3132e52cf3a272cd14d9d3a1dd0f6c2a Mon Sep 17 00:00:00 2001
From: adam <adam@megacz.com>
Date: Mon, 10 Nov 2008 12:50:23 +0100
Subject: [PATCH] add Value.invertBits()

---
 src/edu/berkeley/fleet/fpga/verilog/Verilog.java |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index 711f107..9ad420d 100644
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -19,6 +19,7 @@ public class Verilog {
         public Assignable getAssignableBits(int high, int low) { return new SimpleValue(s, high, low); }
         public String getVerilogName() { return s; }
         public String toString() { return s; }
+        public Value invertBits() { return new SimpleValue("~("+getVerilogName()+")"); }
     }
 
     public static class CatValue implements Value {
@@ -45,6 +46,7 @@ public class Verilog {
             sb.append(" }");
             return sb.toString();
         }
+        public Value invertBits() { return new SimpleValue("~("+getVerilogName()+")"); }
     }
 
     public static interface Action {
@@ -72,6 +74,7 @@ public class Verilog {
         public String getVerilogName();
         public Value getBits(int high, int low);
         public Value getBits(Mask mask);
+        public Value invertBits();
     }
 
     public static class ConditionalAction implements Action {
@@ -105,6 +108,7 @@ public class Verilog {
         public SimpleAssignable(String s) { this.s = s; }
         public String getVerilogName() { return s; }
         public Assignable getAssignableBits(int high, int low) { return new SimpleValue(s, high, low); }
+        public Value invertBits() { return new SimpleValue("~("+getVerilogName()+")"); }
     }
 
     public static class AssignAction implements Action {
@@ -223,6 +227,7 @@ public class Verilog {
             public String getVerilogName() { return name; }
             public Value getBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
             public Value getBits(Mask mask) { return getBits(mask.valmaskmax, mask.valmaskmin); }
+            public Value invertBits() { return new SimpleValue("~("+getVerilogName()+")"); }
             public Assignable getAssignableBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
             public String doReset() { return name+"<="+initial+";"; }
             public void dump(PrintWriter pw) {
@@ -346,6 +351,7 @@ public class Verilog {
                 super(name, width, external); }
             public Value getBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
             public Value getBits(Mask mask) { return getBits(mask.valmaskmax, mask.valmaskmin); }
+            public Value invertBits() { return new SimpleValue("~("+getVerilogName()+")"); }
             public Assignable getAssignableBits(int high, int low) { return new SimpleValue(getVerilogName(), high, low); }
             public String getVerilogTrigger() { return " && " + getReq() + " && !"+getAck(); }
             public String getVerilogAction() { return getAck() + " <= 1;"; }
-- 
1.7.10.4