From 3b8f912f25e9387e08aabf0b9000648681063362 Mon Sep 17 00:00:00 2001 From: adam Date: Sun, 9 Nov 2008 03:13:35 +0100 Subject: [PATCH] institute Z-flag in FpgaDock --- src/edu/berkeley/fleet/fpga/FpgaDock.java | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/src/edu/berkeley/fleet/fpga/FpgaDock.java b/src/edu/berkeley/fleet/fpga/FpgaDock.java index 527b631..a83073a 100644 --- a/src/edu/berkeley/fleet/fpga/FpgaDock.java +++ b/src/edu/berkeley/fleet/fpga/FpgaDock.java @@ -167,11 +167,12 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { ship_in.hasLatch = true; } - Module.Latch ilc = new Latch("ilc", fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1, 1); - Module.Latch olc = new Latch("olc", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth, 1); + Module.Latch ilc = new Latch("ilc", fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1, 1); + Module.Latch olc = new Latch("olc", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth, 1); Module.Latch flag_a = new Latch("flag_a", 1); Module.Latch flag_b = new Latch("flag_b", 1); Module.Latch flag_c = new Latch("flag_c", 1); + Module.Latch flag_z = new Latch("flag_z", 1); Module.StateWire torpedoWaiting = new StateWire("torpedoWaiting", false); @@ -231,7 +232,7 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { "("+ fpga.P_ALWAYS.verilog(ondeck.getName())+ ") || ("+ - fpga.P_OLC_ZERO.verilog(ondeck.getName())+"==(olc==0)"+ + fpga.P_OLC_ZERO.verilog(ondeck.getName())+"==flag_z"+ ")"+ ") && ("+ " " + fpga.P_A.verilog(ondeck.getName())+" ? flag_a"+ @@ -255,8 +256,9 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { new Object[] { ondeck, torpedoWaiting.doDrain(), - new AssignAction(olc, "0"), - new AssignAction(ilc, "1") + new AssignAction(olc, "0"), + new AssignAction(flag_z, "1"), + new AssignAction(ilc, "1") }); // Predicate not met @@ -285,6 +287,11 @@ public class FpgaDock extends FleetTwoDock implements FabricElement { new AssignAction(olc, fpga.SET_OLC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))), new ConditionalAction(fpga.SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName()), new AssignAction(olc, "olc==0 ? 0 : decremented")), + + new ConditionalAction(fpga.SET_OLC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(flag_z, "0")), + new ConditionalAction(fpga.SET_OLC_FROM_IMMEDIATE.verilog(ondeck.getName()), new AssignAction(flag_z, "0")), + new ConditionalAction(fpga.SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName()), new AssignAction(flag_z, "(olc==0 || olc==1)")), + new ConditionalAction(fpga.SET_ILC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(ilc, "data_latch_output")), new ConditionalAction(fpga.SET_ILC_FROM_IMMEDIATE.verilog(ondeck.getName()), new AssignAction(ilc, fpga.SET_ILC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))), -- 1.7.10.4